diff options
| -rw-r--r-- | miasm2/arch/arm/arch.py | 25 | ||||
| -rw-r--r-- | miasm2/arch/arm/regs.py | 5 | ||||
| -rw-r--r-- | miasm2/arch/arm/sem.py | 9 | ||||
| -rw-r--r-- | miasm2/jitter/arch/JitCore_arm.h | 1 | ||||
| -rw-r--r-- | test/arch/arm/arch.py | 4 |
5 files changed, 39 insertions, 5 deletions
diff --git a/miasm2/arch/arm/arch.py b/miasm2/arch/arm/arch.py index e14549ec..9906c94e 100644 --- a/miasm2/arch/arm/arch.py +++ b/miasm2/arch/arm/arch.py @@ -920,6 +920,26 @@ class arm_imm_4_12(m_arg): return True +class arm_imm_12_4(m_arg): + parser = base_expr + + def decode(self, v): + v = v & self.lmask + imm = (self.parent.imm.value << 4) | v + self.expr = ExprInt32(imm) + return True + + def encode(self): + if not isinstance(self.expr, ExprInt): + return False + v = int(self.expr.arg) + if v > 0xffff: + return False + self.parent.imm.value = (v >> 4) & 0xfff + self.value = v & 0xf + return True + + class arm_op2(m_arg): parser = shift_off @@ -1321,6 +1341,9 @@ imm4_noarg = bs(l=4, fname="imm4") imm_4_12 = bs(l=12, cls=(arm_imm_4_12,)) +imm12_noarg = bs(l=12, fname="imm") +imm_12_4 = bs(l=4, cls=(arm_imm_12_4,)) + lowb = bs(l=1, fname='lowb') offs_blx = bs(l=24, cls=(arm_offs_blx,), fname="offs") @@ -1580,7 +1603,7 @@ armop("cdata", [bs('110'), ppi, updown, tl, wback_no_t, bs_ctransfer_name, rn_noarg, crd, cpnum, imm8_12], [cpnum, crd, imm8_12]) armop("mr", [bs('1110'), cpopc, bs_mr_name, crn, rd, cpnum, cp, bs('1'), crm], [cpnum, cpopc, rd, crn, crm, cp]) -armop("bkpt", [bs('00010010'), imm12, bs('0111'), imm4]) +armop("bkpt", [bs('00010010'), imm12_noarg, bs('0111'), imm_12_4]) armop("bx", [bs('000100101111111111110001'), rn]) armop("mov", [bs('00110000'), imm4_noarg, rd, imm_4_12], [rd, imm_4_12]) armop("movt", [bs('00110100'), imm4_noarg, rd, imm_4_12], [rd, imm_4_12]) diff --git a/miasm2/arch/arm/regs.py b/miasm2/arch/arm/regs.py index 2b31da38..1393c372 100644 --- a/miasm2/arch/arm/regs.py +++ b/miasm2/arch/arm/regs.py @@ -10,6 +10,7 @@ regs32_str = ["R%d" % i for i in xrange(13)] + ["SP", "LR", "PC"] regs32_expr = [ExprId(x, 32) for x in regs32_str] exception_flags = ExprId('exception_flags', 32) +bp_num = ExprId('bp_num', 32) R0 = regs32_expr[0] @@ -66,7 +67,7 @@ cf_init = ExprId("cf_init", size=1) all_regs_ids = [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, SP, LR, PC, zf, nf, of, cf, - exception_flags + exception_flags, bp_num ] all_regs_ids_no_alias = all_regs_ids @@ -78,7 +79,7 @@ all_regs_ids_init = [R0_init, R1_init, R2_init, R3_init, R8_init, R9_init, R10_init, R11_init, R12_init, SP_init, LR_init, PC_init, zf_init, nf_init, of_init, cf_init, - ExprInt32(0) + ExprInt32(0), ExprInt32(0) ] regs_init = {} diff --git a/miasm2/arch/arm/sem.py b/miasm2/arch/arm/sem.py index be44061e..1b7ad47f 100644 --- a/miasm2/arch/arm/sem.py +++ b/miasm2/arch/arm/sem.py @@ -5,6 +5,7 @@ from miasm2.arch.arm.regs import * # liris.cnrs.fr/~mmrissa/lib/exe/fetch.php?media=armv7-a-r-manual.pdf +EXCEPT_SOFT_BP = (1 << 1) EXCEPT_PRIV_INSN = (1 << 17) @@ -948,6 +949,13 @@ def uxtab(ir, instr, a, b, c): return e +def bkpt(ir, instr, a): + e = [] + e.append(ExprAff(exception_flags, ExprInt32(EXCEPT_SOFT_BP))) + e.append(ExprAff(bp_num, a)) + return e + + COND_EQ = 0 COND_NE = 1 @@ -1093,6 +1101,7 @@ mnemo_condm0 = {'add': add, 'rev': rev, 'clz': clz, 'uxtab': uxtab, + 'bkpt': bkpt, } mnemo_condm1 = {'adds': add, diff --git a/miasm2/jitter/arch/JitCore_arm.h b/miasm2/jitter/arch/JitCore_arm.h index dda8a65d..66d17604 100644 --- a/miasm2/jitter/arch/JitCore_arm.h +++ b/miasm2/jitter/arch/JitCore_arm.h @@ -26,6 +26,7 @@ typedef struct { uint32_t of; uint32_t cf; + uint32_t bp_num; }vm_cpu_t; diff --git a/test/arch/arm/arch.py b/test/arch/arm/arch.py index 6b010d20..d2022238 100644 --- a/test/arch/arm/arch.py +++ b/test/arch/arm/arch.py @@ -151,8 +151,8 @@ reg_tests_arm = [ "7420696e"), #("xxxxxxxx UND 0x0, 0x0", # "100000e6"), - ("xxxxxxxx BKPT 0x0, 0x0", - "700020e1"), + ('XXXXXXXX BKPT 0x1234', + '742321e1'), ("c00d153c LDRH R2, [R4, 0xCA]", "ba2cd4e1"), ("c00d18a8 LDRH R6, [R12]", |