diff options
| -rw-r--r-- | miasm2/arch/x86/arch.py | 29 | ||||
| -rw-r--r-- | miasm2/arch/x86/sem.py | 37 | ||||
| -rw-r--r-- | test/arch/x86/arch.py | 27 |
3 files changed, 91 insertions, 2 deletions
diff --git a/miasm2/arch/x86/arch.py b/miasm2/arch/x86/arch.py index d364bc32..daa68ced 100644 --- a/miasm2/arch/x86/arch.py +++ b/miasm2/arch/x86/arch.py @@ -2270,8 +2270,11 @@ class x86_rm_mm(x86_rm_m80): p = self.parent xx = self.get_modrm() expr = modrm2expr(xx, p, 0, 0, self.is_xmm, self.is_mm) - if isinstance(expr, ExprMem) and expr.size != self.msize: - expr = ExprMem(expr.arg, self.msize) + if isinstance(expr, ExprMem): + if self.msize is None: + return False + if expr.size != self.msize: + expr = ExprMem(expr.arg, self.msize) self.expr = expr return True @@ -2319,6 +2322,11 @@ class x86_rm_xmm_m64(x86_rm_mm): is_xmm = True +class x86_rm_xmm_reg(x86_rm_mm): + msize = None + is_mm = False + is_xmm = True + class x86_rm_reg_noarg(object): prio = default_prio + 1 @@ -3130,6 +3138,7 @@ rm_arg_mm_m64 = bs(l=0, cls=(x86_rm_mm_m64,), fname='rmarg') rm_arg_xmm = bs(l=0, cls=(x86_rm_xmm,), fname='rmarg') rm_arg_xmm_m32 = bs(l=0, cls=(x86_rm_xmm_m32,), fname='rmarg') rm_arg_xmm_m64 = bs(l=0, cls=(x86_rm_xmm_m64,), fname='rmarg') +rm_arg_xmm_reg = bs(l=0, cls=(x86_rm_xmm_reg,), fname='rmarg') swapargs = bs_swapargs(l=1, fname="swap", mn_mod=range(1 << 1)) @@ -3858,6 +3867,22 @@ addop("movdqu", [bs8(0x0f), bs("011"), swapargs, bs("1111"), pref_f3] addop("movdqa", [bs8(0x0f), bs("011"), swapargs, bs("1111"), pref_66] + rmmod(xmm_reg, rm_arg_xmm), [xmm_reg, rm_arg_xmm]) +addop("movhpd", [bs8(0x0f), bs("0001011"), swapargs, pref_66] + + rmmod(xmm_reg, rm_arg_m64), [xmm_reg, rm_arg_m64]) +addop("movhps", [bs8(0x0f), bs("0001011"), swapargs, no_xmm_pref] + + rmmod(xmm_reg, rm_arg_m64), [xmm_reg, rm_arg_m64]) +addop("movlpd", [bs8(0x0f), bs("0001001"), swapargs, pref_66] + + rmmod(xmm_reg, rm_arg_m64), [xmm_reg, rm_arg_m64]) +addop("movlps", [bs8(0x0f), bs("0001001"), swapargs, no_xmm_pref] + + rmmod(xmm_reg, rm_arg_m64), [xmm_reg, rm_arg_m64]) + +addop("movhlps", [bs8(0x0f), bs8(0x12), no_xmm_pref] + + rmmod(xmm_reg, rm_arg_xmm_reg), [xmm_reg, rm_arg_xmm_reg]) +addop("movlhps", [bs8(0x0f), bs8(0x16), no_xmm_pref] + + rmmod(xmm_reg, rm_arg_xmm_reg), [xmm_reg, rm_arg_xmm_reg]) + +addop("movdq2q", [bs8(0x0f), bs8(0xd6), pref_f2] + + rmmod(mm_reg, rm_arg_xmm_reg), [mm_reg, rm_arg_xmm_reg]) ## Additions diff --git a/miasm2/arch/x86/sem.py b/miasm2/arch/x86/sem.py index 6501d0ff..b4b03ac7 100644 --- a/miasm2/arch/x86/sem.py +++ b/miasm2/arch/x86/sem.py @@ -3867,6 +3867,34 @@ def unpcklpd(ir, instr, a, b): return e, [] +def movlpd(ir, instr, a, b): + e = [] + e.append(m2_expr.ExprAff(a[:64], b[:64])) + return e, [] + + +def movlps(ir, instr, a, b): + e = [] + e.append(m2_expr.ExprAff(a[:64], b[:64])) + return e, [] + + +def movhpd(ir, instr, a, b): + e = [] + e.append(m2_expr.ExprAff(a[64:128], b[:64])) + return e, [] + + +def movhps(ir, instr, a, b): + e = [] + e.append(m2_expr.ExprAff(a[64:128], b[:64])) + return e, [] + +def movdq2q(ir, instr, a, b): + e = [] + e.append(m2_expr.ExprAff(a, b[:64])) + return e, [] + mnemo_func = {'mov': mov, 'xchg': xchg, 'movzx': movzx, @@ -4328,6 +4356,15 @@ mnemo_func = {'mov': mov, "unpcklps": unpcklps, "unpcklpd": unpcklpd, + "movlpd": movlpd, + "movlps": movlps, + "movhpd": movhpd, + "movhps": movhps, + "movlhps": movhps, + "movhlps": movlps, + "movdq2q": movdq2q, + + } diff --git a/test/arch/x86/arch.py b/test/arch/x86/arch.py index a00c33cf..93668fd0 100644 --- a/test/arch/x86/arch.py +++ b/test/arch/x86/arch.py @@ -2238,6 +2238,33 @@ reg_tests = [ (m32, "00000000 MOVAPD XMMWORD PTR [EBP+0xFFFFFFB8], XMM0", "660f2945b8"), + + (m32, "00000000 MOVLPD XMM0, QWORD PTR [ESP+0x4]", + "660F12442404"), + (m32, "00000000 MOVLPS XMM0, QWORD PTR [ESP+0x4]", + "0F12442404"), + (m32, "00000000 MOVLPD QWORD PTR [ESP+0x4], XMM0", + "660F13442404"), + (m32, "00000000 MOVLPS QWORD PTR [ESP+0x4], XMM0", + "0F13442404"), + + (m32, "00000000 MOVHPD XMM0, QWORD PTR [ESP+0x4]", + "660F16442404"), + (m32, "00000000 MOVHPS XMM0, QWORD PTR [ESP+0x4]", + "0F16442404"), + (m32, "00000000 MOVHPD QWORD PTR [ESP+0x4], XMM0", + "660F17442404"), + (m32, "00000000 MOVHPS QWORD PTR [ESP+0x4], XMM0", + "0F17442404"), + + (m32, "00000000 MOVLHPS XMM2, XMM1", + "0F16D1"), + (m32, "00000000 MOVHLPS XMM2, XMM1", + "0F12D1"), + + (m32, "00000000 MOVDQ2Q MM2, XMM1", + "F20Fd6D1"), + (m32, "00000000 MOVUPS XMM2, XMMWORD PTR [ECX]", "0f1011"), (m32, "00000000 MOVSD XMM2, QWORD PTR [ECX]", |