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-rw-r--r--miasm2/arch/arm/arch.py1
-rw-r--r--miasm2/arch/arm/sem.py10
-rw-r--r--test/arch/arm/arch.py3
3 files changed, 14 insertions, 0 deletions
diff --git a/miasm2/arch/arm/arch.py b/miasm2/arch/arm/arch.py
index a70718d9..41c99d4d 100644
--- a/miasm2/arch/arm/arch.py
+++ b/miasm2/arch/arm/arch.py
@@ -1520,6 +1520,7 @@ armop("uxth", [bs('01101111'), bs('1111'), rd, rot_rm, bs('00'), bs('0111'), rm_
 armop("sxtb", [bs('01101010'), bs('1111'), rd, rot_rm, bs('00'), bs('0111'), rm_noarg])
 armop("sxth", [bs('01101011'), bs('1111'), rd, rot_rm, bs('00'), bs('0111'), rm_noarg])
 
+armop("rev", [bs('01101011'), bs('1111'), rd, bs('1111'), bs('0011'), rm])
 
 class arm_widthm1(arm_imm, m_arg):
     def decode(self, v):
diff --git a/miasm2/arch/arm/sem.py b/miasm2/arch/arm/sem.py
index bbab8d59..678f10a8 100644
--- a/miasm2/arch/arm/sem.py
+++ b/miasm2/arch/arm/sem.py
@@ -924,6 +924,15 @@ def bfc(ir, instr, a, b, c):
         e.append(ExprAff(ir.IRDst, r))
     return e
 
+def rev(ir, instr, a, b):
+    e = []
+    c = ExprCompose([(b[:8],      24, 32),
+                     (b[8:16],    16, 24),
+                     (b[16:24],   8, 16),
+                     (b[24:32],   0, 8)])
+    e.append(ExprAff(a, c))
+    return e
+
 
 
 COND_EQ = 0
@@ -1067,6 +1076,7 @@ mnemo_condm0 = {'add': add,
                 'sxth': sxth,
                 'ubfx': ubfx,
                 'bfc': bfc,
+                'rev': rev,
                 }
 
 mnemo_condm1 = {'adds': add,
diff --git a/test/arch/arm/arch.py b/test/arch/arm/arch.py
index 701c45af..2ffbd3b1 100644
--- a/test/arch/arm/arch.py
+++ b/test/arch/arm/arch.py
@@ -242,6 +242,9 @@ reg_tests_arm = [
     ("XXXXXXXX    BFC        R0, 0x0, 0xD",
      "1f00cce7"),
 
+    ("XXXXXXXX    REV        R0, R2",
+     "320FBFE6"),
+
 
 ]
 ts = time.time()