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-rw-r--r--miasm2/arch/x86/sem.py35
-rw-r--r--miasm2/jitter/arch/JitCore_x86.c23
-rw-r--r--test/arch/x86/unit/mn_cdq.py445
-rwxr-xr-xtest/test_all.py1
4 files changed, 489 insertions, 15 deletions
diff --git a/miasm2/arch/x86/sem.py b/miasm2/arch/x86/sem.py
index 56aca1c2..deebba8c 100644
--- a/miasm2/arch/x86/sem.py
+++ b/miasm2/arch/x86/sem.py
@@ -1614,22 +1614,25 @@ def imul(_, instr, src1, src2=None, src3=None):
 
 
 def cbw(_, instr):
+    # Only in 16 bit
     e = []
-    tempAL = mRAX[instr.mode][:8]
-    tempAX = mRAX[instr.mode][:16]
+    tempAL = mRAX[instr.v_opmode()][:8]
+    tempAX = mRAX[instr.v_opmode()][:16]
     e.append(m2_expr.ExprAff(tempAX, tempAL.signExtend(16)))
     return e, []
 
 
 def cwde(_, instr):
+    # Only in 32/64 bit
     e = []
-    tempAX = mRAX[instr.mode][:16]
-    tempEAX = mRAX[instr.mode][:32]
+    tempAX = mRAX[instr.v_opmode()][:16]
+    tempEAX = mRAX[instr.v_opmode()][:32]
     e.append(m2_expr.ExprAff(tempEAX, tempAX.signExtend(32)))
     return e, []
 
 
 def cdqe(_, instr):
+    # Only in 64 bit
     e = []
     tempEAX = mRAX[instr.mode][:32]
     tempRAX = mRAX[instr.mode][:64]
@@ -1638,32 +1641,34 @@ def cdqe(_, instr):
 
 
 def cwd(_, instr):
+    # Only in 16 bit
     e = []
     tempAX = mRAX[instr.mode][:16]
     tempDX = mRDX[instr.mode][:16]
-    c = tempAX.signExtend(32)
-    e.append(m2_expr.ExprAff(tempAX, c[:16]))
-    e.append(m2_expr.ExprAff(tempDX, c[16:32]))
+    result = tempAX.signExtend(32)
+    e.append(m2_expr.ExprAff(tempAX, result[:16]))
+    e.append(m2_expr.ExprAff(tempDX, result[16:32]))
     return e, []
 
 
 def cdq(_, instr):
+    # Only in 32/64 bit
     e = []
-    tempEAX = mRAX[instr.mode][:32]
-    tempEDX = mRDX[instr.mode][:32]
-    c = tempEAX.signExtend(64)
-    e.append(m2_expr.ExprAff(tempEAX, c[:32]))
-    e.append(m2_expr.ExprAff(tempEDX, c[32:64]))
+    tempEAX = mRAX[instr.v_opmode()]
+    tempEDX = mRDX[instr.v_opmode()]
+    result = tempEAX.signExtend(64)
+    e.append(m2_expr.ExprAff(tempEDX, result[32:64]))
     return e, []
 
 
 def cqo(_, instr):
+    # Only in 64 bit
     e = []
     tempRAX = mRAX[instr.mode][:64]
     tempRDX = mRDX[instr.mode][:64]
-    c = tempRAX.signExtend(128)
-    e.append(m2_expr.ExprAff(tempRAX, c[:64]))
-    e.append(m2_expr.ExprAff(tempRDX, c[64:128]))
+    result = tempRAX.signExtend(128)
+    e.append(m2_expr.ExprAff(tempRAX, result[:64]))
+    e.append(m2_expr.ExprAff(tempRDX, result[64:128]))
     return e, []
 
 
diff --git a/miasm2/jitter/arch/JitCore_x86.c b/miasm2/jitter/arch/JitCore_x86.c
index 3198eff3..407a01c7 100644
--- a/miasm2/jitter/arch/JitCore_x86.c
+++ b/miasm2/jitter/arch/JitCore_x86.c
@@ -178,6 +178,29 @@ PyObject * cpu_init_regs(JitCpu* self)
 
 }
 
+void dump_gpregs_16(vm_cpu_t* vmcpu)
+{
+
+	printf("EAX %.8"PRIX32" EBX %.8"PRIX32" ECX %.8"PRIX32" EDX %.8"PRIX32" ",
+	       (uint32_t)(vmcpu->RAX & 0xFFFFFFFF),
+	       (uint32_t)(vmcpu->RBX & 0xFFFFFFFF),
+	       (uint32_t)(vmcpu->RCX & 0xFFFFFFFF),
+	       (uint32_t)(vmcpu->RDX & 0xFFFFFFFF));
+	printf("ESI %.8"PRIX32" EDI %.8"PRIX32" ESP %.8"PRIX32" EBP %.8"PRIX32" ",
+	       (uint32_t)(vmcpu->RSI & 0xFFFFFFFF),
+	       (uint32_t)(vmcpu->RDI & 0xFFFFFFFF),
+	       (uint32_t)(vmcpu->RSP & 0xFFFFFFFF),
+	       (uint32_t)(vmcpu->RBP & 0xFFFFFFFF));
+	printf("EIP %.8"PRIX32" ",
+	       (uint32_t)(vmcpu->RIP & 0xFFFFFFFF));
+	printf("zf %.1"PRIX32" nf %.1"PRIX32" of %.1"PRIX32" cf %.1"PRIX32"\n",
+	       (uint32_t)(vmcpu->zf & 0x1),
+	       (uint32_t)(vmcpu->nf & 0x1),
+	       (uint32_t)(vmcpu->of & 0x1),
+	       (uint32_t)(vmcpu->cf & 0x1));
+
+}
+
 void dump_gpregs_32(vm_cpu_t* vmcpu)
 {
 
diff --git a/test/arch/x86/unit/mn_cdq.py b/test/arch/x86/unit/mn_cdq.py
new file mode 100644
index 00000000..f4e4d6e7
--- /dev/null
+++ b/test/arch/x86/unit/mn_cdq.py
@@ -0,0 +1,445 @@
+#! /usr/bin/env python2
+
+import sys
+
+from asm_test import Asm_Test_16, Asm_Test_32, Asm_Test_64
+from miasm2.core.utils import pck16, pck32
+
+
+class Test_CBW_16(Asm_Test_16):
+    MYSTRING = "test CBW 16"
+
+    def prepare(self):
+        self.myjit.ir_arch.symbol_pool.add_label("lbl_ret", self.ret_addr)
+
+    def test_init(self):
+        self.myjit.cpu.EAX = 0x87654321
+        self.myjit.cpu.EDX = 0x11223344
+
+    TXT = '''
+    main:
+       CBW
+       JMP lbl_ret
+    '''
+
+    def check(self):
+        assert self.myjit.cpu.EAX == 0x87650021
+        assert self.myjit.cpu.EDX == 0x11223344
+
+
+class Test_CBW_16_signed(Asm_Test_16):
+    MYSTRING = "test CBW 16 signed"
+
+    def prepare(self):
+        self.myjit.ir_arch.symbol_pool.add_label("lbl_ret", self.ret_addr)
+
+    def test_init(self):
+        self.myjit.cpu.EAX = 0x87654381
+        self.myjit.cpu.EDX = 0x11223344
+
+    TXT = '''
+    main:
+       CBW
+       JMP lbl_ret
+    '''
+
+    def check(self):
+        assert self.myjit.cpu.EAX == 0x8765FF81
+        assert self.myjit.cpu.EDX == 0x11223344
+
+
+class Test_CBW_32(Asm_Test_32):
+    MYSTRING = "test CBW 32"
+
+    def prepare(self):
+        self.myjit.ir_arch.symbol_pool.add_label("lbl_ret", self.ret_addr)
+
+    def test_init(self):
+        self.myjit.cpu.EAX = 0x87654321
+        self.myjit.cpu.EDX = 0x11223344
+
+    TXT = '''
+    main:
+       CBW
+       JMP lbl_ret
+    '''
+
+    def check(self):
+        assert self.myjit.cpu.EAX == 0x87650021
+        assert self.myjit.cpu.EDX == 0x11223344
+
+
+class Test_CBW_32_signed(Asm_Test_32):
+    MYSTRING = "test CBW 32 signed"
+
+    def prepare(self):
+        self.myjit.ir_arch.symbol_pool.add_label("lbl_ret", self.ret_addr)
+
+    def test_init(self):
+        self.myjit.cpu.EAX = 0x87654381
+        self.myjit.cpu.EDX = 0x11223344
+
+    TXT = '''
+    main:
+       CBW
+       JMP lbl_ret
+    '''
+
+    def check(self):
+        assert self.myjit.cpu.EAX == 0x8765FF81
+        assert self.myjit.cpu.EDX == 0x11223344
+
+
+class Test_CDQ_32(Asm_Test_32):
+    MYSTRING = "test cdq 32"
+
+    def prepare(self):
+        self.myjit.ir_arch.symbol_pool.add_label("lbl_ret", self.ret_addr)
+
+    def test_init(self):
+        self.myjit.cpu.EAX = 0x77654321
+        self.myjit.cpu.EDX = 0x11223344
+
+    TXT = '''
+    main:
+       CDQ
+       JMP lbl_ret
+    '''
+
+    def check(self):
+        assert self.myjit.cpu.EAX == 0x77654321
+        assert self.myjit.cpu.EDX == 0x0
+
+
+class Test_CDQ_32_signed(Asm_Test_32):
+    MYSTRING = "test cdq 32 signed"
+
+    def prepare(self):
+        self.myjit.ir_arch.symbol_pool.add_label("lbl_ret", self.ret_addr)
+
+    def test_init(self):
+        self.myjit.cpu.EAX = 0x87654321
+        self.myjit.cpu.EDX = 0x11223344
+
+    TXT = '''
+    main:
+       CDQ
+       JMP lbl_ret
+    '''
+
+    def check(self):
+        assert self.myjit.cpu.EAX == 0x87654321
+        assert self.myjit.cpu.EDX == 0xFFFFFFFF
+
+
+class Test_CDQ_64(Asm_Test_64):
+    MYSTRING = "test cdq 64"
+
+    def prepare(self):
+        self.myjit.ir_arch.symbol_pool.add_label("lbl_ret", self.ret_addr)
+
+    def test_init(self):
+        self.myjit.cpu.RAX = 0x1234567877654321
+        self.myjit.cpu.RDX = 0x1122334455667788
+
+    TXT = '''
+    main:
+       CDQ
+       JMP lbl_ret
+    '''
+
+    def check(self):
+        assert self.myjit.cpu.RAX == 0x1234567877654321
+        assert self.myjit.cpu.RDX == 0x0
+
+
+class Test_CDQ_64_signed(Asm_Test_64):
+    MYSTRING = "test cdq 64 signed"
+
+    def prepare(self):
+        self.myjit.ir_arch.symbol_pool.add_label("lbl_ret", self.ret_addr)
+
+    def test_init(self):
+        self.myjit.cpu.RAX = 0x1234567887654321
+        self.myjit.cpu.RDX = 0x1122334455667788
+
+    TXT = '''
+    main:
+       CDQ
+       JMP lbl_ret
+    '''
+
+    def check(self):
+        assert self.myjit.cpu.RAX == 0x1234567887654321
+        assert self.myjit.cpu.RDX == 0x00000000FFFFFFFF
+
+
+class Test_CDQE_64(Asm_Test_64):
+    MYSTRING = "test cdq 64"
+
+    def prepare(self):
+        self.myjit.ir_arch.symbol_pool.add_label("lbl_ret", self.ret_addr)
+
+    def test_init(self):
+        self.myjit.cpu.RAX = 0x1234567877654321
+        self.myjit.cpu.RDX = 0x1122334455667788
+
+    TXT = '''
+    main:
+       CDQE
+       JMP lbl_ret
+    '''
+
+    def check(self):
+        assert self.myjit.cpu.RAX == 0x77654321
+        assert self.myjit.cpu.RDX == 0x1122334455667788
+
+
+class Test_CDQE_64_signed(Asm_Test_64):
+    MYSTRING = "test cdq 64 signed"
+
+    def prepare(self):
+        self.myjit.ir_arch.symbol_pool.add_label("lbl_ret", self.ret_addr)
+
+    def test_init(self):
+        self.myjit.cpu.RAX = 0x1234567887654321
+        self.myjit.cpu.RDX = 0x1122334455667788
+
+    TXT = '''
+    main:
+       CDQE
+       JMP lbl_ret
+    '''
+
+    def check(self):
+        assert self.myjit.cpu.RAX == 0xFFFFFFFF87654321
+        assert self.myjit.cpu.RDX == 0x1122334455667788
+
+
+class Test_CWD_32(Asm_Test_32):
+    MYSTRING = "test cdq 32"
+
+    def prepare(self):
+        self.myjit.ir_arch.symbol_pool.add_label("lbl_ret", self.ret_addr)
+
+    def test_init(self):
+        self.myjit.cpu.EAX = 0x87654321
+        self.myjit.cpu.EDX = 0x12345678
+
+    TXT = '''
+    main:
+       CWD
+       JMP lbl_ret
+    '''
+
+    def check(self):
+        assert self.myjit.cpu.RAX == 0x87654321
+        assert self.myjit.cpu.RDX == 0x12340000
+
+
+class Test_CWD_32_signed(Asm_Test_32):
+    MYSTRING = "test cdq 32"
+
+    def prepare(self):
+        self.myjit.ir_arch.symbol_pool.add_label("lbl_ret", self.ret_addr)
+
+    def test_init(self):
+        self.myjit.cpu.EAX = 0x87658321
+        self.myjit.cpu.EDX = 0x12345678
+
+    TXT = '''
+    main:
+       CWD
+       JMP lbl_ret
+    '''
+
+    def check(self):
+        assert self.myjit.cpu.RAX == 0x87658321
+        assert self.myjit.cpu.RDX == 0x1234FFFF
+
+
+class Test_CWD_32(Asm_Test_32):
+    MYSTRING = "test cdq 32"
+
+    def prepare(self):
+        self.myjit.ir_arch.symbol_pool.add_label("lbl_ret", self.ret_addr)
+
+    def test_init(self):
+        self.myjit.cpu.EAX = 0x87654321
+        self.myjit.cpu.EDX = 0x12345678
+
+    TXT = '''
+    main:
+       CWD
+       JMP lbl_ret
+    '''
+
+    def check(self):
+        assert self.myjit.cpu.RAX == 0x87654321
+        assert self.myjit.cpu.RDX == 0x12340000
+
+
+class Test_CWDE_32(Asm_Test_32):
+    MYSTRING = "test cwde 32"
+
+    def prepare(self):
+        self.myjit.ir_arch.symbol_pool.add_label("lbl_ret", self.ret_addr)
+
+    def test_init(self):
+        self.myjit.cpu.EAX = 0x87654321
+        self.myjit.cpu.EDX = 0x11223344
+
+    TXT = '''
+    main:
+       CWDE
+       JMP lbl_ret
+    '''
+
+    def check(self):
+        assert self.myjit.cpu.RAX == 0x4321
+        assert self.myjit.cpu.RDX == 0x11223344
+
+
+class Test_CWDE_32_signed(Asm_Test_32):
+    MYSTRING = "test cwde 32 signed"
+
+    def prepare(self):
+        self.myjit.ir_arch.symbol_pool.add_label("lbl_ret", self.ret_addr)
+
+    def test_init(self):
+        self.myjit.cpu.RAX = 0x87658321
+        self.myjit.cpu.RDX = 0x11223344
+
+    TXT = '''
+    main:
+       CWDE
+       JMP lbl_ret
+    '''
+
+    def check(self):
+        assert self.myjit.cpu.EAX == 0xFFFF8321
+        assert self.myjit.cpu.RDX == 0x11223344
+
+
+class Test_CWDE_64(Asm_Test_64):
+    MYSTRING = "test cwde 64"
+
+    def prepare(self):
+        self.myjit.ir_arch.symbol_pool.add_label("lbl_ret", self.ret_addr)
+
+    def test_init(self):
+        self.myjit.cpu.RAX = 0x1234567887654321
+        self.myjit.cpu.RDX = 0x1122334455667788
+
+    TXT = '''
+    main:
+       CWDE
+       JMP lbl_ret
+    '''
+
+    def check(self):
+        assert self.myjit.cpu.RAX == 0x4321
+        assert self.myjit.cpu.RDX == 0x1122334455667788
+
+
+class Test_CWDE_64_signed(Asm_Test_64):
+    MYSTRING = "test cwde 64 signed"
+
+    def prepare(self):
+        self.myjit.ir_arch.symbol_pool.add_label("lbl_ret", self.ret_addr)
+
+    def test_init(self):
+        self.myjit.cpu.RAX = 0x1234567887658321
+        self.myjit.cpu.RDX = 0x1122334455667788
+
+    TXT = '''
+    main:
+       CWDE
+       JMP lbl_ret
+    '''
+
+    def check(self):
+        assert self.myjit.cpu.RAX == 0xFFFF8321
+        assert self.myjit.cpu.RDX == 0x1122334455667788
+
+
+class Test_CQO_64(Asm_Test_64):
+    MYSTRING = "test cwde 64"
+
+    def prepare(self):
+        self.myjit.ir_arch.symbol_pool.add_label("lbl_ret", self.ret_addr)
+
+    def test_init(self):
+        self.myjit.cpu.RAX = 0x1234567887654321
+        self.myjit.cpu.RDX = 0x1122334455667788
+
+    TXT = '''
+    main:
+       CQO
+       JMP lbl_ret
+    '''
+
+    def check(self):
+        assert self.myjit.cpu.RAX == 0x1234567887654321
+        assert self.myjit.cpu.RDX == 0x0
+
+
+class Test_CQO_64_signed(Asm_Test_64):
+    MYSTRING = "test cwde 64 signed"
+
+    def prepare(self):
+        self.myjit.ir_arch.symbol_pool.add_label("lbl_ret", self.ret_addr)
+
+    def test_init(self):
+        self.myjit.cpu.RAX = 0x8234567887658321
+        self.myjit.cpu.RDX = 0x1122334455667788
+
+    TXT = '''
+    main:
+       CQO
+       JMP lbl_ret
+    '''
+
+    def check(self):
+        assert self.myjit.cpu.RAX == 0x8234567887658321
+        assert self.myjit.cpu.RDX == 0xFFFFFFFFFFFFFFFF
+
+
+
+
+if __name__ == "__main__":
+    tests = [
+        Test_CBW_16,
+        Test_CBW_16_signed,
+
+        Test_CBW_32,
+        Test_CBW_32_signed,
+
+        Test_CWD_32,
+        Test_CWD_32_signed,
+
+        Test_CWDE_32,
+        Test_CWDE_32_signed,
+
+        Test_CWDE_64,
+        Test_CWDE_64_signed,
+
+        Test_CDQ_32,
+        Test_CDQ_32_signed,
+
+        Test_CDQ_64,
+        Test_CDQ_64_signed,
+
+        Test_CDQE_64,
+        Test_CDQE_64_signed,
+    ]
+    if sys.argv[1] not in ["gcc", "tcc"]:
+        # TODO XXX CQO use 128 bit not supported in gcc yet!
+        tests += [
+            Test_CQO_64,
+            Test_CQO_64_signed,
+        ]
+
+    [
+        test(*sys.argv[1:])() for test in tests
+    ]
diff --git a/test/test_all.py b/test/test_all.py
index 23937366..04aca62e 100755
--- a/test/test_all.py
+++ b/test/test_all.py
@@ -79,6 +79,7 @@ for script in ["x86/sem.py",
                "x86/unit/mn_pextr.py",
                "x86/unit/mn_pmovmskb.py",
                "x86/unit/mn_pushpop.py",
+               "x86/unit/mn_cdq.py",
                "x86/unit/mn_seh.py",
                "x86/unit/mn_cpuid.py",
                "x86/unit/mn_div.py",