diff options
Diffstat (limited to 'miasm/arch/x86/jit.py')
| -rw-r--r-- | miasm/arch/x86/jit.py | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/miasm/arch/x86/jit.py b/miasm/arch/x86/jit.py index 9113b9ad..38301e3c 100644 --- a/miasm/arch/x86/jit.py +++ b/miasm/arch/x86/jit.py @@ -2,7 +2,7 @@ from builtins import range import logging from miasm.jitter.jitload import Jitter, named_arguments -from miasm.arch.x86.sem import ir_x86_16, ir_x86_32, ir_x86_64 +from miasm.arch.x86.sem import Lifter_X86_16, Lifter_X86_32, Lifter_X86_64 from miasm.jitter.codegen import CGen from miasm.ir.translators.C import TranslatorC @@ -42,7 +42,7 @@ class jitter_x86_16(Jitter): C_Gen = x86_32_CGen def __init__(self, loc_db, *args, **kwargs): - Jitter.__init__(self, ir_x86_16(loc_db), *args, **kwargs) + Jitter.__init__(self, Lifter_X86_16(loc_db), *args, **kwargs) self.vm.set_little_endian() self.ir_arch.do_stk_segm = False self.orig_irbloc_fix_regs_for_mode = self.ir_arch.irbloc_fix_regs_for_mode @@ -73,7 +73,7 @@ class jitter_x86_32(Jitter): C_Gen = x86_32_CGen def __init__(self, loc_db, *args, **kwargs): - Jitter.__init__(self, ir_x86_32(loc_db), *args, **kwargs) + Jitter.__init__(self, Lifter_X86_32(loc_db), *args, **kwargs) self.vm.set_little_endian() self.ir_arch.do_stk_segm = False @@ -199,7 +199,7 @@ class jitter_x86_64(Jitter): args_regs_stdcall = ['RCX', 'RDX', 'R8', 'R9'] def __init__(self, loc_db, *args, **kwargs): - Jitter.__init__(self, ir_x86_64(loc_db), *args, **kwargs) + Jitter.__init__(self, Lifter_X86_64(loc_db), *args, **kwargs) self.vm.set_little_endian() self.ir_arch.do_stk_segm = False |