diff options
Diffstat (limited to 'miasm2/arch/aarch64')
| -rw-r--r-- | miasm2/arch/aarch64/arch.py | 36 | ||||
| -rw-r--r-- | miasm2/arch/aarch64/regs.py | 4 | ||||
| -rw-r--r-- | miasm2/arch/aarch64/sem.py | 38 |
3 files changed, 39 insertions, 39 deletions
diff --git a/miasm2/arch/aarch64/arch.py b/miasm2/arch/aarch64/arch.py index 6f95df99..1a2283d6 100644 --- a/miasm2/arch/aarch64/arch.py +++ b/miasm2/arch/aarch64/arch.py @@ -10,7 +10,7 @@ import regs as regs_module from regs import * from miasm2.core.asmblock import AsmLabel from miasm2.core.cpu import log as log_cpu -from miasm2.expression.modint import uint32, uint64 +from miasm2.expression.modint import uint32, uint64, mod_size2int import math log = logging.getLogger("aarch64dis") @@ -62,8 +62,8 @@ replace_regs = { WSP: SP[:32], - WZR: m2_expr.ExprInt32(0), - XZR: m2_expr.ExprInt64(0), + WZR: m2_expr.ExprInt(0, 32), + XZR: m2_expr.ExprInt(0, 64), } @@ -81,7 +81,7 @@ def ast_id2expr32(t): return t def ast_int2expr32(a): - return m2_expr.ExprInt32(a) + return m2_expr.ExprInt(a, 32) def ast_id2expr64(t): @@ -93,7 +93,7 @@ def ast_id2expr64(t): def ast_int2expr64(a): - return m2_expr.ExprInt64(a) + return m2_expr.ExprInt(a, 64) my_var_parser32 = ParseAst(ast_id2expr32, ast_int2expr32, default_size=32) my_var_parser64 = ParseAst(ast_id2expr64, ast_int2expr64, default_size=64) @@ -129,7 +129,7 @@ def shift2expr(t): return t[0] elif len(t) == 3: if t[0].size == 32 and isinstance(t[2], m2_expr.ExprInt): - t[2] = m2_expr.ExprInt32(t[2].arg) + t[2] = m2_expr.ExprInt(int(t[2]), 32) return m2_expr.ExprOp(t[1], t[0], t[2]) else: raise ValueError('bad string') @@ -140,7 +140,7 @@ def shift2expr_sc(t): return t[0] elif len(t) == 3: if t[0].size == 32 and isinstance(t[2], m2_expr.ExprInt): - t[2] = m2_expr.ExprInt32(t[2].arg) + t[2] = m2_expr.ExprInt(t[2].arg, 32) if t[1] != '<<': raise ValueError('bad op') return m2_expr.ExprOp("slice_at", t[0], t[2]) @@ -214,7 +214,7 @@ def ast_id2expr(t): def ast_int2expr(a): - return m2_expr.ExprInt64(a) + return m2_expr.ExprInt(a, 64) gpregs_info = {32: gpregs32_info, 64: gpregs64_info} @@ -236,7 +236,7 @@ base_expr.setParseAction(my_var_parser) def deref2expr_nooff(t): t = t[0] # XXX default - return m2_expr.ExprOp("preinc", t[0], m2_expr.ExprInt64(0)) + return m2_expr.ExprOp("preinc", t[0], m2_expr.ExprInt(0, 64)) def deref2expr_post(t): @@ -416,7 +416,7 @@ class instruction_aarch64(instruction): off = e.arg - self.offset if int(off % 4): raise ValueError('strange offset! %r' % off) - self.args[index] = m2_expr.ExprInt64(off) + self.args[index] = m2_expr.ExprInt(int(off), 64) @@ -782,15 +782,15 @@ class aarch64_int64_noarg(int32_noarg): parser = base_expr intsize = 64 intmask = (1 << intsize) - 1 - int2expr = lambda self, x: m2_expr.ExprInt64( - sign_ext(x, self.l, self.intsize)) + int2expr = lambda self, x: m2_expr.ExprInt( + sign_ext(x, self.l, self.intsize), 64) class aarch64_uint64_noarg(imm_noarg): parser = base_expr intsize = 64 intmask = (1 << intsize) - 1 - int2expr = lambda self, x: m2_expr.ExprInt64(x) + int2expr = lambda self, x: m2_expr.ExprInt(x, 64) class aarch64_uint64(aarch64_uint64_noarg, m_arg): @@ -1110,7 +1110,7 @@ class aarch64_immhip_page(aarch64_imm_32): def decode(self, v): v = ((v << 2) | self.parent.immlo.value) << 12 v = sign_ext(v, 33, 64) - self.expr = m2_expr.ExprInt64(v) + self.expr = m2_expr.ExprInt(v, 64) return True def encode(self): @@ -1132,7 +1132,7 @@ class aarch64_immhi_page(aarch64_imm_32): def decode(self, v): v = ((v << 2) | self.parent.immlo.value) v = sign_ext(v, 21, 64) - self.expr = m2_expr.ExprInt64(v) + self.expr = m2_expr.ExprInt(v, 64) return True def encode(self): @@ -1222,7 +1222,7 @@ class aarch64_offs(imm_noarg, m_arg): v = v & self.lmask v = (v << 2) v = sign_ext(v, (self.l + 2), 64) - self.expr = m2_expr.ExprInt64(v) + self.expr = m2_expr.ExprInt(v, 64) return True def encode(self): @@ -1285,7 +1285,7 @@ class aarch64_deref(m_arg): off = self.parent.imm.expr.arg op = self.get_postpre(self.parent) off = self.decode_w_size(off) - self.expr = m2_expr.ExprOp(op, reg, m2_expr.ExprInt64(off)) + self.expr = m2_expr.ExprOp(op, reg, m2_expr.ExprInt(off, 64)) return True def encode(self): @@ -1308,7 +1308,7 @@ class aarch64_deref(m_arg): imm = self.encode_w_size(imm) if imm is False: return False - self.parent.imm.expr = m2_expr.ExprInt64(imm) + self.parent.imm.expr = m2_expr.ExprInt(imm, 64) if not self.parent.imm.encode(): return False self.value = gpregs64_info.expr.index(reg) diff --git a/miasm2/arch/aarch64/regs.py b/miasm2/arch/aarch64/regs.py index 9de82c04..01ae4252 100644 --- a/miasm2/arch/aarch64/regs.py +++ b/miasm2/arch/aarch64/regs.py @@ -107,12 +107,12 @@ all_regs_ids_init = (simd08_init + gpregs32_init + gpregs64_init + [ - ExprInt32(0), + ExprInt(0, 32), PC_init, WZR_init, XZR_init, zf_init, nf_init, of_init, cf_init, - ExprInt64(0), ExprInt32(0), + ExprInt(0, 64), ExprInt(0, 32), ] ) diff --git a/miasm2/arch/aarch64/sem.py b/miasm2/arch/aarch64/sem.py index 792a4984..e9eaffc8 100644 --- a/miasm2/arch/aarch64/sem.py +++ b/miasm2/arch/aarch64/sem.py @@ -10,7 +10,7 @@ EXCEPT_PRIV_INSN = (1 << 17) def update_flag_zf(a): - return [m2_expr.ExprAff(zf, m2_expr.ExprCond(a, m2_expr.ExprInt1(0), m2_expr.ExprInt1(1)))] + return [m2_expr.ExprAff(zf, m2_expr.ExprCond(a, m2_expr.ExprInt(0, 1), m2_expr.ExprInt(1, 1)))] def update_flag_nf(a): @@ -28,7 +28,7 @@ def update_flag_logic(a): e = [] e += update_flag_zn(a) # XXX TODO: set cf if ROT imm in argument - # e.append(m2_expr.ExprAff(cf, m2_expr.ExprInt1(0))) + # e.append(m2_expr.ExprAff(cf, m2_expr.ExprInt(0, 1))) return e @@ -66,7 +66,7 @@ def update_flag_add_of(op1, op2, res): def update_flag_sub_cf(op1, op2, res): "Compote CF in @res = @op1 - @op2" return m2_expr.ExprAff(cf, - ((((op1 ^ op2) ^ res) ^ ((op1 ^ res) & (op1 ^ op2))).msb()) ^ m2_expr.ExprInt1(1)) + ((((op1 ^ op2) ^ res) ^ ((op1 ^ res) & (op1 ^ op2))).msb()) ^ m2_expr.ExprInt(1, 1)) def update_flag_sub_of(op1, op2, res): @@ -93,22 +93,22 @@ def update_flag_sub(x, y, z): cond2expr = {'EQ': zf, - 'NE': zf ^ m2_expr.ExprInt1(1), + 'NE': zf ^ m2_expr.ExprInt(1, 1), 'CS': cf, - 'CC': cf ^ m2_expr.ExprInt1(1), + 'CC': cf ^ m2_expr.ExprInt(1, 1), 'MI': nf, - 'PL': nf ^ m2_expr.ExprInt1(1), + 'PL': nf ^ m2_expr.ExprInt(1, 1), 'VS': of, - 'VC': of ^ m2_expr.ExprInt1(1), - 'HI': cf & (zf ^ m2_expr.ExprInt1(1)), - 'LS': (cf ^ m2_expr.ExprInt1(1)) | zf, - 'GE': nf ^ of ^ m2_expr.ExprInt1(1), + 'VC': of ^ m2_expr.ExprInt(1, 1), + 'HI': cf & (zf ^ m2_expr.ExprInt(1, 1)), + 'LS': (cf ^ m2_expr.ExprInt(1, 1)) | zf, + 'GE': nf ^ of ^ m2_expr.ExprInt(1, 1), 'LT': nf ^ of, - 'GT': ((zf ^ m2_expr.ExprInt1(1)) & - (nf ^ of ^ m2_expr.ExprInt1(1))), + 'GT': ((zf ^ m2_expr.ExprInt(1, 1)) & + (nf ^ of ^ m2_expr.ExprInt(1, 1))), 'LE': zf | (nf ^ of), - 'AL': m2_expr.ExprInt1(1), - 'NV': m2_expr.ExprInt1(0) + 'AL': m2_expr.ExprInt(1, 1), + 'NV': m2_expr.ExprInt(0, 1) } @@ -277,9 +277,9 @@ def movk(ir, instr, arg1, arg2): isinstance(arg2.args[1], m2_expr.ExprInt)) value, shift = int(arg2.args[0].arg), int(arg2.args[1]) e.append( - m2_expr.ExprAff(arg1[shift:shift + 16], m2_expr.ExprInt16(value))) + m2_expr.ExprAff(arg1[shift:shift + 16], m2_expr.ExprInt(value, 16))) else: - e.append(m2_expr.ExprAff(arg1[:16], m2_expr.ExprInt16(int(arg2)))) + e.append(m2_expr.ExprAff(arg1[:16], m2_expr.ExprInt(int(arg2), 16))) return e, [] @@ -298,7 +298,7 @@ def movn(arg1, arg2): def bl(arg1): PC = arg1 ir.IRDst = arg1 - LR = m2_expr.ExprInt64(instr.offset + instr.l) + LR = m2_expr.ExprInt(instr.offset + instr.l, 64) @sbuild.parse def csel(arg1, arg2, arg3, arg4): @@ -649,7 +649,7 @@ def ret(arg1): @sbuild.parse def adrp(arg1, arg2): - arg1 = (PC & m2_expr.ExprInt64(0xfffffffffffff000)) + arg2 + arg1 = (PC & m2_expr.ExprInt(0xfffffffffffff000, 64)) + arg2 @sbuild.parse @@ -797,7 +797,7 @@ class ir_aarch64l(IntermediateRepresentation): def mod_pc(self, instr, instr_ir, extra_ir): "Replace PC by the instruction's offset" - cur_offset = m2_expr.ExprInt64(instr.offset) + cur_offset = m2_expr.ExprInt(instr.offset, 64) for i, expr in enumerate(instr_ir): dst, src = expr.dst, expr.src if dst != self.pc: |