diff options
Diffstat (limited to 'miasm2/arch/arm')
| -rw-r--r-- | miasm2/arch/arm/arch.py | 1 | ||||
| -rw-r--r-- | miasm2/arch/arm/disasm.py | 4 | ||||
| -rw-r--r-- | miasm2/arch/arm/ira.py | 16 | ||||
| -rw-r--r-- | miasm2/arch/arm/jit.py | 29 | ||||
| -rw-r--r-- | miasm2/arch/arm/sem.py | 20 |
5 files changed, 32 insertions, 38 deletions
diff --git a/miasm2/arch/arm/arch.py b/miasm2/arch/arm/arch.py index d9bf42ba..54a168af 100644 --- a/miasm2/arch/arm/arch.py +++ b/miasm2/arch/arm/arch.py @@ -8,7 +8,6 @@ from collections import defaultdict from miasm2.core.bin_stream import bin_stream import miasm2.arch.arm.regs as regs_module from miasm2.arch.arm.regs import * -from miasm2.core.asmbloc import asm_label # A1 encoding diff --git a/miasm2/arch/arm/disasm.py b/miasm2/arch/arm/disasm.py index 6209be5e..3f6ea4d5 100644 --- a/miasm2/arch/arm/disasm.py +++ b/miasm2/arch/arm/disasm.py @@ -1,4 +1,4 @@ -from miasm2.core.asmbloc import asm_constraint, disasmEngine +from miasm2.core.asmblock import AsmConstraint, disasmEngine from miasm2.arch.arm.arch import mn_arm, mn_armt @@ -24,7 +24,7 @@ def cb_arm_fix_call(mn, cur_bloc, symbol_pool, offsets_to_dis, *args, **kwargs): return if not l2.args[1] in values: return - cur_bloc.add_cst(l1.offset + 4, asm_constraint.c_next, symbol_pool) + cur_bloc.add_cst(l1.offset + 4, AsmConstraint.c_next, symbol_pool) offsets_to_dis.add(l1.offset + 4) cb_arm_funcs = [cb_arm_fix_call] diff --git a/miasm2/arch/arm/ira.py b/miasm2/arch/arm/ira.py index 8d659b58..760e6d90 100644 --- a/miasm2/arch/arm/ira.py +++ b/miasm2/arch/arm/ira.py @@ -1,11 +1,7 @@ #-*- coding:utf-8 -*- -from miasm2.expression.expression import * -from miasm2.ir.ir import ir, irbloc, AssignBlock from miasm2.ir.analysis import ira from miasm2.arch.arm.sem import ir_arml, ir_armtl, ir_armb, ir_armtb -from miasm2.arch.arm.regs import * -# from miasm2.core.graph import DiGraph class ir_a_arml_base(ir_arml, ira): @@ -26,13 +22,13 @@ class ir_a_arml(ir_a_arml_base): self.ret_reg = self.arch.regs.R0 # for test XXX TODO - def set_dead_regs(self, b): - b.rw[-1][1].add(self.arch.regs.zf) - b.rw[-1][1].add(self.arch.regs.nf) - b.rw[-1][1].add(self.arch.regs.of) - b.rw[-1][1].add(self.arch.regs.cf) + def set_dead_regs(self, irblock): + irblock.rw[-1][1].add(self.arch.regs.zf) + irblock.rw[-1][1].add(self.arch.regs.nf) + irblock.rw[-1][1].add(self.arch.regs.of) + irblock.rw[-1][1].add(self.arch.regs.cf) - def get_out_regs(self, b): + def get_out_regs(self, _): return set([self.ret_reg, self.sp]) def sizeof_char(self): diff --git a/miasm2/arch/arm/jit.py b/miasm2/arch/arm/jit.py index 70d16176..70c708e1 100644 --- a/miasm2/arch/arm/jit.py +++ b/miasm2/arch/arm/jit.py @@ -1,8 +1,8 @@ import logging from miasm2.jitter.jitload import jitter, named_arguments -from miasm2.core import asmbloc -from miasm2.core.utils import * +from miasm2.core import asmblock +from miasm2.core.utils import pck32, upck32 from miasm2.arch.arm.sem import ir_armb, ir_arml log = logging.getLogger('jit_arm') @@ -14,22 +14,21 @@ log.setLevel(logging.CRITICAL) class jitter_arml(jitter): def __init__(self, *args, **kwargs): - sp = asmbloc.asm_symbol_pool() + sp = asmblock.AsmSymbolPool() jitter.__init__(self, ir_arml(sp), *args, **kwargs) self.vm.set_little_endian() - def push_uint32_t(self, v): + def push_uint32_t(self, value): self.cpu.SP -= 4 - self.vm.set_mem(self.cpu.SP, pck32(v)) + self.vm.set_mem(self.cpu.SP, pck32(value)) def pop_uint32_t(self): - x = upck32(self.vm.get_mem(self.cpu.SP, 4)) + value = upck32(self.vm.get_mem(self.cpu.SP, 4)) self.cpu.SP += 4 - return x + return value - def get_stack_arg(self, n): - x = upck32(self.vm.get_mem(self.cpu.SP + 4 * n, 4)) - return x + def get_stack_arg(self, index): + return upck32(self.vm.get_mem(self.cpu.SP + 4 * index, 4)) # calling conventions @@ -49,11 +48,11 @@ class jitter_arml(jitter): self.cpu.R0 = ret_value return True - def get_arg_n_stdcall(self, n): - if n < 4: - arg = self.cpu.get_gpreg()['R%d' % n] + def get_arg_n_stdcall(self, index): + if index < 4: + arg = self.cpu.get_gpreg()['R%d' % index] else: - arg = self.get_stack_arg(n-4) + arg = self.get_stack_arg(index-4) return arg def init_run(self, *args, **kwargs): @@ -63,6 +62,6 @@ class jitter_arml(jitter): class jitter_armb(jitter_arml): def __init__(self, *args, **kwargs): - sp = asmbloc.asm_symbol_pool() + sp = asmblock.AsmSymbolPool() jitter.__init__(self, ir_armb(sp), *args, **kwargs) self.vm.set_big_endian() diff --git a/miasm2/arch/arm/sem.py b/miasm2/arch/arm/sem.py index 225b393c..8c74aa76 100644 --- a/miasm2/arch/arm/sem.py +++ b/miasm2/arch/arm/sem.py @@ -1,5 +1,5 @@ from miasm2.expression.expression import * -from miasm2.ir.ir import ir, irbloc +from miasm2.ir.ir import IntermediateRepresentation, IRBlock from miasm2.arch.arm.arch import mn_arm, mn_armt from miasm2.arch.arm.regs import * @@ -1055,7 +1055,7 @@ def add_condition_expr(ir, instr, cond, instr_ir): break if not has_irdst: instr_ir.append(ExprAff(ir.IRDst, lbl_next)) - e_do = irbloc(lbl_do.name, [instr_ir]) + e_do = IRBlock(lbl_do.name, [instr_ir]) e = [ExprAff(ir.IRDst, dst_cond)] return e, [e_do] @@ -1227,9 +1227,9 @@ class arminfo: # offset -class ir_arml(ir): +class ir_arml(IntermediateRepresentation): def __init__(self, symbol_pool=None): - ir.__init__(self, mn_arm, "l", symbol_pool) + IntermediateRepresentation.__init__(self, mn_arm, "l", symbol_pool) self.pc = PC self.sp = SP self.IRDst = ExprId('IRDst', 32) @@ -1252,8 +1252,8 @@ class ir_arml(ir): x = ExprAff(x.dst, x.src.replace_expr( {self.pc: ExprInt32(instr.offset + 8)})) instr_ir[i] = x - for b in extra_ir: - for irs in b.irs: + for irblock in extra_ir: + for irs in irblock.irs: for i, x in enumerate(irs): x = ExprAff(x.dst, x.src.replace_expr( {self.pc: ExprInt32(instr.offset + 8)})) @@ -1264,14 +1264,14 @@ class ir_arml(ir): class ir_armb(ir_arml): def __init__(self, symbol_pool=None): - ir.__init__(self, mn_arm, "b", symbol_pool) + IntermediateRepresentation.__init__(self, mn_arm, "b", symbol_pool) self.pc = PC self.sp = SP self.IRDst = ExprId('IRDst', 32) -class ir_armtl(ir): +class ir_armtl(IntermediateRepresentation): def __init__(self, symbol_pool=None): - ir.__init__(self, mn_armt, "l", symbol_pool) + IntermediateRepresentation.__init__(self, mn_armt, "l", symbol_pool) self.pc = PC self.sp = SP self.IRDst = ExprId('IRDst', 32) @@ -1281,7 +1281,7 @@ class ir_armtl(ir): class ir_armtb(ir_armtl): def __init__(self, symbol_pool=None): - ir.__init__(self, mn_armt, "b", symbol_pool) + IntermediateRepresentation.__init__(self, mn_armt, "b", symbol_pool) self.pc = PC self.sp = SP self.IRDst = ExprId('IRDst', 32) |