diff options
Diffstat (limited to 'miasm2/arch/arm')
| -rw-r--r-- | miasm2/arch/arm/arch.py | 36 | ||||
| -rw-r--r-- | miasm2/arch/arm/disasm.py | 4 | ||||
| -rw-r--r-- | miasm2/arch/arm/ira.py | 24 | ||||
| -rw-r--r-- | miasm2/arch/arm/jit.py | 8 | ||||
| -rw-r--r-- | miasm2/arch/arm/sem.py | 28 |
5 files changed, 50 insertions, 50 deletions
diff --git a/miasm2/arch/arm/arch.py b/miasm2/arch/arm/arch.py index 624642cf..498de94c 100644 --- a/miasm2/arch/arm/arch.py +++ b/miasm2/arch/arm/arch.py @@ -343,13 +343,13 @@ class instruction_arm(instruction): super(instruction_arm, self).__init__(*args, **kargs) @staticmethod - def arg2str(expr, index=None, symbol_pool=None): + def arg2str(expr, index=None, loc_db=None): wb = False if expr.is_id() or expr.is_int(): return str(expr) elif expr.is_loc(): - if symbol_pool is not None: - return symbol_pool.str_loc_key(expr.loc_key) + if loc_db is not None: + return loc_db.str_loc_key(expr.loc_key) else: return str(expr) if isinstance(expr, ExprOp) and expr.op in expr2shift_dct: @@ -422,7 +422,7 @@ class instruction_arm(instruction): def dstflow(self): return self.name in conditional_branch + unconditional_branch - def dstflow2label(self, symbol_pool): + def dstflow2label(self, loc_db): expr = self.args[0] if not isinstance(expr, ExprInt): return @@ -430,7 +430,7 @@ class instruction_arm(instruction): addr = expr.arg + self.offset else: addr = expr.arg + self.offset - loc_key = symbol_pool.getby_offset_create(addr) + loc_key = loc_db.getby_offset_create(addr) self.args[0] = ExprLoc(loc_key, expr.size) def breakflow(self): @@ -447,7 +447,7 @@ class instruction_arm(instruction): return True return self.additional_info.lnk - def getdstflow(self, symbol_pool): + def getdstflow(self, loc_db): return [self.args[0]] def splitflow(self): @@ -459,7 +459,7 @@ class instruction_arm(instruction): return False return self.breakflow() and self.additional_info.cond != 14 - def get_symbol_size(self, symbol, symbol_pool): + def get_symbol_size(self, symbol, loc_db): return 32 def fixDstOffset(self): @@ -494,7 +494,7 @@ class instruction_armt(instruction_arm): return True return self.name in conditional_branch + unconditional_branch - def dstflow2label(self, symbol_pool): + def dstflow2label(self, loc_db): if self.name in ["CBZ", "CBNZ"]: expr = self.args[1] else: @@ -512,7 +512,7 @@ class instruction_armt(instruction_arm): else: addr = expr.arg + self.offset - loc_key = symbol_pool.getby_offset_create(addr) + loc_key = loc_db.getby_offset_create(addr) dst = ExprLoc(loc_key, expr.size) if self.name in ["CBZ", "CBNZ"]: @@ -529,7 +529,7 @@ class instruction_armt(instruction_arm): return True return False - def getdstflow(self, symbol_pool): + def getdstflow(self, loc_db): if self.name in ['CBZ', 'CBNZ']: return [self.args[1]] return [self.args[0]] @@ -662,7 +662,7 @@ class mn_arm(cls_mn): raise NotImplementedError('bad attrib') - def get_symbol_size(self, symbol, symbol_pool, mode): + def get_symbol_size(self, symbol, loc_db, mode): return 32 @@ -769,28 +769,28 @@ class mn_armt(cls_mn): args = [a.expr for a in self.args] return args - def get_symbol_size(self, symbol, symbol_pool, mode): + def get_symbol_size(self, symbol, loc_db, mode): return 32 class arm_arg(m_arg): - def asm_ast_to_expr(self, arg, symbol_pool): + def asm_ast_to_expr(self, arg, loc_db): if isinstance(arg, AstId): if isinstance(arg.name, ExprId): return arg.name if arg.name in gpregs.str: return None - loc_key = symbol_pool.getby_name_create(arg.name) + loc_key = loc_db.getby_name_create(arg.name) return ExprLoc(loc_key, 32) if isinstance(arg, AstOp): - args = [self.asm_ast_to_expr(tmp, symbol_pool) for tmp in arg.args] + args = [self.asm_ast_to_expr(tmp, loc_db) for tmp in arg.args] if None in args: return None return ExprOp(arg.op, *args) if isinstance(arg, AstInt): return ExprInt(arg.value, 32) if isinstance(arg, AstMem): - ptr = self.asm_ast_to_expr(arg.ptr, symbol_pool) + ptr = self.asm_ast_to_expr(arg.ptr, loc_db) if ptr is None: return None return ExprMem(ptr, arg.size) @@ -2809,8 +2809,8 @@ class armt_aif(reg_noarg, arm_arg): return ret return self.value != 0 - def fromstring(self, text, symbol_pool, parser_result=None): - start, stop = super(armt_aif, self).fromstring(text, symbol_pool, parser_result) + def fromstring(self, text, loc_db, parser_result=None): + start, stop = super(armt_aif, self).fromstring(text, loc_db, parser_result) if self.expr.name == "X": return None, None return start, stop diff --git a/miasm2/arch/arm/disasm.py b/miasm2/arch/arm/disasm.py index 8997fa2b..41034211 100644 --- a/miasm2/arch/arm/disasm.py +++ b/miasm2/arch/arm/disasm.py @@ -2,7 +2,7 @@ from miasm2.core.asmblock import AsmConstraint, disasmEngine from miasm2.arch.arm.arch import mn_arm, mn_armt -def cb_arm_fix_call(mn, cur_bloc, symbol_pool, offsets_to_dis, *args, **kwargs): +def cb_arm_fix_call(mn, cur_bloc, loc_db, offsets_to_dis, *args, **kwargs): """ for arm: MOV LR, PC @@ -24,7 +24,7 @@ def cb_arm_fix_call(mn, cur_bloc, symbol_pool, offsets_to_dis, *args, **kwargs): return if not l2.args[1] in values: return - loc_key_cst = symbol_pool.getby_offset_create(l1.offset + 4) + loc_key_cst = loc_db.getby_offset_create(l1.offset + 4) cur_bloc.add_cst(loc_key_cst, AsmConstraint.c_next) offsets_to_dis.add(l1.offset + 4) diff --git a/miasm2/arch/arm/ira.py b/miasm2/arch/arm/ira.py index cfcb294c..0c84c919 100644 --- a/miasm2/arch/arm/ira.py +++ b/miasm2/arch/arm/ira.py @@ -5,20 +5,20 @@ from miasm2.arch.arm.sem import ir_arml, ir_armtl, ir_armb, ir_armtb class ir_a_arml_base(ir_arml, ira): - def __init__(self, symbol_pool=None): - ir_arml.__init__(self, symbol_pool) + def __init__(self, loc_db=None): + ir_arml.__init__(self, loc_db) self.ret_reg = self.arch.regs.R0 class ir_a_armb_base(ir_armb, ira): - def __init__(self, symbol_pool=None): - ir_armb.__init__(self, symbol_pool) + def __init__(self, loc_db=None): + ir_armb.__init__(self, loc_db) self.ret_reg = self.arch.regs.R0 class ir_a_arml(ir_a_arml_base): - def __init__(self, symbol_pool=None): - ir_a_arml_base.__init__(self, symbol_pool) + def __init__(self, loc_db=None): + ir_a_arml_base.__init__(self, loc_db) self.ret_reg = self.arch.regs.R0 def get_out_regs(self, _): @@ -41,17 +41,17 @@ class ir_a_arml(ir_a_arml_base): class ir_a_armb(ir_a_armb_base, ir_a_arml): - def __init__(self, symbol_pool=None): - ir_a_armb_base.__init__(self, symbol_pool) + def __init__(self, loc_db=None): + ir_a_armb_base.__init__(self, loc_db) self.ret_reg = self.arch.regs.R0 class ir_a_armtl(ir_armtl, ir_a_arml): - def __init__(self, symbol_pool=None): - ir_armtl.__init__(self, symbol_pool) + def __init__(self, loc_db=None): + ir_armtl.__init__(self, loc_db) self.ret_reg = self.arch.regs.R0 class ir_a_armtb(ir_a_armtl, ir_armtb, ir_a_armb): - def __init__(self, symbol_pool=None): - ir_armtb.__init__(self, symbol_pool) + def __init__(self, loc_db=None): + ir_armtb.__init__(self, loc_db) self.ret_reg = self.arch.regs.R0 diff --git a/miasm2/arch/arm/jit.py b/miasm2/arch/arm/jit.py index ef2e14ae..10a7c644 100644 --- a/miasm2/arch/arm/jit.py +++ b/miasm2/arch/arm/jit.py @@ -1,7 +1,7 @@ import logging from miasm2.jitter.jitload import Jitter, named_arguments -from miasm2.core import asmblock +from miasm2.core.locationdb import LocationDB from miasm2.core.utils import pck32, upck32 from miasm2.arch.arm.sem import ir_armb, ir_arml, ir_armtl, ir_armtb, cond_dct_inv, tab_cond from miasm2.jitter.codegen import CGen @@ -55,7 +55,7 @@ class jitter_arml(Jitter): C_Gen = arm_CGen def __init__(self, *args, **kwargs): - sp = asmblock.AsmSymbolPool() + sp = LocationDB() Jitter.__init__(self, ir_arml(sp), *args, **kwargs) self.vm.set_little_endian() @@ -115,7 +115,7 @@ class jitter_armb(jitter_arml): C_Gen = arm_CGen def __init__(self, *args, **kwargs): - sp = asmblock.AsmSymbolPool() + sp = LocationDB() Jitter.__init__(self, ir_armb(sp), *args, **kwargs) self.vm.set_big_endian() @@ -124,6 +124,6 @@ class jitter_armtl(jitter_arml): C_Gen = arm_CGen def __init__(self, *args, **kwargs): - sp = asmblock.AsmSymbolPool() + sp = LocationDB() Jitter.__init__(self, ir_armtl(sp), *args, **kwargs) self.vm.set_little_endian() diff --git a/miasm2/arch/arm/sem.py b/miasm2/arch/arm/sem.py index ccd56e8f..6e311f8e 100644 --- a/miasm2/arch/arm/sem.py +++ b/miasm2/arch/arm/sem.py @@ -441,8 +441,8 @@ def sdiv(ir, instr, a, b, c=None): if c is None: b, c = a, b - loc_div = ExprLoc(ir.symbol_pool.gen_loc_key(), ir.IRDst.size) - loc_except = ExprId(ir.symbol_pool.gen_loc_key(), ir.IRDst.size) + loc_div = ExprLoc(ir.loc_db.gen_loc_key(), ir.IRDst.size) + loc_except = ExprId(ir.loc_db.gen_loc_key(), ir.IRDst.size) loc_next = ExprLoc(ir.get_next_loc_key(instr), ir.IRDst.size) e.append(ExprAff(ir.IRDst, ExprCond(c, loc_div, loc_except))) @@ -474,8 +474,8 @@ def udiv(ir, instr, a, b, c=None): - loc_div = ExprLoc(ir.symbol_pool.gen_loc_key(), ir.IRDst.size) - loc_except = ExprLoc(ir.symbol_pool.gen_loc_key(), ir.IRDst.size) + loc_div = ExprLoc(ir.loc_db.gen_loc_key(), ir.IRDst.size) + loc_except = ExprLoc(ir.loc_db.gen_loc_key(), ir.IRDst.size) loc_next = ExprLoc(ir.get_next_loc_key(instr), ir.IRDst.size) e.append(ExprAff(ir.IRDst, ExprCond(c, loc_div, loc_except))) @@ -1266,7 +1266,7 @@ def add_condition_expr(ir, instr, cond, instr_ir, extra_ir): loc_next = ir.get_next_loc_key(instr) loc_next_expr = ExprLoc(loc_next, 32) - loc_do = ir.symbol_pool.gen_loc_key() + loc_do = ir.loc_db.gen_loc_key() loc_do_expr = ExprLoc(loc_do, 32) dst_cond = ExprCond(cond, loc_do_expr, loc_next_expr) @@ -1474,8 +1474,8 @@ class arminfo: class ir_arml(IntermediateRepresentation): - def __init__(self, symbol_pool=None): - IntermediateRepresentation.__init__(self, mn_arm, "l", symbol_pool) + def __init__(self, loc_db=None): + IntermediateRepresentation.__init__(self, mn_arm, "l", loc_db) self.pc = PC self.sp = SP self.IRDst = ExprId('IRDst', 32) @@ -1556,7 +1556,7 @@ class ir_arml(IntermediateRepresentation): instr = block.lines[index] # Add conditionnal jump to current irblock - loc_do = self.symbol_pool.gen_loc_key() + loc_do = self.loc_db.gen_loc_key() loc_next = self.get_next_loc_key(instr) if hint: @@ -1630,8 +1630,8 @@ class ir_arml(IntermediateRepresentation): class ir_armb(ir_arml): - def __init__(self, symbol_pool=None): - IntermediateRepresentation.__init__(self, mn_arm, "b", symbol_pool) + def __init__(self, loc_db=None): + IntermediateRepresentation.__init__(self, mn_arm, "b", loc_db) self.pc = PC self.sp = SP self.IRDst = ExprId('IRDst', 32) @@ -1639,8 +1639,8 @@ class ir_armb(ir_arml): class ir_armtl(ir_arml): - def __init__(self, symbol_pool=None): - IntermediateRepresentation.__init__(self, mn_armt, "l", symbol_pool) + def __init__(self, loc_db=None): + IntermediateRepresentation.__init__(self, mn_armt, "l", loc_db) self.pc = PC self.sp = SP self.IRDst = ExprId('IRDst', 32) @@ -1665,8 +1665,8 @@ class ir_armtl(ir_arml): class ir_armtb(ir_armtl): - def __init__(self, symbol_pool=None): - IntermediateRepresentation.__init__(self, mn_armt, "b", symbol_pool) + def __init__(self, loc_db=None): + IntermediateRepresentation.__init__(self, mn_armt, "b", loc_db) self.pc = PC self.sp = SP self.IRDst = ExprId('IRDst', 32) |