3 files changed, 78 insertions, 3 deletions
diff --git a/miasm2/arch/arm/jit.py b/miasm2/arch/arm/jit.py
new file mode 100644
index 00000000..d491671c
--- /dev/null
+++ b/miasm2/arch/arm/jit.py
@@ -0,0 +1,71 @@
+from miasm2.jitter.jitload import jitter
+from miasm2.core import asmbloc
+from miasm2.core.utils import *
+from miasm2.arch.arm.sem import ir_arm
+
+import logging
+
+log = logging.getLogger('jit_arm')
+hnd = logging.StreamHandler()
+hnd.setFormatter(logging.Formatter("[%(levelname)s]: %(message)s"))
+log.addHandler(hnd)
+log.setLevel(logging.CRITICAL)
+
+class jitter_arm(jitter):
+
+    def __init__(self, *args, **kwargs):
+        sp = asmbloc.asm_symbol_pool()
+        jitter.__init__(self, ir_arm(sp), *args, **kwargs)
+        self.my_ir.jit_pc = self.my_ir.arch.regs.PC
+
+    def vm_push_uint32_t(self, v):
+        self.cpu.SP -= 4
+        self.vm.vm_set_mem(self.cpu.SP, pck32(v))
+
+    def vm_pop_uint32_t(self):
+        x = upck32(self.vm.vm_get_mem(self.cpu.SP, 4))
+        self.cpu.SP += 4
+        return x
+
+    def get_stack_arg(self, n):
+        x = upck32(self.vm.vm_get_mem(self.cpu.SP + 4 * n, 4))
+        return x
+
+    # calling conventions
+
+    def func_args_stdcall(self, n_args):
+        args = []
+        for i in xrange(min(n_args, 4)):
+            args.append(self.cpu.vm_get_gpreg()['R%d' % i])
+        for i in xrange(max(0, n_args - 4)):
+            args.append(self.get_stack_arg(i))
+
+        ret_ad = self.cpu.LR
+        log.debug('%s %s %s' % (whoami(), hex(ret_ad), [hex(x) for x in args]))
+        return ret_ad, args
+
+    def func_ret_stdcall(self, ret_addr, ret_value=None):
+        self.pc = self.cpu.PC = ret_addr
+        if ret_value is not None:
+            self.cpu.R0 = ret_value
+        return True
+
+    def get_arg_n_stdcall(self, n):
+        if n < 4:
+            arg = self.cpu.vm_get_gpreg()['R%d' % n]
+        else:
+            arg = self.get_stack_arg(n-4)
+        return arg
+
+    def add_lib_handler(self, libs):
+        from miasm2.jitter.os_dep import linux_stdlib
+        for offset, fname in libs.fad2cname.iteritems():
+            if fname in linux_stdlib.__dict__:
+                self.add_breakpoint(offset, linux_stdlib.__dict__[fname])
+            else:
+                log.warning(
+                    'jitter libhandler: %s function not found!' % fname)
+
+    def init_run(self, *args, **kwargs):
+        jitter.init_run(self, *args, **kwargs)
+        self.cpu.PC = self.pc
diff --git a/miasm2/arch/arm/regs.py b/miasm2/arch/arm/regs.py
index 2787605a..29b2c805 100644
--- a/miasm2/arch/arm/regs.py
+++ b/miasm2/arch/arm/regs.py
@@ -9,6 +9,8 @@ from miasm2.expression.expression import *
 regs32_str = ["R%d" % i for i in xrange(13)] + ["SP", "LR", "PC"]
 regs32_expr = [ExprId(x, 32) for x in regs32_str]
 
+exception_flags = ExprId('exception_flags', 32)
+
 
 R0 = regs32_expr[0]
 R1 = regs32_expr[1]
@@ -63,7 +65,8 @@ cf_init = ExprId("cf_init", size=1)
 
 all_regs_ids = [
     R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, SP, LR, PC,
-    zf, nf, of, cf
+    zf, nf, of, cf,
+    exception_flags
 ]
 
 all_regs_ids_no_alias = all_regs_ids
@@ -74,7 +77,8 @@ all_regs_ids_init = [R0_init, R1_init, R2_init, R3_init,
                      R4_init, R5_init, R6_init, R7_init,
                      R8_init, R9_init, R10_init, R11_init,
                      R12_init, SP_init, LR_init, PC_init,
-                     zf_init, nf_init, of_init, cf_init
+                     zf_init, nf_init, of_init, cf_init,
+                     ExprInt32(0)
                      ]
 
 regs_init = {}
diff --git a/miasm2/arch/arm/sem.py b/miasm2/arch/arm/sem.py
index 498017c9..c2ce1b55 100644
--- a/miasm2/arch/arm/sem.py
+++ b/miasm2/arch/arm/sem.py
@@ -701,7 +701,7 @@ def stmdb(ir, instr, a, b):
 def svc(ir, instr, a):
     # XXX TODO implement
     e = [
-        ExprAff(ExprId('vmmngr.exception_flags'), ExprInt32(EXCEPT_PRIV_INSN))]
+        ExprAff(ExprId(exception_flags), ExprInt32(EXCEPT_PRIV_INSN))]
     return None, e