diff options
Diffstat (limited to 'miasm2/arch/arm')
| -rw-r--r-- | miasm2/arch/arm/arch.py | 6 | ||||
| -rw-r--r-- | miasm2/arch/arm/disasm.py | 2 | ||||
| -rw-r--r-- | miasm2/arch/arm/jit.py | 12 | ||||
| -rw-r--r-- | miasm2/arch/arm/sem.py | 3 |
4 files changed, 7 insertions, 16 deletions
diff --git a/miasm2/arch/arm/arch.py b/miasm2/arch/arm/arch.py index 17b57ba4..624642cf 100644 --- a/miasm2/arch/arm/arch.py +++ b/miasm2/arch/arm/arch.py @@ -1038,16 +1038,12 @@ class arm_op2(arm_arg): shift_kind = shift & 1 shift_type = (shift >> 1) & 3 shift >>= 3 - # print self.parent.immop.value, hex(shift), hex(shift_kind), - # hex(shift_type) if shift_kind: # shift kind is reg if shift & 1: - # log.debug('error in shift1') return False rs = shift >> 1 if rs == 0xf: - # log.debug('error in shift2') return False shift_op = regs_expr[rs] else: @@ -2155,12 +2151,10 @@ class armt_rlist_pclr(armt_rlist): reg_l = list(e.args) self.parent.pclr.value = 0 if self.parent.pp.value == 0: - # print 'push' if regs_expr[14] in reg_l: reg_l.remove(regs_expr[14]) self.parent.pclr.value = 1 else: - # print 'pop', if regs_expr[15] in reg_l: reg_l.remove(regs_expr[15]) self.parent.pclr.value = 1 diff --git a/miasm2/arch/arm/disasm.py b/miasm2/arch/arm/disasm.py index 205e2a17..8997fa2b 100644 --- a/miasm2/arch/arm/disasm.py +++ b/miasm2/arch/arm/disasm.py @@ -24,7 +24,7 @@ def cb_arm_fix_call(mn, cur_bloc, symbol_pool, offsets_to_dis, *args, **kwargs): return if not l2.args[1] in values: return - loc_key_cst = self.symbol_pool.getby_offset_create(l1.offset + 4) + loc_key_cst = symbol_pool.getby_offset_create(l1.offset + 4) cur_bloc.add_cst(loc_key_cst, AsmConstraint.c_next) offsets_to_dis.add(l1.offset + 4) diff --git a/miasm2/arch/arm/jit.py b/miasm2/arch/arm/jit.py index b92e2c32..ef2e14ae 100644 --- a/miasm2/arch/arm/jit.py +++ b/miasm2/arch/arm/jit.py @@ -1,6 +1,6 @@ import logging -from miasm2.jitter.jitload import jitter, named_arguments +from miasm2.jitter.jitload import Jitter, named_arguments from miasm2.core import asmblock from miasm2.core.utils import pck32, upck32 from miasm2.arch.arm.sem import ir_armb, ir_arml, ir_armtl, ir_armtb, cond_dct_inv, tab_cond @@ -51,12 +51,12 @@ class arm_CGen(CGen): return irblocks_list -class jitter_arml(jitter): +class jitter_arml(Jitter): C_Gen = arm_CGen def __init__(self, *args, **kwargs): sp = asmblock.AsmSymbolPool() - jitter.__init__(self, ir_arml(sp), *args, **kwargs) + Jitter.__init__(self, ir_arml(sp), *args, **kwargs) self.vm.set_little_endian() def push_uint32_t(self, value): @@ -107,7 +107,7 @@ class jitter_arml(jitter): get_arg_n_systemv = get_arg_n_stdcall def init_run(self, *args, **kwargs): - jitter.init_run(self, *args, **kwargs) + Jitter.init_run(self, *args, **kwargs) self.cpu.PC = self.pc @@ -116,7 +116,7 @@ class jitter_armb(jitter_arml): def __init__(self, *args, **kwargs): sp = asmblock.AsmSymbolPool() - jitter.__init__(self, ir_armb(sp), *args, **kwargs) + Jitter.__init__(self, ir_armb(sp), *args, **kwargs) self.vm.set_big_endian() @@ -125,5 +125,5 @@ class jitter_armtl(jitter_arml): def __init__(self, *args, **kwargs): sp = asmblock.AsmSymbolPool() - jitter.__init__(self, ir_armtl(sp), *args, **kwargs) + Jitter.__init__(self, ir_armtl(sp), *args, **kwargs) self.vm.set_little_endian() diff --git a/miasm2/arch/arm/sem.py b/miasm2/arch/arm/sem.py index c80e9826..ccd56e8f 100644 --- a/miasm2/arch/arm/sem.py +++ b/miasm2/arch/arm/sem.py @@ -635,7 +635,6 @@ def st_ld_r(ir, instr, a, a2, b, store=False, size=32, s_ext=False, z_ext=False) base, off = b.args[0], b.args[1] # ExprInt(size/8, 32) else: base, off = b, ExprInt(0, 32) - # print a, wb, base, off, postinc if postinc: ad = base else: @@ -734,13 +733,11 @@ def ldrsh(ir, instr, a, b): def st_ld_m(ir, instr, a, b, store=False, postinc=False, updown=False): e = [] wb = False - # sb = False dst = None if isinstance(a, ExprOp) and a.op == 'wback': wb = True a = a.args[0] if isinstance(b, ExprOp) and b.op == 'sbit': - # sb = True b = b.args[0] regs = b.args base = a |