4 files changed, 62 insertions, 22 deletions
diff --git a/miasm2/arch/arm/disasm.py b/miasm2/arch/arm/disasm.py
index 64e10eec..3ba08995 100644
--- a/miasm2/arch/arm/disasm.py
+++ b/miasm2/arch/arm/disasm.py
@@ -36,16 +36,24 @@ def cb_arm_disasm(mn, attrib, pool_bin, cur_bloc, offsets_to_dis, symbol_pool):
         func(mn, attrib, pool_bin, cur_bloc, offsets_to_dis, symbol_pool)
 
 
-class dis_arm(disasmEngine):
-    attrib = 'arm'
-
+class dis_armb(disasmEngine):
+    attrib = 'b'
     def __init__(self, bs=None, **kwargs):
-        super(dis_arm, self).__init__(mn_arm, self.attrib, bs, **kwargs)
+        super(dis_armb, self).__init__(mn_arm, self.attrib, bs, **kwargs)
         self.dis_bloc_callback = cb_arm_disasm
 
+class dis_arml(disasmEngine):
+    attrib = 'l'
+    def __init__(self, bs=None, **kwargs):
+        super(dis_arml, self).__init__(mn_arm, self.attrib, bs, **kwargs)
+        self.dis_bloc_callback = cb_arm_disasm
 
-class dis_armt(disasmEngine):
-    attrib = 'armt'
+class dis_armtb(disasmEngine):
+    attrib = 'b'
+    def __init__(self, bs=None, **kwargs):
+        super(dis_armtb, self).__init__(mn_armt, self.attrib, bs, **kwargs)
 
+class dis_armtl(disasmEngine):
+    attrib = 'l'
     def __init__(self, bs=None, **kwargs):
-        super(dis_armt, self).__init__(mn_armt, self.attrib, bs, **kwargs)
+        super(dis_armtl, self).__init__(mn_armt, self.attrib, bs, **kwargs)
diff --git a/miasm2/arch/arm/ira.py b/miasm2/arch/arm/ira.py
index b92800e7..8cfe2da0 100644
--- a/miasm2/arch/arm/ira.py
+++ b/miasm2/arch/arm/ira.py
@@ -4,22 +4,26 @@
 from miasm2.expression.expression import *
 from miasm2.ir.ir import ir, irbloc
 from miasm2.ir.analysis import ira
-from miasm2.arch.arm.sem import ir_arm, ir_armt
+from miasm2.arch.arm.sem import ir_arml, ir_armtl, ir_armb, ir_armtb
 from miasm2.arch.arm.regs import *
 # from miasm2.core.graph import DiGraph
 
 
-class ir_a_arm_base(ir_arm, ira):
+class ir_a_arml_base(ir_arml, ira):
+    def __init__(self, symbol_pool=None):
+        ir_arml.__init__(self, symbol_pool)
+        self.ret_reg = self.arch.regs.R0
 
+class ir_a_armb_base(ir_armb, ira):
     def __init__(self, symbol_pool=None):
-        ir_arm.__init__(self, symbol_pool)
+        ir_armb.__init__(self, symbol_pool)
         self.ret_reg = self.arch.regs.R0
 
 
-class ir_a_arm(ir_a_arm_base):
+class ir_a_arml(ir_a_arml_base):
 
     def __init__(self, symbol_pool=None):
-        ir_a_arm_base.__init__(self, symbol_pool)
+        ir_a_arml_base.__init__(self, symbol_pool)
         self.ret_reg = self.arch.regs.R0
 
     # for test XXX TODO
@@ -120,9 +124,19 @@ class ir_a_arm(ir_a_arm_base):
     def sizeof_pointer(self):
         return 32
 
+class ir_a_armb(ir_a_armb_base, ir_a_arml):
+
+    def __init__(self, symbol_pool=None):
+        ir_a_armb_base.__init__(self, symbol_pool)
+        self.ret_reg = self.arch.regs.R0
+
 
-class ir_a_armt(ir_armt, ir_a_arm):
+class ir_a_armtl(ir_armtl, ir_a_arml):
+    def __init__(self, symbol_pool):
+        ir_armtl.__init__(self, symbol_pool)
+        self.ret_reg = self.arch.regs.R0
 
+class ir_a_armtb(ir_a_armtl, ir_armtb, ir_a_armb):
     def __init__(self, symbol_pool):
-        ir_armt.__init__(self, symbol_pool)
+        ir_armtb.__init__(self, symbol_pool)
         self.ret_reg = self.arch.regs.R0
diff --git a/miasm2/arch/arm/jit.py b/miasm2/arch/arm/jit.py
index 2947674a..29b701df 100644
--- a/miasm2/arch/arm/jit.py
+++ b/miasm2/arch/arm/jit.py
@@ -1,7 +1,7 @@
 from miasm2.jitter.jitload import jitter
 from miasm2.core import asmbloc
 from miasm2.core.utils import *
-from miasm2.arch.arm.sem import ir_arm
+from miasm2.arch.arm.sem import ir_arml
 
 import logging
 
@@ -11,11 +11,12 @@ hnd.setFormatter(logging.Formatter("[%(levelname)s]: %(message)s"))
 log.addHandler(hnd)
 log.setLevel(logging.CRITICAL)
 
-class jitter_arm(jitter):
+class jitter_arml(jitter):
 
     def __init__(self, *args, **kwargs):
         sp = asmbloc.asm_symbol_pool()
-        jitter.__init__(self, ir_arm(sp), *args, **kwargs)
+        jitter.__init__(self, ir_arml(sp), *args, **kwargs)
+        self.vm.set_little_endian()
         self.ir_arch.jit_pc = self.ir_arch.arch.regs.PC
 
     def push_uint32_t(self, v):
@@ -87,3 +88,8 @@ class jitter_arm(jitter):
     def init_run(self, *args, **kwargs):
         jitter.init_run(self, *args, **kwargs)
         self.cpu.PC = self.pc
+
+class jitter_armb(jitter_arml):
+    def __init__(self, *args, **kwargs):
+        jitter_arml.__init__(self)
+        self.vm.set_big_endian()
diff --git a/miasm2/arch/arm/sem.py b/miasm2/arch/arm/sem.py
index 72625eab..e0e59555 100644
--- a/miasm2/arch/arm/sem.py
+++ b/miasm2/arch/arm/sem.py
@@ -1116,10 +1116,9 @@ class arminfo:
     # offset
 
 
-class ir_arm(ir):
-
+class ir_arml(ir):
     def __init__(self, symbol_pool=None):
-        ir.__init__(self, mn_arm, "arm", symbol_pool)
+        ir.__init__(self, mn_arm, "l", symbol_pool)
         self.pc = PC
         self.sp = SP
         self.IRDst = ExprId('IRDst', 32)
@@ -1152,10 +1151,16 @@ class ir_arm(ir):
         return instr_ir, extra_ir
 
 
-class ir_armt(ir):
+class ir_armb(ir_arml):
+    def __init__(self, symbol_pool=None):
+        ir.__init__(self, mn_arm, "b", symbol_pool)
+        self.pc = PC
+        self.sp = SP
+        self.IRDst = ExprId('IRDst', 32)
 
+class ir_armtl(ir):
     def __init__(self, symbol_pool=None):
-        ir.__init__(self, mn_armt, "armt", symbol_pool)
+        ir.__init__(self, mn_armt, "l", symbol_pool)
         self.pc = PC
         self.sp = SP
         self.IRDst = ExprId('IRDst', 32)
@@ -1163,3 +1168,10 @@ class ir_armt(ir):
     def get_ir(self, instr):
         return get_mnemo_expr(self, instr, *instr.args)
 
+class ir_armtb(ir_armtl):
+    def __init__(self, symbol_pool=None):
+        ir.__init__(self, mn_armt, "b", symbol_pool)
+        self.pc = PC
+        self.sp = SP
+        self.IRDst = ExprId('IRDst', 32)
+