diff options
Diffstat (limited to '')
| -rw-r--r-- | miasm2/arch/mips32/arch.py | 1 | ||||
| -rw-r--r-- | miasm2/arch/mips32/disasm.py | 2 | ||||
| -rw-r--r-- | miasm2/arch/mips32/ira.py | 38 | ||||
| -rw-r--r-- | miasm2/arch/mips32/jit.py | 25 | ||||
| -rw-r--r-- | miasm2/arch/mips32/sem.py | 55 |
5 files changed, 37 insertions, 84 deletions
diff --git a/miasm2/arch/mips32/arch.py b/miasm2/arch/mips32/arch.py index 79176205..f11c6e3a 100644 --- a/miasm2/arch/mips32/arch.py +++ b/miasm2/arch/mips32/arch.py @@ -9,7 +9,6 @@ from miasm2.expression.expression import ExprMem, ExprInt, ExprInt32, ExprId from miasm2.core.bin_stream import bin_stream import miasm2.arch.mips32.regs as regs import miasm2.core.cpu as cpu -from miasm2.core.asmbloc import asm_label log = logging.getLogger("mips32dis") console_handler = logging.StreamHandler() diff --git a/miasm2/arch/mips32/disasm.py b/miasm2/arch/mips32/disasm.py index e5a70349..bdd800d5 100644 --- a/miasm2/arch/mips32/disasm.py +++ b/miasm2/arch/mips32/disasm.py @@ -1,4 +1,4 @@ -from miasm2.core.asmbloc import disasmEngine +from miasm2.core.asmblock import disasmEngine from miasm2.arch.mips32.arch import mn_mips32 diff --git a/miasm2/arch/mips32/ira.py b/miasm2/arch/mips32/ira.py index 8f7b2df3..dd02ff50 100644 --- a/miasm2/arch/mips32/ira.py +++ b/miasm2/arch/mips32/ira.py @@ -1,34 +1,28 @@ #-*- coding:utf-8 -*- -from miasm2.expression.expression import * -from miasm2.ir.ir import ir, irbloc, AssignBlock +from miasm2.expression.expression import ExprAff, ExprInt32, ExprId +from miasm2.ir.ir import IntermediateRepresentation, IRBlock, AssignBlock from miasm2.ir.analysis import ira from miasm2.arch.mips32.sem import ir_mips32l, ir_mips32b -from miasm2.arch.mips32.regs import * -from miasm2.core.asmbloc import expr_is_int_or_label, expr_is_label +from miasm2.core.asmblock import expr_is_int_or_label, expr_is_label class ir_a_mips32l(ir_mips32l, ira): def __init__(self, symbol_pool=None): ir_mips32l.__init__(self, symbol_pool) self.ret_reg = self.arch.regs.V0 - - # for test XXX TODO - def set_dead_regs(self, b): - pass - def pre_add_instr(self, block, instr, irb_cur, ir_blocks_all, gen_pc_updt): # Avoid adding side effects, already done in post_add_bloc return irb_cur - def post_add_bloc(self, bloc, ir_blocs): - ir.post_add_bloc(self, bloc, ir_blocs) - for irb in ir_blocs: + def post_add_bloc(self, block, ir_blocks): + IntermediateRepresentation.post_add_bloc(self, block, ir_blocks) + for irb in ir_blocks: pc_val = None lr_val = None for assignblk in irb.irs: - pc_val = assignblk.get(PC, pc_val) - lr_val = assignblk.get(RA, lr_val) + pc_val = assignblk.get(self.arch.regs.PC, pc_val) + lr_val = assignblk.get(self.arch.regs.RA, lr_val) if pc_val is None or lr_val is None: continue @@ -37,22 +31,22 @@ class ir_a_mips32l(ir_mips32l, ira): if expr_is_label(lr_val): lr_val = ExprInt32(lr_val.name.offset) - l = bloc.lines[-2] - if lr_val.arg != l.offset + 8: + line = block.lines[-2] + if lr_val.arg != line.offset + 8: raise ValueError("Wrong arg") # CALL - lbl = bloc.get_next() + lbl = block.get_next() new_lbl = self.gen_label() - irs = self.call_effects(pc_val, l) + irs = self.call_effects(pc_val, line) irs.append(AssignBlock([ExprAff(self.IRDst, ExprId(lbl, size=self.pc.size))])) - nbloc = irbloc(new_lbl, irs) - nbloc.lines = [l] * len(irs) - self.blocs[new_lbl] = nbloc + nblock = IRBlock(new_lbl, irs) + nblock.lines = [line] * len(irs) + self.blocks[new_lbl] = nblock irb.dst = ExprId(new_lbl, size=self.pc.size) - def get_out_regs(self, b): + def get_out_regs(self, _): return set([self.ret_reg, self.sp]) def sizeof_char(self): diff --git a/miasm2/arch/mips32/jit.py b/miasm2/arch/mips32/jit.py index 332e8d13..0ba531f1 100644 --- a/miasm2/arch/mips32/jit.py +++ b/miasm2/arch/mips32/jit.py @@ -1,8 +1,8 @@ import logging from miasm2.jitter.jitload import jitter -from miasm2.core import asmbloc -from miasm2.core.utils import * +from miasm2.core import asmblock +from miasm2.core.utils import pck32, upck32 from miasm2.arch.mips32.sem import ir_mips32l, ir_mips32b from miasm2.jitter.codegen import CGen import miasm2.expression.expression as m2_expr @@ -43,7 +43,7 @@ class mipsCGen(CGen): if not instr.breakflow(): continue for irblock in irblocks: - for i, assignblock in enumerate(irblock.irs): + for assignblock in irblock.irs: if self.ir_arch.pc not in assignblock: continue # Add internal branch destination @@ -68,7 +68,7 @@ class mipsCGen(CGen): m2_expr.ExprId('branch_dst_irdst'), m2_expr.ExprId('branch_dst_irdst'), self.id_to_c(m2_expr.ExprInt(lbl.offset, 32))) - ).split('\n') + ).split('\n') return out @@ -77,22 +77,21 @@ class jitter_mips32l(jitter): C_Gen = mipsCGen def __init__(self, *args, **kwargs): - sp = asmbloc.asm_symbol_pool() + sp = asmblock.AsmSymbolPool() jitter.__init__(self, ir_mips32l(sp), *args, **kwargs) self.vm.set_little_endian() - def push_uint32_t(self, v): + def push_uint32_t(self, value): self.cpu.SP -= 4 - self.vm.set_mem(self.cpu.SP, pck32(v)) + self.vm.set_mem(self.cpu.SP, pck32(value)) def pop_uint32_t(self): - x = upck32(self.vm.get_mem(self.cpu.SP, 4)) + value = upck32(self.vm.get_mem(self.cpu.SP, 4)) self.cpu.SP += 4 - return x + return value - def get_stack_arg(self, n): - x = upck32(self.vm.get_mem(self.cpu.SP + 4 * n, 4)) - return x + def get_stack_arg(self, index): + return upck32(self.vm.get_mem(self.cpu.SP + 4 * index, 4)) def init_run(self, *args, **kwargs): jitter.init_run(self, *args, **kwargs) @@ -102,6 +101,6 @@ class jitter_mips32l(jitter): class jitter_mips32b(jitter_mips32l): def __init__(self, *args, **kwargs): - sp = asmbloc.asm_symbol_pool() + sp = asmblock.AsmSymbolPool() jitter.__init__(self, ir_mips32b(sp), *args, **kwargs) self.vm.set_big_endian() diff --git a/miasm2/arch/mips32/sem.py b/miasm2/arch/mips32/sem.py index b52b8401..d982f033 100644 --- a/miasm2/arch/mips32/sem.py +++ b/miasm2/arch/mips32/sem.py @@ -1,5 +1,5 @@ import miasm2.expression.expression as m2_expr -from miasm2.ir.ir import ir, irbloc +from miasm2.ir.ir import IntermediateRepresentation, IRBlock from miasm2.arch.mips32.arch import mn_mips32 from miasm2.arch.mips32.regs import R_LO, R_HI, PC, RA from miasm2.core.sembuilder import SemBuilder @@ -429,10 +429,10 @@ def get_mnemo_expr(ir, instr, *args): instr, extra_ir = mnemo_func[instr.name.lower()](ir, instr, *args) return instr, extra_ir -class ir_mips32l(ir): +class ir_mips32l(IntermediateRepresentation): def __init__(self, symbol_pool=None): - ir.__init__(self, mn_mips32, 'l', symbol_pool) + IntermediateRepresentation.__init__(self, mn_mips32, 'l', symbol_pool) self.pc = mn_mips32.getpc() self.sp = mn_mips32.getsp() self.IRDst = m2_expr.ExprId('IRDst', 32) @@ -445,8 +445,8 @@ class ir_mips32l(ir): x = m2_expr.ExprAff(x.dst, x.src.replace_expr( {self.pc: m2_expr.ExprInt32(instr.offset + 4)})) instr_ir[i] = x - for b in extra_ir: - for irs in b.irs: + for irblock in extra_ir: + for irs in irblock.irs: for i, x in enumerate(irs): x = m2_expr.ExprAff(x.dst, x.src.replace_expr( {self.pc: m2_expr.ExprInt32(instr.offset + 4)})) @@ -454,53 +454,14 @@ class ir_mips32l(ir): return instr_ir, extra_ir def get_next_instr(self, instr): - l = self.symbol_pool.getby_offset_create(instr.offset + 4) - return l + return self.symbol_pool.getby_offset_create(instr.offset + 4) def get_next_break_label(self, instr): - l = self.symbol_pool.getby_offset_create(instr.offset + 8) - return l - """ - def add_bloc(self, bloc, gen_pc_updt = False): - c = None - ir_blocs_all = [] - for l in bloc.lines: - if c is None: - # print 'new c' - label = self.get_label(l) - c = irbloc(label, [], []) - ir_blocs_all.append(c) - bloc_dst = None - # print 'Translate', l - dst, ir_bloc_cur, ir_blocs_extra = self.instr2ir(l) - # print ir_bloc_cur - # for xxx in ir_bloc_cur: - # print "\t", xxx - assert((dst is None) or (bloc_dst is None)) - bloc_dst = dst - #if bloc_dst is not None: - # c.dst = bloc_dst - if dst is not None: - ir_bloc_cur.append(m2_expr.ExprAff(PC_FETCH, dst)) - c.dst = PC_FETCH - if gen_pc_updt is not False: - self.gen_pc_update(c, l) - - c.irs.append(ir_bloc_cur) - c.lines.append(l) - if ir_blocs_extra: - # print 'split' - for b in ir_blocs_extra: - b.lines = [l] * len(b.irs) - ir_blocs_all += ir_blocs_extra - c = None - self.post_add_bloc(bloc, ir_blocs_all) - return ir_blocs_all - """ + return self.symbol_pool.getby_offset_create(instr.offset + 8) class ir_mips32b(ir_mips32l): def __init__(self, symbol_pool=None): - ir.__init__(self, mn_mips32, 'b', symbol_pool) + IntermediateRepresentation.__init__(self, mn_mips32, 'b', symbol_pool) self.pc = mn_mips32.getpc() self.sp = mn_mips32.getsp() self.IRDst = m2_expr.ExprId('IRDst', 32) |