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-rw-r--r--miasm2/arch/mips32/ira.py10
-rw-r--r--miasm2/arch/mips32/jit.py12
2 files changed, 13 insertions, 9 deletions
diff --git a/miasm2/arch/mips32/ira.py b/miasm2/arch/mips32/ira.py
index 92af5cc5..a2eab4fb 100644
--- a/miasm2/arch/mips32/ira.py
+++ b/miasm2/arch/mips32/ira.py
@@ -31,18 +31,18 @@ class ir_a_mips32l(ir_mips32l, ira):
             if expr_is_label(lr_val):
                 lr_val = ExprInt(lr_val.name.offset, 32)
 
-            line = block.lines[-2]
-            if lr_val.arg != line.offset + 8:
+            instr = block.irs[-2].instr
+            if lr_val.arg != instr.offset + 8:
                 raise ValueError("Wrong arg")
 
             # CALL
             lbl = block.get_next()
             new_lbl = self.gen_label()
-            irs = self.call_effects(pc_val, line)
+            irs = self.call_effects(pc_val, instr)
             irs.append(AssignBlock([ExprAff(self.IRDst,
-                                            ExprId(lbl, size=self.pc.size))]))
+                                            ExprId(lbl, size=self.pc.size))],
+                                   instr))
             nblock = IRBlock(new_lbl, irs)
-            nblock.lines = [line] * len(irs)
             self.blocks[new_lbl] = nblock
             irb.dst = ExprId(new_lbl, size=self.pc.size)
 
diff --git a/miasm2/arch/mips32/jit.py b/miasm2/arch/mips32/jit.py
index bfa9c5fd..9b46589f 100644
--- a/miasm2/arch/mips32/jit.py
+++ b/miasm2/arch/mips32/jit.py
@@ -5,6 +5,7 @@ from miasm2.core import asmblock
 from miasm2.core.utils import pck32, upck32
 from miasm2.arch.mips32.sem import ir_mips32l, ir_mips32b
 from miasm2.jitter.codegen import CGen
+from miasm2.ir.ir import AssignBlock
 import miasm2.expression.expression as m2_expr
 
 log = logging.getLogger('jit_mips32')
@@ -43,18 +44,21 @@ class mipsCGen(CGen):
             if not instr.breakflow():
                 continue
             for irblock in irblocks:
-                for assignblock in irblock.irs:
+                for idx, assignblock in enumerate(irblock.irs):
                     if self.ir_arch.pc not in assignblock:
                         continue
+                    new_assignblock = dict(assignblock)
                     # Add internal branch destination
-                    assignblock[self.delay_slot_dst] = assignblock[
+                    new_assignblock[self.delay_slot_dst] = assignblock[
                         self.ir_arch.pc]
-                    assignblock[self.delay_slot_set] = m2_expr.ExprInt(1, 32)
+                    new_assignblock[self.delay_slot_set] = m2_expr.ExprInt(1, 32)
                     # Replace IRDst with next instruction
-                    assignblock[self.ir_arch.IRDst] = m2_expr.ExprId(
+                    new_assignblock[self.ir_arch.IRDst] = m2_expr.ExprId(
                         self.ir_arch.get_next_instr(instr))
                     irblock.dst = m2_expr.ExprId(
                         self.ir_arch.get_next_instr(instr))
+                    irblock.irs[idx] = AssignBlock(new_assignblock, assignblock.instr)
+
         return irblocks_list
 
     def gen_finalize(self, block):