2 files changed, 5 insertions, 4 deletions
diff --git a/miasm2/arch/mips32/jit.py b/miasm2/arch/mips32/jit.py
index 93223896..aca85de5 100644
--- a/miasm2/arch/mips32/jit.py
+++ b/miasm2/arch/mips32/jit.py
@@ -1,9 +1,10 @@
+import logging
+
 from miasm2.jitter.jitload import jitter
 from miasm2.core import asmbloc
 from miasm2.core.utils import *
 from miasm2.arch.mips32.sem import ir_mips32l, ir_mips32b
-
-import logging
+from miasm2.jitter.codegen import CGen
 
 log = logging.getLogger('jit_mips32')
 hnd = logging.StreamHandler()
@@ -17,7 +18,6 @@ class jitter_mips32l(jitter):
         sp = asmbloc.asm_symbol_pool()
         jitter.__init__(self, ir_mips32l(sp), *args, **kwargs)
         self.vm.set_little_endian()
-        self.ir_arch.jit_pc = self.ir_arch.arch.regs.PC
 
     def push_uint32_t(self, v):
         self.cpu.SP -= 4
@@ -42,4 +42,3 @@ class jitter_mips32b(jitter_mips32l):
         sp = asmbloc.asm_symbol_pool()
         jitter.__init__(self, ir_mips32b(sp), *args, **kwargs)
         self.vm.set_big_endian()
-        self.ir_arch.jit_pc = self.ir_arch.arch.regs.PC
diff --git a/miasm2/arch/mips32/regs.py b/miasm2/arch/mips32/regs.py
index 6ddcf25b..b64b40d5 100644
--- a/miasm2/arch/mips32/regs.py
+++ b/miasm2/arch/mips32/regs.py
@@ -11,6 +11,8 @@ gen_reg('PC_FETCH', globals())
 gen_reg('R_LO', globals())
 gen_reg('R_HI', globals())
 
+exception_flags = ExprId('exception_flags', 32)
+
 PC_init = ExprId("PC_init")
 PC_FETCH_init = ExprId("PC_FETCH_init")