diff options
Diffstat (limited to 'miasm2/arch/mips32')
| -rw-r--r-- | miasm2/arch/mips32/arch.py | 24 | ||||
| -rw-r--r-- | miasm2/arch/mips32/sem.py | 10 |
2 files changed, 17 insertions, 17 deletions
diff --git a/miasm2/arch/mips32/arch.py b/miasm2/arch/mips32/arch.py index f963737e..75a1aff0 100644 --- a/miasm2/arch/mips32/arch.py +++ b/miasm2/arch/mips32/arch.py @@ -69,7 +69,7 @@ class instruction_mips32(cpu.instruction): else: return str(expr) assert(isinstance(expr, ExprMem)) - arg = expr.arg + arg = expr.ptr if isinstance(arg, ExprId): return "(%s)"%arg assert(len(arg.args) == 2 and arg.op == '+') @@ -394,13 +394,13 @@ class mips32_dreg_imm(mips32_arg): e = self.expr if not isinstance(e, ExprMem): return False - arg = e.arg - if isinstance(arg, ExprId): + ptr = e.ptr + if isinstance(ptr, ExprId): self.parent.imm.expr = ExprInt(0, 32) - r = arg - elif len(arg.args) == 2 and arg.op == "+": - self.parent.imm.expr = arg.args[1] - r = arg.args[0] + r = ptr + elif len(ptr.args) == 2 and ptr.op == "+": + self.parent.imm.expr = ptr.args[1] + r = ptr.args[0] else: return False self.value = gpregs.expr.index(r) @@ -409,11 +409,11 @@ class mips32_dreg_imm(mips32_arg): @staticmethod def arg2str(expr, index=None): assert(isinstance(expr, ExprMem)) - arg = expr.arg - if isinstance(arg, ExprId): - return "(%s)"%arg - assert(len(arg.args) == 2 and arg.op == '+') - return "%s(%s)"%(arg.args[1], arg.args[0]) + ptr = expr.ptr + if isinstance(ptr, ExprId): + return "(%s)"%ptr + assert(len(ptr.args) == 2 and ptr.op == '+') + return "%s(%s)"%(ptr.args[1], ptr.args[0]) class mips32_esize(mips32_imm, mips32_arg): def decode(self, v): diff --git a/miasm2/arch/mips32/sem.py b/miasm2/arch/mips32/sem.py index a603e7c3..a57d2200 100644 --- a/miasm2/arch/mips32/sem.py +++ b/miasm2/arch/mips32/sem.py @@ -64,18 +64,18 @@ def l_b(arg1): def lbu(arg1, arg2): """A byte is loaded (unsigned extended) into a register @arg1 from the specified address @arg2.""" - arg1 = mem8[arg2.arg].zeroExtend(32) + arg1 = mem8[arg2.ptr].zeroExtend(32) @sbuild.parse def lhu(arg1, arg2): """A word is loaded (unsigned extended) into a register @arg1 from the specified address @arg2.""" - arg1 = mem16[arg2.arg].zeroExtend(32) + arg1 = mem16[arg2.ptr].zeroExtend(32) @sbuild.parse def lb(arg1, arg2): "A byte is loaded into a register @arg1 from the specified address @arg2." - arg1 = mem8[arg2.arg].signExtend(32) + arg1 = mem8[arg2.ptr].signExtend(32) @sbuild.parse def beq(arg1, arg2, arg3): @@ -174,11 +174,11 @@ def l_sub(arg1, arg2, arg3): def sb(arg1, arg2): """The least significant byte of @arg1 is stored at the specified address @arg2.""" - mem8[arg2.arg] = arg1[:8] + mem8[arg2.ptr] = arg1[:8] @sbuild.parse def sh(arg1, arg2): - mem16[arg2.arg] = arg1[:16] + mem16[arg2.ptr] = arg1[:16] @sbuild.parse def movn(arg1, arg2, arg3): |