diff options
Diffstat (limited to 'miasm2/arch/mips32')
| -rw-r--r-- | miasm2/arch/mips32/arch.py | 6 | ||||
| -rw-r--r-- | miasm2/arch/mips32/jit.py | 7 | ||||
| -rw-r--r-- | miasm2/arch/mips32/regs.py | 15 |
3 files changed, 15 insertions, 13 deletions
diff --git a/miasm2/arch/mips32/arch.py b/miasm2/arch/mips32/arch.py index 75a1aff0..6046b12c 100644 --- a/miasm2/arch/mips32/arch.py +++ b/miasm2/arch/mips32/arch.py @@ -42,7 +42,7 @@ deref_nooff = (LPARENTHESIS + gpregs.parser + RPARENTHESIS).setParseAction(cb_de deref = deref_off | deref_nooff -class additional_info: +class additional_info(object): def __init__(self): self.except_on_instr = False @@ -200,7 +200,7 @@ class mn_mips32(cpu.cls_mn): return 0 o = 0 while n: - offset = start / 8 + offset = start // 8 n_offset = cls.endian_offset(attrib, offset) c = cls.getbytes(bitstream, n_offset, 1) if not c: @@ -265,7 +265,7 @@ class mips32_arg(cpu.m_arg): return arg.name if arg.name in gpregs.str: return None - loc_key = loc_db.get_or_create_name_location(arg.name) + loc_key = loc_db.get_or_create_name_location(arg.name.encode()) return ExprLoc(loc_key, 32) if isinstance(arg, AstOp): args = [self.asm_ast_to_expr(tmp, loc_db) for tmp in arg.args] diff --git a/miasm2/arch/mips32/jit.py b/miasm2/arch/mips32/jit.py index 4abe0cd4..04690a3e 100644 --- a/miasm2/arch/mips32/jit.py +++ b/miasm2/arch/mips32/jit.py @@ -1,3 +1,4 @@ +from builtins import range import logging from miasm2.jitter.jitload import Jitter, named_arguments @@ -109,7 +110,7 @@ class jitter_mips32l(Jitter): @named_arguments def func_args_stdcall(self, n_args): - args = [self.get_arg_n_stdcall(i) for i in xrange(n_args)] + args = [self.get_arg_n_stdcall(i) for i in range(n_args)] ret_ad = self.cpu.RA return ret_ad, args @@ -122,9 +123,9 @@ class jitter_mips32l(Jitter): return True def func_prepare_stdcall(self, ret_addr, *args): - for index in xrange(min(len(args), 4)): + for index in range(min(len(args), 4)): setattr(self.cpu, 'A%d' % index, args[index]) - for index in xrange(4, len(args)): + for index in range(4, len(args)): self.vm.set_mem(self.cpu.SP + 4 * (index - 4), pck32(args[index])) self.cpu.RA = ret_addr diff --git a/miasm2/arch/mips32/regs.py b/miasm2/arch/mips32/regs.py index ddaaff79..d1d14bdc 100644 --- a/miasm2/arch/mips32/regs.py +++ b/miasm2/arch/mips32/regs.py @@ -1,5 +1,6 @@ #-*- coding:utf-8 -*- +from builtins import range from miasm2.expression.expression import ExprId from miasm2.core.cpu import gen_reg, gen_regs @@ -16,19 +17,19 @@ PC_init = ExprId("PC_init", 32) PC_FETCH_init = ExprId("PC_FETCH_init", 32) regs32_str = ["ZERO", 'AT', 'V0', 'V1'] +\ - ['A%d'%i for i in xrange(4)] +\ - ['T%d'%i for i in xrange(8)] +\ - ['S%d'%i for i in xrange(8)] +\ - ['T%d'%i for i in xrange(8, 10)] +\ + ['A%d'%i for i in range(4)] +\ + ['T%d'%i for i in range(8)] +\ + ['S%d'%i for i in range(8)] +\ + ['T%d'%i for i in range(8, 10)] +\ ['K0', 'K1'] +\ ['GP', 'SP', 'FP', 'RA'] regs32_expr = [ExprId(x, 32) for x in regs32_str] ZERO = regs32_expr[0] -regs_flt_str = ['F%d'%i for i in xrange(0x20)] +regs_flt_str = ['F%d'%i for i in range(0x20)] -regs_fcc_str = ['FCC%d'%i for i in xrange(8)] +regs_fcc_str = ['FCC%d'%i for i in range(8)] R_LO = ExprId('R_LO', 32) R_HI = ExprId('R_HI', 32) @@ -37,7 +38,7 @@ R_LO_init = ExprId('R_LO_init', 32) R_HI_init = ExprId('R_HI_init', 32) -cpr0_str = ["CPR0_%d"%x for x in xrange(0x100)] +cpr0_str = ["CPR0_%d"%x for x in range(0x100)] cpr0_str[0] = "INDEX" cpr0_str[16] = "ENTRYLO0" cpr0_str[24] = "ENTRYLO1" |