5 files changed, 28 insertions, 33 deletions
diff --git a/miasm2/arch/msp430/arch.py b/miasm2/arch/msp430/arch.py
index d7463f3d..07ba3019 100644
--- a/miasm2/arch/msp430/arch.py
+++ b/miasm2/arch/msp430/arch.py
@@ -8,7 +8,6 @@ from collections import defaultdict
 from miasm2.core.bin_stream import bin_stream
 import miasm2.arch.msp430.regs as regs_module
 from miasm2.arch.msp430.regs import *
-from miasm2.core.asmbloc import asm_label
 
 log = logging.getLogger("msp430dis")
 console_handler = logging.StreamHandler()
diff --git a/miasm2/arch/msp430/disasm.py b/miasm2/arch/msp430/disasm.py
index ac5d9cce..849cd675 100644
--- a/miasm2/arch/msp430/disasm.py
+++ b/miasm2/arch/msp430/disasm.py
@@ -1,4 +1,4 @@
-from miasm2.core.asmbloc import disasmEngine
+from miasm2.core.asmblock import disasmEngine
 from miasm2.arch.msp430.arch import mn_msp430
 
 
diff --git a/miasm2/arch/msp430/ira.py b/miasm2/arch/msp430/ira.py
index 071bfae8..0dc63c61 100644
--- a/miasm2/arch/msp430/ira.py
+++ b/miasm2/arch/msp430/ira.py
@@ -1,11 +1,7 @@
 #-*- coding:utf-8 -*-
 
-from miasm2.expression.expression import *
-from miasm2.ir.ir import ir, irbloc, AssignBlock
 from miasm2.ir.analysis import ira
 from miasm2.arch.msp430.sem import ir_msp430
-from miasm2.arch.msp430.regs import *
-# from miasm2.core.graph import DiGraph
 
 
 class ir_a_msp430_base(ir_msp430, ira):
@@ -21,19 +17,19 @@ class ir_a_msp430(ir_a_msp430_base):
         ir_a_msp430_base.__init__(self, symbol_pool)
 
     # for test XXX TODO
-    def set_dead_regs(self, b):
-        b.rw[-1][1].add(self.arch.regs.zf)
-        b.rw[-1][1].add(self.arch.regs.nf)
-        b.rw[-1][1].add(self.arch.regs.of)
-        b.rw[-1][1].add(self.arch.regs.cf)
-
-        b.rw[-1][1].add(self.arch.regs.res)
-        b.rw[-1][1].add(self.arch.regs.scg1)
-        b.rw[-1][1].add(self.arch.regs.scg0)
-        b.rw[-1][1].add(self.arch.regs.osc)
-        b.rw[-1][1].add(self.arch.regs.cpuoff)
-        b.rw[-1][1].add(self.arch.regs.gie)
-
-    def get_out_regs(self, b):
+    def set_dead_regs(self, irblock):
+        irblock.rw[-1][1].add(self.arch.regs.zf)
+        irblock.rw[-1][1].add(self.arch.regs.nf)
+        irblock.rw[-1][1].add(self.arch.regs.of)
+        irblock.rw[-1][1].add(self.arch.regs.cf)
+
+        irblock.rw[-1][1].add(self.arch.regs.res)
+        irblock.rw[-1][1].add(self.arch.regs.scg1)
+        irblock.rw[-1][1].add(self.arch.regs.scg0)
+        irblock.rw[-1][1].add(self.arch.regs.osc)
+        irblock.rw[-1][1].add(self.arch.regs.cpuoff)
+        irblock.rw[-1][1].add(self.arch.regs.gie)
+
+    def get_out_regs(self, _):
         return set([self.ret_reg, self.sp])
 
diff --git a/miasm2/arch/msp430/jit.py b/miasm2/arch/msp430/jit.py
index 95d34f96..dd5fe94e 100644
--- a/miasm2/arch/msp430/jit.py
+++ b/miasm2/arch/msp430/jit.py
@@ -1,6 +1,6 @@
 from miasm2.jitter.jitload import jitter
-from miasm2.core import asmbloc
-from miasm2.core.utils import *
+from miasm2.core import asmblock
+from miasm2.core.utils import pck16, upck16
 from miasm2.arch.msp430.sem import ir_msp430
 
 import logging
@@ -14,27 +14,27 @@ log.setLevel(logging.CRITICAL)
 class jitter_msp430(jitter):
 
     def __init__(self, *args, **kwargs):
-        sp = asmbloc.asm_symbol_pool()
+        sp = asmblock.AsmSymbolPool()
         jitter.__init__(self, ir_msp430(sp), *args, **kwargs)
         self.vm.set_little_endian()
 
-    def push_uint16_t(self, v):
+    def push_uint16_t(self, value):
         regs = self.cpu.get_gpreg()
         regs['SP'] -= 2
         self.cpu.set_gpreg(regs)
-        self.vm.set_mem(regs['SP'], pck16(v))
+        self.vm.set_mem(regs['SP'], pck16(value))
 
     def pop_uint16_t(self):
         regs = self.cpu.get_gpreg()
-        x = upck16(self.vm.get_mem(regs['SP'], 2))
+        value = upck16(self.vm.get_mem(regs['SP'], 2))
         regs['SP'] += 2
         self.cpu.set_gpreg(regs)
-        return x
+        return value
 
-    def get_stack_arg(self, n):
+    def get_stack_arg(self, index):
         regs = self.cpu.get_gpreg()
-        x = upck16(self.vm.get_mem(regs['SP'] + 2 * n, 2))
-        return x
+        value = upck16(self.vm.get_mem(regs['SP'] + 2 * index, 2))
+        return value
 
     def init_run(self, *args, **kwargs):
         jitter.init_run(self, *args, **kwargs)
diff --git a/miasm2/arch/msp430/sem.py b/miasm2/arch/msp430/sem.py
index 4b52361d..e8eb91cc 100644
--- a/miasm2/arch/msp430/sem.py
+++ b/miasm2/arch/msp430/sem.py
@@ -3,7 +3,7 @@
 from miasm2.expression.expression import *
 from miasm2.arch.msp430.regs import *
 from miasm2.arch.msp430.arch import mn_msp430
-from miasm2.ir.ir import ir
+from miasm2.ir.ir import IntermediateRepresentation
 
 
 # Utils
@@ -412,10 +412,10 @@ def ComposeExprAff(dst, src):
     return e
 
 
-class ir_msp430(ir):
+class ir_msp430(IntermediateRepresentation):
 
     def __init__(self, symbol_pool=None):
-        ir.__init__(self, mn_msp430, None, symbol_pool)
+        IntermediateRepresentation.__init__(self, mn_msp430, None, symbol_pool)
         self.pc = PC
         self.sp = SP
         self.IRDst = ExprId('IRDst', 16)