diff options
Diffstat (limited to 'miasm2/arch/msp430')
| -rw-r--r-- | miasm2/arch/msp430/arch.py | 14 | ||||
| -rw-r--r-- | miasm2/arch/msp430/sem.py | 30 |
2 files changed, 22 insertions, 22 deletions
diff --git a/miasm2/arch/msp430/arch.py b/miasm2/arch/msp430/arch.py index 07ba3019..9728d776 100644 --- a/miasm2/arch/msp430/arch.py +++ b/miasm2/arch/msp430/arch.py @@ -75,7 +75,7 @@ def ast_id2expr(t): def ast_int2expr(a): - return ExprInt16(a) + return ExprInt(a, 16) variable, operand, base_expr = gen_base_expr() @@ -328,12 +328,12 @@ class msp430_sreg_arg(reg_noarg, m_arg): self.expr = e elif self.parent.a_s.value == 0b01: if e == SR: - self.expr = ExprMem(ExprInt16(self.parent.off_s.value), size) + self.expr = ExprMem(ExprInt(self.parent.off_s.value, 16), size) elif e == R3: self.expr = ExprInt(1, size) else: self.expr = ExprMem( - e + ExprInt16(self.parent.off_s.value), size) + e + ExprInt(self.parent.off_s.value, 16), size) elif self.parent.a_s.value == 0b10: if e == SR: self.expr = ExprInt(4, size) @@ -431,9 +431,9 @@ class msp430_dreg_arg(msp430_sreg_arg): self.expr = e elif self.parent.a_d.value == 1: if e == SR: - x = ExprInt16(self.parent.off_d.value) + x = ExprInt(self.parent.off_d.value, 16) else: - x = e + ExprInt16(self.parent.off_d.value) + x = e + ExprInt(self.parent.off_d.value, 16) self.expr = ExprMem(x, size) else: raise NotImplementedError( @@ -448,7 +448,7 @@ class msp430_dreg_arg(msp430_sreg_arg): self.value = self.reg_info.expr.index(e) elif isinstance(e, ExprMem): if isinstance(e.arg, ExprId): - r, i = e.arg, ExprInt16(0) + r, i = e.arg, ExprInt(0, 16) elif isinstance(e.arg, ExprOp): r, i = e.arg.args[0], e.arg.args[1] elif isinstance(e.arg, ExprInt): @@ -538,7 +538,7 @@ class msp430_offs(imm_noarg, m_arg): if (1 << (self.l - 1)) & v: v |= ~0 ^ self.lmask v = self.decodeval(v) - self.expr = ExprInt16(v) + self.expr = ExprInt(v, 16) return True def encode(self): diff --git a/miasm2/arch/msp430/sem.py b/miasm2/arch/msp430/sem.py index e8eb91cc..5bf2999f 100644 --- a/miasm2/arch/msp430/sem.py +++ b/miasm2/arch/msp430/sem.py @@ -53,7 +53,7 @@ def update_flag_zn_r(a): def update_flag_sub_cf(a, b, c): return [ExprAff(cf, - ((((a ^ b) ^ c) ^ ((a ^ c) & (a ^ b))).msb()) ^ ExprInt1(1))] + ((((a ^ b) ^ c) ^ ((a ^ c) & (a ^ b))).msb()) ^ ExprInt(1, 1))] def update_flag_add_cf(a, b, c): @@ -77,7 +77,7 @@ def mng_autoinc(a, b, size): e.append(ExprAff(a_r, a_r + ExprInt(size / 8, a_r.size))) a = ExprMem(a_r, size) if isinstance(b, ExprMem) and a_r in b.arg: - b = ExprMem(b.arg + ExprInt16(size / 8), b.size) + b = ExprMem(b.arg + ExprInt(size / 8, 16), b.size) return e, a, b # Mnemonics @@ -108,7 +108,7 @@ def and_b(ir, instr, a, b): e.append(ExprAff(b, c.zeroExtend(16))) e += update_flag_zn_r(c) e += update_flag_cf_inv_zf(c) - e += [ExprAff(of, ExprInt1(0))] + e += [ExprAff(of, ExprInt(0, 1))] return e, [] @@ -118,13 +118,13 @@ def and_w(ir, instr, a, b): e.append(ExprAff(b, c)) e += update_flag_zn_r(c) e += update_flag_cf_inv_zf(c) - e += [ExprAff(of, ExprInt1(0))] + e += [ExprAff(of, ExprInt(0, 1))] return e, [] def bic_b(ir, instr, a, b): e, a, b = mng_autoinc(a, b, 8) - c = (a[:8] ^ ExprInt8(0xff)) & b[:8] + c = (a[:8] ^ ExprInt(0xff, 8)) & b[:8] c = c.zeroExtend(b.size) e.append(ExprAff(b, c)) return e, [] @@ -132,7 +132,7 @@ def bic_b(ir, instr, a, b): def bic_w(ir, instr, a, b): e, a, b = mng_autoinc(a, b, 16) - c = (a ^ ExprInt16(0xffff)) & b + c = (a ^ ExprInt(0xffff, 16)) & b e.append(ExprAff(b, c)) return e, [] @@ -149,7 +149,7 @@ def bit_w(ir, instr, a, b): c = a & b e += update_flag_zn_r(c) e += update_flag_cf_inv_zf(c) - e.append(ExprAff(of, ExprInt1(0))) + e.append(ExprAff(of, ExprInt(0, 1))) return e, [] """ @@ -231,16 +231,16 @@ def xor_w(ir, instr, a, b): def push_w(ir, instr, a): e = [] - e.append(ExprAff(ExprMem(SP - ExprInt16(2), 16), a)) - e.append(ExprAff(SP, SP - ExprInt16(2))) + e.append(ExprAff(ExprMem(SP - ExprInt(2, 16), 16), a)) + e.append(ExprAff(SP, SP - ExprInt(2, 16))) return e, [] def call(ir, instr, a): e, a, dummy = mng_autoinc(a, None, 16) n = ExprId(ir.get_next_label(instr), 16) - e.append(ExprAff(ExprMem(SP - ExprInt16(2), 16), n)) - e.append(ExprAff(SP, SP - ExprInt16(2))) + e.append(ExprAff(ExprMem(SP - ExprInt(2, 16), 16), n)) + e.append(ExprAff(SP, SP - ExprInt(2, 16))) e.append(ExprAff(PC, a)) e.append(ExprAff(ir.IRDst, a)) return e, [] @@ -338,7 +338,7 @@ def rrc_w(ir, instr, a): # e += update_flag_nf(a) e += reset_sr_res() - e.append(ExprAff(of, ExprInt1(0))) + e.append(ExprAff(of, ExprInt(0, 1))) return e, [] @@ -355,7 +355,7 @@ def rra_w(ir, instr, a): # e += update_flag_nf(a) e += reset_sr_res() - e.append(ExprAff(of, ExprInt1(0))) + e.append(ExprAff(of, ExprInt(0, 1))) return e, [] @@ -366,7 +366,7 @@ def sxt(ir, instr, a): e += update_flag_zn_r(c) e += update_flag_cf_inv_zf(c) - e.append(ExprAff(of, ExprInt1(0))) + e.append(ExprAff(of, ExprInt(0, 1))) return e, [] @@ -441,7 +441,7 @@ class ir_msp430(IntermediateRepresentation): instr_ir[i:i+1] = xx for i, x in enumerate(instr_ir): x = ExprAff(x.dst, x.src.replace_expr( - {self.pc: ExprInt16(instr.offset + instr.l)})) + {self.pc: ExprInt(instr.offset + instr.l, 16)})) instr_ir[i] = x if extra_ir: |