diff options
Diffstat (limited to 'miasm2/arch/ppc')
| -rw-r--r-- | miasm2/arch/ppc/arch.py | 9 | ||||
| -rw-r--r-- | miasm2/arch/ppc/jit.py | 7 | ||||
| -rw-r--r-- | miasm2/arch/ppc/regs.py | 11 | ||||
| -rw-r--r-- | miasm2/arch/ppc/sem.py | 19 |
4 files changed, 26 insertions, 20 deletions
diff --git a/miasm2/arch/ppc/arch.py b/miasm2/arch/ppc/arch.py index 37acc1c5..e7661371 100644 --- a/miasm2/arch/ppc/arch.py +++ b/miasm2/arch/ppc/arch.py @@ -1,3 +1,4 @@ +from builtins import range import logging from pyparsing import * @@ -40,7 +41,7 @@ class ppc_arg(m_arg): return arg.name if arg.name in gpregs.str: return None - loc_key = loc_db.get_or_create_name_location(arg.name) + loc_key = loc_db.get_or_create_name_location(arg.name.encode()) return ExprLoc(loc_key, 32) if isinstance(arg, AstOp): args = [self.asm_ast_to_expr(tmp, loc_db) for tmp in arg.args] @@ -57,7 +58,7 @@ class ppc_arg(m_arg): return None -class additional_info: +class additional_info(object): def __init__(self): self.except_on_instr = False @@ -227,7 +228,7 @@ class mn_ppc(cls_mn): if n > bs.getlen() * 8: raise ValueError('not enough bits %r %r' % (n, len(bs.bin) * 8)) while n: - offset = start / 8 + offset = start // 8 n_offset = cls.endian_offset(attrib, offset) c = cls.getbytes(bs, n_offset, 1) if not c: @@ -468,7 +469,7 @@ def ppc_bo_bi_to_mnemo(bo, bi, prefer_taken=True, default_taken=True): def ppc_all_bo_bi(): for bo in [0, 2, 4, 8, 10, 12, 16, 18, 20]: - for bi in xrange(4): + for bi in range(4): yield bo, bi class ppc_divert_conditional_branch(bs_divert): diff --git a/miasm2/arch/ppc/jit.py b/miasm2/arch/ppc/jit.py index 14c203a9..8dc4aa99 100644 --- a/miasm2/arch/ppc/jit.py +++ b/miasm2/arch/ppc/jit.py @@ -1,3 +1,4 @@ +from builtins import range from miasm2.jitter.jitload import Jitter, named_arguments from miasm2.core.locationdb import LocationDB from miasm2.arch.ppc.sem import ir_ppc32b @@ -34,7 +35,7 @@ class jitter_ppc32b(Jitter): @named_arguments def func_args_systemv(self, n_args): - args = [self.get_arg_n_systemv(i) for i in xrange(n_args)] + args = [self.get_arg_n_systemv(i) for i in range(n_args)] ret_ad = self.cpu.LR return ret_ad, args @@ -47,9 +48,9 @@ class jitter_ppc32b(Jitter): return True def func_prepare_systemv(self, ret_addr, *args): - for index in xrange(min(len(args), self.max_reg_arg)): + for index in range(min(len(args), self.max_reg_arg)): setattr(self.cpu, 'R%d' % (index + 3), args[index]) - for index in xrange(len(args) - 1, self.max_reg_arg - 1, -1): + for index in range(len(args) - 1, self.max_reg_arg - 1, -1): self.push_uint32_t(args[index]) # reserve room for LR save word and backchain diff --git a/miasm2/arch/ppc/regs.py b/miasm2/arch/ppc/regs.py index 70b49f82..e70afce2 100644 --- a/miasm2/arch/ppc/regs.py +++ b/miasm2/arch/ppc/regs.py @@ -1,4 +1,5 @@ +from builtins import range from miasm2.expression.expression import * from miasm2.core.cpu import gen_reg, gen_regs @@ -14,13 +15,13 @@ SPR_ACCESS_SPR_OFF = 0 SPR_ACCESS_GPR_MASK = 0x0001F000 SPR_ACCESS_GPR_OFF = 12 -gpregs_str = ["R%d" % i for i in xrange(32)] +gpregs_str = ["R%d" % i for i in range(32)] gpregs_expr, gpregs_init, gpregs = gen_regs(gpregs_str, globals(), 32) -crfregs_str = ["CR%d" % i for i in xrange(8)] +crfregs_str = ["CR%d" % i for i in range(8)] crfregs_expr, crfregs_init, crfregs = gen_regs(crfregs_str, globals(), 4) -crfbitregs_str = ["CR%d_%s" % (i, flag) for i in xrange(8) +crfbitregs_str = ["CR%d_%s" % (i, flag) for i in range(8) for flag in ['LT', 'GT', 'EQ', 'SO'] ] crfbitregs_expr, crfbitregs_init, crfbitregs = gen_regs(crfbitregs_str, globals(), 1) @@ -38,8 +39,8 @@ otherregs_str = ["PC", "CTR", "LR" ] otherregs_expr, otherregs_init, otherregs = gen_regs(otherregs_str, globals(), 32) -superregs_str = (["SPRG%d" % i for i in xrange(4)] + - ["SRR%d" % i for i in xrange(2)] + +superregs_str = (["SPRG%d" % i for i in range(4)] + + ["SRR%d" % i for i in range(2)] + ["DAR", "DSISR", "MSR", "PIR", "PVR", "DEC", "TBL", "TBU"]) superregs_expr, superregs_init, superregs = gen_regs(superregs_str, diff --git a/miasm2/arch/ppc/sem.py b/miasm2/arch/ppc/sem.py index 558450b2..ef44ffe3 100644 --- a/miasm2/arch/ppc/sem.py +++ b/miasm2/arch/ppc/sem.py @@ -1,3 +1,6 @@ +from __future__ import print_function +from builtins import range + import miasm2.expression.expression as expr from miasm2.ir.ir import AssignBlock, IntermediateRepresentation, IRBlock from miasm2.arch.ppc.arch import mn_ppc @@ -15,7 +18,7 @@ spr_dict = { crf_dict = dict((ExprId("CR%d" % i, 4), dict( (bit, ExprId("CR%d_%s" % (i, bit), 1)) for bit in ['LT', 'GT', 'EQ', 'SO' ] )) - for i in xrange(8) ) + for i in range(8) ) ctx = { 'crf_dict': crf_dict, @@ -112,7 +115,7 @@ def mn_do_cntlzw(ir, instr, ra, rs): def crbit_to_reg(bit): bit = bit.arg.arg - crid = bit / 4 + crid = bit // 4 bitname = [ 'LT', 'GT', 'EQ', 'SO' ][bit % 4] return all_regs_ids_byname["CR%d_%s" % (crid, bitname)] @@ -217,8 +220,8 @@ def mn_do_exts(ir, instr, ra, rs): return ret, [] def byte_swap(expr): - nbytes = expr.size / 8 - bytes = [ expr[i*8:i*8+8] for i in xrange(nbytes - 1, -1, -1) ] + nbytes = expr.size // 8 + bytes = [ expr[i*8:i*8+8] for i in range(nbytes - 1, -1, -1) ] return ExprCompose(bytes) def mn_do_load(ir, instr, arg1, arg2, arg3=None): @@ -325,7 +328,7 @@ def mn_do_mcrxr(ir, instr, crfd): def mn_do_mfcr(ir, instr, rd): return ([ ExprAssign(rd, ExprCompose(*[ all_regs_ids_byname["CR%d_%s" % (i, b)] - for i in xrange(7, -1, -1) + for i in range(7, -1, -1) for b in ['SO', 'EQ', 'GT', 'LT']]))], []) @@ -350,7 +353,7 @@ def mn_mfspr(ir, instr, arg1, arg2): def mn_mtcrf(ir, instr, crm, rs): ret = [] - for i in xrange(8): + for i in range(8): if crm.arg.arg & (1 << (7 - i)): j = (28 - 4 * i) + 3 for b in ['LT', 'GT', 'EQ', 'SO']: @@ -361,7 +364,7 @@ def mn_mtcrf(ir, instr, crm, rs): return ret, [] def mn_mtmsr(ir, instr, rs): - print "%08x: MSR assigned" % instr.offset + print("%08x: MSR assigned" % instr.offset) return [ ExprAssign(MSR, rs) ], [] def mn_mtspr(ir, instr, arg1, arg2): @@ -746,7 +749,7 @@ def mn_do_cond_branch(ir, instr, dest): return ret, [] def mn_do_nop_warn(ir, instr, *args): - print "Warning, instruction %s implemented as NOP" % instr + print("Warning, instruction %s implemented as NOP" % instr) return [], [] @sbuild.parse |