diff options
Diffstat (limited to '')
| -rw-r--r-- | miasm2/arch/x86/arch.py | 4 | ||||
| -rw-r--r-- | miasm2/arch/x86/disasm.py | 2 | ||||
| -rw-r--r-- | miasm2/arch/x86/ira.py | 30 | ||||
| -rw-r--r-- | miasm2/arch/x86/jit.py | 61 | ||||
| -rw-r--r-- | miasm2/arch/x86/sem.py | 56 |
5 files changed, 74 insertions, 79 deletions
diff --git a/miasm2/arch/x86/arch.py b/miasm2/arch/x86/arch.py index 8ae6cd31..d686cd55 100644 --- a/miasm2/arch/x86/arch.py +++ b/miasm2/arch/x86/arch.py @@ -7,7 +7,7 @@ from miasm2.core.cpu import * from collections import defaultdict import miasm2.arch.x86.regs as regs_module from miasm2.arch.x86.regs import * -from miasm2.core.asmbloc import asm_label +from miasm2.core.asmblock import AsmLabel log = logging.getLogger("x86_arch") console_handler = logging.StreamHandler() @@ -489,7 +489,7 @@ class instruction_x86(instruction): return expr = self.args[0] if isinstance(expr, ExprId): - if not isinstance(expr.name, asm_label) and expr not in all_regs_ids: + if not isinstance(expr.name, AsmLabel) and expr not in all_regs_ids: raise ValueError("ExprId must be a label or a register") elif isinstance(expr, ExprInt): ad = expr.arg + int(self.offset) diff --git a/miasm2/arch/x86/disasm.py b/miasm2/arch/x86/disasm.py index 0ff55097..fc981c09 100644 --- a/miasm2/arch/x86/disasm.py +++ b/miasm2/arch/x86/disasm.py @@ -1,4 +1,4 @@ -from miasm2.core.asmbloc import disasmEngine +from miasm2.core.asmblock import disasmEngine from miasm2.arch.x86.arch import mn_x86 diff --git a/miasm2/arch/x86/ira.py b/miasm2/arch/x86/ira.py index 31d38b37..74aa0203 100644 --- a/miasm2/arch/x86/ira.py +++ b/miasm2/arch/x86/ira.py @@ -1,9 +1,7 @@ #-*- coding:utf-8 -*- -from miasm2.expression.expression import ExprAff, ExprOp, ExprId -from miasm2.core.graph import DiGraph -from miasm2.core.asmbloc import expr_is_label -from miasm2.ir.ir import ir, irbloc, AssignBlock +from miasm2.expression.expression import ExprAff, ExprOp +from miasm2.ir.ir import AssignBlock from miasm2.ir.analysis import ira from miasm2.arch.x86.sem import ir_x86_16, ir_x86_32, ir_x86_64 @@ -15,21 +13,21 @@ class ir_a_x86_16(ir_x86_16, ira): self.ret_reg = self.arch.regs.AX # for test XXX TODO - def set_dead_regs(self, b): - b.rw[-1][1].add(self.arch.regs.zf) - b.rw[-1][1].add(self.arch.regs.of) - b.rw[-1][1].add(self.arch.regs.pf) - b.rw[-1][1].add(self.arch.regs.cf) - b.rw[-1][1].add(self.arch.regs.nf) - b.rw[-1][1].add(self.arch.regs.af) - - def get_out_regs(self, b): + def set_dead_regs(self, irblock): + irblock.rw[-1][1].add(self.arch.regs.zf) + irblock.rw[-1][1].add(self.arch.regs.of) + irblock.rw[-1][1].add(self.arch.regs.pf) + irblock.rw[-1][1].add(self.arch.regs.cf) + irblock.rw[-1][1].add(self.arch.regs.nf) + irblock.rw[-1][1].add(self.arch.regs.af) + + def get_out_regs(self, _): return set([self.ret_reg, self.sp]) def add_unused_regs(self): - leaves = [self.blocs[n] for n in self.g.leafs()] - for b in leaves: - self.set_dead_regs(b) + leaves = [self.blocks[label] for label in self.g.leafs()] + for irblock in leaves: + self.set_dead_regs(irblock) class ir_a_x86_32(ir_x86_32, ir_a_x86_16): diff --git a/miasm2/arch/x86/jit.py b/miasm2/arch/x86/jit.py index 2e483f2a..cfdabf8c 100644 --- a/miasm2/arch/x86/jit.py +++ b/miasm2/arch/x86/jit.py @@ -1,8 +1,8 @@ import logging from miasm2.jitter.jitload import jitter, named_arguments -from miasm2.core import asmbloc -from miasm2.core.utils import * +from miasm2.core import asmblock +from miasm2.core.utils import pck16, pck32, pck64, upck16, upck32, upck64 from miasm2.arch.x86.sem import ir_x86_16, ir_x86_32, ir_x86_64 from miasm2.jitter.codegen import CGen @@ -37,28 +37,27 @@ class jitter_x86_16(jitter): C_Gen = x86_32_CGen def __init__(self, *args, **kwargs): - sp = asmbloc.asm_symbol_pool() + sp = asmblock.AsmSymbolPool() jitter.__init__(self, ir_x86_16(sp), *args, **kwargs) self.vm.set_little_endian() self.ir_arch.do_stk_segm = False self.orig_irbloc_fix_regs_for_mode = self.ir_arch.irbloc_fix_regs_for_mode self.ir_arch.irbloc_fix_regs_for_mode = self.ir_archbloc_fix_regs_for_mode - def ir_archbloc_fix_regs_for_mode(self, irbloc, attrib=64): - self.orig_irbloc_fix_regs_for_mode(irbloc, 64) + def ir_archbloc_fix_regs_for_mode(self, irblock, attrib=64): + self.orig_irbloc_fix_regs_for_mode(irblock, 64) - def push_uint16_t(self, v): + def push_uint16_t(self, value): self.cpu.SP -= self.ir_arch.sp.size / 8 - self.vm.set_mem(self.cpu.SP, pck16(v)) + self.vm.set_mem(self.cpu.SP, pck16(value)) def pop_uint16_t(self): - x = upck16(self.vm.get_mem(self.cpu.SP, self.ir_arch.sp.size / 8)) + value = upck16(self.vm.get_mem(self.cpu.SP, self.ir_arch.sp.size / 8)) self.cpu.SP += self.ir_arch.sp.size / 8 - return x + return value - def get_stack_arg(self, n): - x = upck16(self.vm.get_mem(self.cpu.SP + 4 * n, 4)) - return x + def get_stack_arg(self, index): + return upck16(self.vm.get_mem(self.cpu.SP + 4 * index, 4)) def init_run(self, *args, **kwargs): jitter.init_run(self, *args, **kwargs) @@ -70,7 +69,7 @@ class jitter_x86_32(jitter): C_Gen = x86_32_CGen def __init__(self, *args, **kwargs): - sp = asmbloc.asm_symbol_pool() + sp = asmblock.AsmSymbolPool() jitter.__init__(self, ir_x86_32(sp), *args, **kwargs) self.vm.set_little_endian() self.ir_arch.do_stk_segm = False @@ -78,21 +77,20 @@ class jitter_x86_32(jitter): self.orig_irbloc_fix_regs_for_mode = self.ir_arch.irbloc_fix_regs_for_mode self.ir_arch.irbloc_fix_regs_for_mode = self.ir_archbloc_fix_regs_for_mode - def ir_archbloc_fix_regs_for_mode(self, irbloc, attrib=64): - self.orig_irbloc_fix_regs_for_mode(irbloc, 64) + def ir_archbloc_fix_regs_for_mode(self, irblock, attrib=64): + self.orig_irbloc_fix_regs_for_mode(irblock, 64) - def push_uint32_t(self, v): + def push_uint32_t(self, value): self.cpu.ESP -= self.ir_arch.sp.size / 8 - self.vm.set_mem(self.cpu.ESP, pck32(v)) + self.vm.set_mem(self.cpu.ESP, pck32(value)) def pop_uint32_t(self): - x = upck32(self.vm.get_mem(self.cpu.ESP, self.ir_arch.sp.size / 8)) + value = upck32(self.vm.get_mem(self.cpu.ESP, self.ir_arch.sp.size / 8)) self.cpu.ESP += self.ir_arch.sp.size / 8 - return x + return value - def get_stack_arg(self, n): - x = upck32(self.vm.get_mem(self.cpu.ESP + 4 * n, 4)) - return x + def get_stack_arg(self, index): + return upck32(self.vm.get_mem(self.cpu.ESP + 4 * index, 4)) # calling conventions @@ -131,7 +129,7 @@ class jitter_x86_64(jitter): C_Gen = x86_64_CGen def __init__(self, *args, **kwargs): - sp = asmbloc.asm_symbol_pool() + sp = asmblock.AsmSymbolPool() jitter.__init__(self, ir_x86_64(sp), *args, **kwargs) self.vm.set_little_endian() self.ir_arch.do_stk_segm = False @@ -139,21 +137,20 @@ class jitter_x86_64(jitter): self.orig_irbloc_fix_regs_for_mode = self.ir_arch.irbloc_fix_regs_for_mode self.ir_arch.irbloc_fix_regs_for_mode = self.ir_archbloc_fix_regs_for_mode - def ir_archbloc_fix_regs_for_mode(self, irbloc, attrib=64): - self.orig_irbloc_fix_regs_for_mode(irbloc, 64) + def ir_archbloc_fix_regs_for_mode(self, irblock, attrib=64): + self.orig_irbloc_fix_regs_for_mode(irblock, 64) - def push_uint64_t(self, v): + def push_uint64_t(self, value): self.cpu.RSP -= self.ir_arch.sp.size / 8 - self.vm.set_mem(self.cpu.RSP, pck64(v)) + self.vm.set_mem(self.cpu.RSP, pck64(value)) def pop_uint64_t(self): - x = upck64(self.vm.get_mem(self.cpu.RSP, self.ir_arch.sp.size / 8)) + value = upck64(self.vm.get_mem(self.cpu.RSP, self.ir_arch.sp.size / 8)) self.cpu.RSP += self.ir_arch.sp.size / 8 - return x + return value - def get_stack_arg(self, n): - x = upck64(self.vm.get_mem(self.cpu.RSP + 8 * n, 8)) - return x + def get_stack_arg(self, index): + return upck64(self.vm.get_mem(self.cpu.RSP + 8 * index, 8)) @named_arguments def func_args_stdcall(self, n_args): diff --git a/miasm2/arch/x86/sem.py b/miasm2/arch/x86/sem.py index 18a1421e..729806b5 100644 --- a/miasm2/arch/x86/sem.py +++ b/miasm2/arch/x86/sem.py @@ -21,7 +21,7 @@ from miasm2.expression.simplifications import expr_simp from miasm2.arch.x86.regs import * from miasm2.arch.x86.arch import mn_x86, repeat_mn, replace_regs from miasm2.expression.expression_helper import expr_cmps, expr_cmpu -from miasm2.ir.ir import ir, irbloc +from miasm2.ir.ir import IntermediateRepresentation, IRBlock from miasm2.core.sembuilder import SemBuilder import math import struct @@ -277,7 +277,7 @@ def gen_fcmov(ir, instr, cond, arg1, arg2, mov_if): e_do, extra_irs = [m2_expr.ExprAff(arg1, arg2)], [] e_do.append(m2_expr.ExprAff(ir.IRDst, lbl_skip)) e.append(m2_expr.ExprAff(ir.IRDst, m2_expr.ExprCond(cond, dstA, dstB))) - return e, [irbloc(lbl_do.name, [e_do])] + return e, [IRBlock(lbl_do.name, [e_do])] def gen_cmov(ir, instr, cond, dst, src, mov_if): @@ -297,7 +297,7 @@ def gen_cmov(ir, instr, cond, dst, src, mov_if): e_do, extra_irs = mov(ir, instr, dst, src) e_do.append(m2_expr.ExprAff(ir.IRDst, lbl_skip)) e.append(m2_expr.ExprAff(ir.IRDst, m2_expr.ExprCond(cond, dstA, dstB))) - return e, [irbloc(lbl_do.name, [e_do])] + return e, [IRBlock(lbl_do.name, [e_do])] def mov(_, instr, dst, src): @@ -518,7 +518,7 @@ def _rotate_tpl(ir, instr, dst, src, op, left=False, include_cf=False): e_do.append(m2_expr.ExprAff(ir.IRDst, lbl_skip)) e.append(m2_expr.ExprAff( ir.IRDst, m2_expr.ExprCond(shifter, lbl_do, lbl_skip))) - return (e, [irbloc(lbl_do.name, [e_do])]) + return (e, [IRBlock(lbl_do.name, [e_do])]) def l_rol(ir, instr, dst, src): @@ -615,7 +615,7 @@ def _shift_tpl(op, ir, instr, a, b, c=None, op_inv=None, left=False, e_do.append(m2_expr.ExprAff(ir.IRDst, lbl_skip)) e.append(m2_expr.ExprAff(ir.IRDst, m2_expr.ExprCond(shifter, lbl_do, lbl_skip))) - return e, [irbloc(lbl_do.name, [e_do])] + return e, [IRBlock(lbl_do.name, [e_do])] def sar(ir, instr, dst, src): @@ -963,7 +963,7 @@ def cmps(ir, instr, size): e0.append(m2_expr.ExprAff(b.arg, b.arg + m2_expr.ExprInt(size / 8, b.arg.size))) e0.append(m2_expr.ExprAff(ir.IRDst, lbl_next)) - e0 = irbloc(lbl_df_0.name, [e0]) + e0 = IRBlock(lbl_df_0.name, [e0]) e1 = [] e1.append(m2_expr.ExprAff(a.arg, @@ -971,7 +971,7 @@ def cmps(ir, instr, size): e1.append(m2_expr.ExprAff(b.arg, b.arg - m2_expr.ExprInt(size / 8, b.arg.size))) e1.append(m2_expr.ExprAff(ir.IRDst, lbl_next)) - e1 = irbloc(lbl_df_1.name, [e1]) + e1 = IRBlock(lbl_df_1.name, [e1]) e.append(m2_expr.ExprAff(ir.IRDst, m2_expr.ExprCond(df, lbl_df_1, lbl_df_0))) @@ -992,13 +992,13 @@ def scas(ir, instr, size): e0.append(m2_expr.ExprAff(a.arg, a.arg + m2_expr.ExprInt(size / 8, a.arg.size))) e0.append(m2_expr.ExprAff(ir.IRDst, lbl_next)) - e0 = irbloc(lbl_df_0.name, [e0]) + e0 = IRBlock(lbl_df_0.name, [e0]) e1 = [] e1.append(m2_expr.ExprAff(a.arg, a.arg - m2_expr.ExprInt(size / 8, a.arg.size))) e1.append(m2_expr.ExprAff(ir.IRDst, lbl_next)) - e1 = irbloc(lbl_df_1.name, [e1]) + e1 = IRBlock(lbl_df_1.name, [e1]) e.append(m2_expr.ExprAff(ir.IRDst, m2_expr.ExprCond(df, lbl_df_1, lbl_df_0))) @@ -1641,12 +1641,12 @@ def stos(ir, instr, size): e0 = [] e0.append(m2_expr.ExprAff(addr_o, addr_p)) e0.append(m2_expr.ExprAff(ir.IRDst, lbl_next)) - e0 = irbloc(lbl_df_0.name, [e0]) + e0 = IRBlock(lbl_df_0.name, [e0]) e1 = [] e1.append(m2_expr.ExprAff(addr_o, addr_m)) e1.append(m2_expr.ExprAff(ir.IRDst, lbl_next)) - e1 = irbloc(lbl_df_1.name, [e1]) + e1 = IRBlock(lbl_df_1.name, [e1]) e = [] e.append(m2_expr.ExprAff(ir.ExprMem(addr, size), b)) @@ -1676,12 +1676,12 @@ def lods(ir, instr, size): e0 = [] e0.append(m2_expr.ExprAff(addr_o, addr_p)) e0.append(m2_expr.ExprAff(ir.IRDst, lbl_next)) - e0 = irbloc(lbl_df_0.name, [e0]) + e0 = IRBlock(lbl_df_0.name, [e0]) e1 = [] e1.append(m2_expr.ExprAff(addr_o, addr_m)) e1.append(m2_expr.ExprAff(ir.IRDst, lbl_next)) - e1 = irbloc(lbl_df_1.name, [e1]) + e1 = IRBlock(lbl_df_1.name, [e1]) e = [] if instr.mode == 64 and b.size == 32: @@ -1718,13 +1718,13 @@ def movs(ir, instr, size): e0.append(m2_expr.ExprAff(a, a + m2_expr.ExprInt(size / 8, a.size))) e0.append(m2_expr.ExprAff(b, b + m2_expr.ExprInt(size / 8, b.size))) e0.append(m2_expr.ExprAff(ir.IRDst, lbl_next)) - e0 = irbloc(lbl_df_0.name, [e0]) + e0 = IRBlock(lbl_df_0.name, [e0]) e1 = [] e1.append(m2_expr.ExprAff(a, a - m2_expr.ExprInt(size / 8, a.size))) e1.append(m2_expr.ExprAff(b, b - m2_expr.ExprInt(size / 8, b.size))) e1.append(m2_expr.ExprAff(ir.IRDst, lbl_next)) - e1 = irbloc(lbl_df_1.name, [e1]) + e1 = IRBlock(lbl_df_1.name, [e1]) e.append(m2_expr.ExprAff(ir.IRDst, m2_expr.ExprCond(df, lbl_df_1, lbl_df_0))) @@ -2758,8 +2758,8 @@ def bsr_bsf(ir, instr, dst, src, op_name): e_src_not_null.append(m2_expr.ExprAff(dst, m2_expr.ExprOp(op_name, src))) e_src_not_null.append(aff_dst) - return e, [irbloc(lbl_src_null.name, [e_src_null]), - irbloc(lbl_src_not_null.name, [e_src_not_null])] + return e, [IRBlock(lbl_src_null.name, [e_src_null]), + IRBlock(lbl_src_not_null.name, [e_src_not_null])] def bsf(ir, instr, dst, src): @@ -3655,7 +3655,7 @@ def ps_rl_ll(ir, instr, dst, src, op, size): e_do = [] e.append(m2_expr.ExprAff(dst[0:dst.size], m2_expr.ExprCompose(*slices))) e_do.append(m2_expr.ExprAff(ir.IRDst, lbl_next)) - return e, [irbloc(lbl_do.name, [e_do]), irbloc(lbl_zero.name, [e_zero])] + return e, [IRBlock(lbl_do.name, [e_do]), IRBlock(lbl_zero.name, [e_zero])] def psrlw(ir, instr, dst, src): @@ -4484,10 +4484,10 @@ mnemo_func = {'mov': mov, } -class ir_x86_16(ir): +class ir_x86_16(IntermediateRepresentation): def __init__(self, symbol_pool=None): - ir.__init__(self, mn_x86, 16, symbol_pool) + IntermediateRepresentation.__init__(self, mn_x86, 16, symbol_pool) self.do_stk_segm = False self.do_ds_segm = False self.do_str_segm = False @@ -4571,8 +4571,8 @@ class ir_x86_16(ir): lbl_skip = m2_expr.ExprId(self.get_next_label(instr), self.IRDst.size) lbl_next = m2_expr.ExprId(self.get_next_label(instr), self.IRDst.size) - for b in extra_ir: - for ir in b.irs: + for irblock in extra_ir: + for ir in irblock.irs: for i, e in enumerate(ir): src = e.src.replace_expr({lbl_next: lbl_end}) ir[i] = m2_expr.ExprAff(e.dst, src) @@ -4583,10 +4583,10 @@ class ir_x86_16(ir): cond_bloc.append(m2_expr.ExprAff(self.IRDst, m2_expr.ExprCond(c_cond, lbl_skip, lbl_do))) - cond_bloc = irbloc(lbl_end.name, [cond_bloc]) + cond_bloc = IRBlock(lbl_end.name, [cond_bloc]) e_do = instr_ir - c = irbloc(lbl_do.name, [e_do]) + c = IRBlock(lbl_do.name, [e_do]) c.except_automod = False e_n = [m2_expr.ExprAff(self.IRDst, m2_expr.ExprCond(c_reg, lbl_do, lbl_skip))] @@ -4622,7 +4622,7 @@ class ir_x86_16(ir): class ir_x86_32(ir_x86_16): def __init__(self, symbol_pool=None): - ir.__init__(self, mn_x86, 32, symbol_pool) + IntermediateRepresentation.__init__(self, mn_x86, 32, symbol_pool) self.do_stk_segm = False self.do_ds_segm = False self.do_str_segm = False @@ -4636,7 +4636,7 @@ class ir_x86_32(ir_x86_16): class ir_x86_64(ir_x86_16): def __init__(self, symbol_pool=None): - ir.__init__(self, mn_x86, 64, symbol_pool) + IntermediateRepresentation.__init__(self, mn_x86, 64, symbol_pool) self.do_stk_segm = False self.do_ds_segm = False self.do_str_segm = False @@ -4656,8 +4656,8 @@ class ir_x86_64(ir_x86_16): src = src.replace_expr( {self.pc: m2_expr.ExprInt64(instr.offset + instr.l)}) instr_ir[i] = m2_expr.ExprAff(dst, src) - for b in extra_ir: - for irs in b.irs: + for irblock in extra_ir: + for irs in irblock.irs: for i, expr in enumerate(irs): dst, src = expr.dst, expr.src if dst != self.pc: |