diff options
Diffstat (limited to 'miasm2/arch/x86')
| -rw-r--r-- | miasm2/arch/x86/arch.py | 21 | ||||
| -rw-r--r-- | miasm2/arch/x86/jit.py | 32 | ||||
| -rw-r--r-- | miasm2/arch/x86/sem.py | 20 |
3 files changed, 57 insertions, 16 deletions
diff --git a/miasm2/arch/x86/arch.py b/miasm2/arch/x86/arch.py index 280090aa..ff7dc1ee 100644 --- a/miasm2/arch/x86/arch.py +++ b/miasm2/arch/x86/arch.py @@ -826,6 +826,13 @@ class mn_x86(cls_mn): self.rex_b.value = pre_dis_info['rex_b'] self.rex_x.value = pre_dis_info['rex_x'] self.rex_p.value = pre_dis_info['rex_p'] + + if hasattr(self, 'no_rex') and\ + (self.rex_r.value or self.rex_b.value or + self.rex_x.value or self.rex_p.value): + return False + + self.g1.value = pre_dis_info['g1'] self.g2.value = pre_dis_info['g2'] self.prefix = pre_dis_info['prefix'] @@ -853,6 +860,10 @@ class mn_x86(cls_mn): rex |= 0x1 if rex != 0x40 or self.rex_p.value == 1: v = chr(rex) + v + if hasattr(self, 'no_rex'): + return None + + if hasattr(self, 'prefixed'): v = self.prefixed.default + v @@ -3084,6 +3095,8 @@ pref_f3 = bs(l=0, fname="prefixed", default="\xf3") pref_66 = bs(l=0, fname="prefixed", default="\x66") no_xmm_pref = bs(l=0, fname="no_xmm_pref") +no_rex = bs(l=0, fname="no_rex") + sib_scale = bs(l=2, cls=(bs_cond_scale,), fname = "sib_scale") sib_index = bs(l=3, cls=(bs_cond_index,), fname = "sib_index") sib_base = bs(l=3, cls=(bs_cond_index,), fname = "sib_base") @@ -3723,6 +3736,7 @@ addop("outsw", [bs8(0x6f), bs_opmode16]) addop("outsd", [bs8(0x6f), bs_opmode32]) addop("outsd", [bs8(0x6f), bs_opmode64]) +addop("setalc", [bs8(0xD6)]) # addop("pause", [bs8(0xf3), bs8(0x90)]) @@ -3898,7 +3912,7 @@ addop("wrmsr", [bs8(0x0f), bs8(0x30)]) addop("xadd", [bs8(0x0f), bs("1100000"), w8] + rmmod(rmreg, rm_arg_w8), [rm_arg_w8, rmreg]) -addop("nop", [bs8(0x90)], alias=True) +addop("nop", [bs8(0x90), no_rex], alias=True) addop("xchg", [bs('10010'), d_eax, reg]) addop("xchg", [bs('1000011'), w8] + @@ -4301,10 +4315,7 @@ addop("pextrq", [bs8(0x0f), bs8(0x3a), bs8(0x16), pref_66] + addop("pextrw", [bs8(0x0f), bs8(0x3a), bs8(0x15), pref_66] + - rmmod(xmm_reg, rm_arg_m16) + [u08], [rm_arg_m16, xmm_reg, u08]) -#addop("pextrw", [bs8(0x0f), bs8(0x3a), bs8(0x15), no_xmm_pref] + -# rmmod(mm_reg, rm_arg_m16) + [u08], [rm_arg_m16, mm_reg, u08]) - + rmmod(xmm_reg, rm_arg_reg_m16) + [u08], [rm_arg_reg_m16, xmm_reg, u08]) addop("pextrw", [bs8(0x0f), bs8(0xc5), no_xmm_pref] + rmmod(mm_reg, rm_arg_reg_m16) + [u08], [rm_arg_reg_m16, mm_reg, u08]) addop("pextrw", [bs8(0x0f), bs8(0xc5), pref_66] + diff --git a/miasm2/arch/x86/jit.py b/miasm2/arch/x86/jit.py index 5a9886c5..2e483f2a 100644 --- a/miasm2/arch/x86/jit.py +++ b/miasm2/arch/x86/jit.py @@ -4,6 +4,7 @@ from miasm2.jitter.jitload import jitter, named_arguments from miasm2.core import asmbloc from miasm2.core.utils import * from miasm2.arch.x86.sem import ir_x86_16, ir_x86_32, ir_x86_64 +from miasm2.jitter.codegen import CGen log = logging.getLogger('jit_x86') hnd = logging.StreamHandler() @@ -11,13 +12,34 @@ hnd.setFormatter(logging.Formatter("[%(levelname)s]: %(message)s")) log.addHandler(hnd) log.setLevel(logging.CRITICAL) + +class x86_32_CGen(CGen): + def __init__(self, ir_arch): + self.ir_arch = ir_arch + self.PC = self.ir_arch.arch.regs.RIP + self.init_arch_C() + + def gen_post_code(self, attrib): + out = [] + if attrib.log_regs: + out.append('dump_gpregs_32(jitcpu->cpu);') + return out + +class x86_64_CGen(x86_32_CGen): + def gen_post_code(self, attrib): + out = [] + if attrib.log_regs: + out.append('dump_gpregs_64(jitcpu->cpu);') + return out + class jitter_x86_16(jitter): + C_Gen = x86_32_CGen + def __init__(self, *args, **kwargs): sp = asmbloc.asm_symbol_pool() jitter.__init__(self, ir_x86_16(sp), *args, **kwargs) self.vm.set_little_endian() - self.ir_arch.jit_pc = self.ir_arch.arch.regs.RIP self.ir_arch.do_stk_segm = False self.orig_irbloc_fix_regs_for_mode = self.ir_arch.irbloc_fix_regs_for_mode self.ir_arch.irbloc_fix_regs_for_mode = self.ir_archbloc_fix_regs_for_mode @@ -45,11 +67,12 @@ class jitter_x86_16(jitter): class jitter_x86_32(jitter): + C_Gen = x86_32_CGen + def __init__(self, *args, **kwargs): sp = asmbloc.asm_symbol_pool() jitter.__init__(self, ir_x86_32(sp), *args, **kwargs) self.vm.set_little_endian() - self.ir_arch.jit_pc = self.ir_arch.arch.regs.RIP self.ir_arch.do_stk_segm = False self.orig_irbloc_fix_regs_for_mode = self.ir_arch.irbloc_fix_regs_for_mode @@ -81,7 +104,7 @@ class jitter_x86_32(jitter): return ret_ad, args def func_ret_stdcall(self, ret_addr, ret_value1=None, ret_value2=None): - self.cpu.EIP = ret_addr + self.pc = self.cpu.EIP = ret_addr if ret_value1 is not None: self.cpu.EAX = ret_value1 if ret_value2 is not None: @@ -105,11 +128,12 @@ class jitter_x86_32(jitter): class jitter_x86_64(jitter): + C_Gen = x86_64_CGen + def __init__(self, *args, **kwargs): sp = asmbloc.asm_symbol_pool() jitter.__init__(self, ir_x86_64(sp), *args, **kwargs) self.vm.set_little_endian() - self.ir_arch.jit_pc = self.ir_arch.arch.regs.RIP self.ir_arch.do_stk_segm = False self.orig_irbloc_fix_regs_for_mode = self.ir_arch.irbloc_fix_regs_for_mode diff --git a/miasm2/arch/x86/sem.py b/miasm2/arch/x86/sem.py index 28e42353..cdc98fba 100644 --- a/miasm2/arch/x86/sem.py +++ b/miasm2/arch/x86/sem.py @@ -3606,19 +3606,25 @@ def ps_rl_ll(ir, instr, a, b, op, size): mask = {16: 0xF, 32: 0x1F, 64: 0x3F}[size] - test = count & m2_expr.ExprInt(((1 << a.size) - 1) ^ mask, a.size) + test = expr_simp(count & m2_expr.ExprInt(((1 << a.size) - 1) ^ mask, a.size)) e = [m2_expr.ExprAff(ir.IRDst, m2_expr.ExprCond(test, lbl_zero, lbl_do))] - e_zero = [m2_expr.ExprAff(a, m2_expr.ExprInt(0, a.size)), - m2_expr.ExprAff(ir.IRDst, lbl_next)] - - e_do = [] slices = [] for i in xrange(0, a.size, size): slices.append((m2_expr.ExprOp(op, a[i:i + size], count[:size]), i, i + size)) + + if isinstance(test, m2_expr.ExprInt): + if int(test.arg) == 0: + return [m2_expr.ExprAff(a[0:a.size], m2_expr.ExprCompose(slices))], [] + else: + return [m2_expr.ExprAff(a, m2_expr.ExprInt(0, a.size))], [] + + e_zero = [m2_expr.ExprAff(a, m2_expr.ExprInt(0, a.size)), + m2_expr.ExprAff(ir.IRDst, lbl_next)] + e_do = [] e.append(m2_expr.ExprAff(a[0:a.size], m2_expr.ExprCompose(slices))) e_do.append(m2_expr.ExprAff(ir.IRDst, lbl_next)) return e, [irbloc(lbl_do.name, [e_do]), irbloc(lbl_zero.name, [e_zero])] @@ -4484,7 +4490,6 @@ class ir_x86_16(ir): instr_ir, extra_ir = mnemo_func[ instr.name.lower()](self, instr, *args) - self.mod_pc(instr, instr_ir, extra_ir) self.mod_pc(instr, instr_ir, extra_ir) instr.additional_info.except_on_instr = False @@ -4566,7 +4571,8 @@ class ir_x86_16(ir): dst = self.expr_fix_regs_for_mode(dst, mode) src = self.expr_fix_regs_for_mode(src, mode) assignblk[dst] = src - irbloc.dst = self.expr_fix_regs_for_mode(irbloc.dst, mode) + if irbloc.dst is not None: + irbloc.dst = self.expr_fix_regs_for_mode(irbloc.dst, mode) class ir_x86_32(ir_x86_16): |