3 files changed, 19 insertions, 13 deletions
diff --git a/miasm2/arch/x86/jit.py b/miasm2/arch/x86/jit.py
index d39f1f38..50501060 100644
--- a/miasm2/arch/x86/jit.py
+++ b/miasm2/arch/x86/jit.py
@@ -135,10 +135,12 @@ class jitter_x86_32(jitter):
         args = [self.get_stack_arg(i) for i in xrange(n_args)]
         return ret_ad, args
 
-    def func_ret_cdecl(self, ret_addr, ret_value=None):
+    def func_ret_cdecl(self, ret_addr, ret_value1=None, ret_value2=None):
         self.pc = self.cpu.EIP = ret_addr
-        if ret_value is not None:
-            self.cpu.EAX = ret_value
+        if ret_value1 is not None:
+            self.cpu.EAX = ret_value1
+        if ret_value2 is not None:
+            self.cpu.EDX = ret_value2
 
     get_arg_n_cdecl = get_stack_arg
 
diff --git a/miasm2/arch/x86/regs.py b/miasm2/arch/x86/regs.py
index 7354457f..5db75e37 100644
--- a/miasm2/arch/x86/regs.py
+++ b/miasm2/arch/x86/regs.py
@@ -425,8 +425,8 @@ all_regs_ids_no_alias = [
 ] + fltregs32_expr
 
 attrib_to_regs = {
-    16: regs16_expr + all_regs_ids_no_alias[all_regs_ids_no_alias.index(zf):],
-    32: regs32_expr + all_regs_ids_no_alias[all_regs_ids_no_alias.index(zf):],
+    16: regs16_expr + all_regs_ids_no_alias[all_regs_ids_no_alias.index(zf):] + [IP],
+    32: regs32_expr + all_regs_ids_no_alias[all_regs_ids_no_alias.index(zf):] + [EIP],
     64: all_regs_ids_no_alias,
 }
 
diff --git a/miasm2/arch/x86/sem.py b/miasm2/arch/x86/sem.py
index b3dfb3ef..12f2ef2a 100644
--- a/miasm2/arch/x86/sem.py
+++ b/miasm2/arch/x86/sem.py
@@ -1775,14 +1775,18 @@ def movs(ir, instr, size):
 
 
 def movsd(_, instr, dst, src):
-    e = []
-    if isinstance(dst, m2_expr.ExprId) and isinstance(src, m2_expr.ExprMem):
-        src = m2_expr.ExprMem(src.arg, dst.size)
-    elif isinstance(dst, m2_expr.ExprMem) and isinstance(src, m2_expr.ExprId):
-        dst = m2_expr.ExprMem(dst.arg, src.size)
-
-    e.append(m2_expr.ExprAff(dst, src))
-    return e, []
+    # 64 bits access
+    if dst.is_id() and src.is_id():
+        src = src[:64]
+        dst = dst[:64]
+    elif dst.is_mem() and src.is_id():
+        dst = m2_expr.ExprMem(dst.arg, 64)
+        src = src[:64]
+    else:
+        src = m2_expr.ExprMem(src.arg, 64)
+        # Erase dst high bits
+        src = src.zeroExtend(dst.size)
+    return [m2_expr.ExprAff(dst, src)], []
 
 
 def movsd_dispatch(ir, instr, dst=None, src=None):