diff options
Diffstat (limited to '')
| -rw-r--r-- | miasm2/arch/mips32/ira.py | 5 | ||||
| -rw-r--r-- | miasm2/arch/mips32/regs.py | 6 | ||||
| -rw-r--r-- | miasm2/arch/mips32/sem.py | 36 |
3 files changed, 41 insertions, 6 deletions
diff --git a/miasm2/arch/mips32/ira.py b/miasm2/arch/mips32/ira.py index bf0ed413..82af9acc 100644 --- a/miasm2/arch/mips32/ira.py +++ b/miasm2/arch/mips32/ira.py @@ -19,10 +19,7 @@ class ir_a_mips32(ir_mips32, ira): # for test XXX TODO def set_dead_regs(self, b): - b.rw[-1][1].add(self.arch.regs.zf) - b.rw[-1][1].add(self.arch.regs.nf) - b.rw[-1][1].add(self.arch.regs.of) - b.rw[-1][1].add(self.arch.regs.cf) + pass def call_effects(self, ad): irs = [[ExprAff(self.ret_reg, ExprOp('call_func_ret', ad, self.sp)), diff --git a/miasm2/arch/mips32/regs.py b/miasm2/arch/mips32/regs.py index 4999ea51..ef5e380c 100644 --- a/miasm2/arch/mips32/regs.py +++ b/miasm2/arch/mips32/regs.py @@ -5,11 +5,13 @@ from miasm2.expression.expression import * from miasm2.core.cpu import gen_reg, gen_regs gen_reg('PC', globals()) +gen_reg('PC_FETCH', globals()) gen_reg('R_LO', globals()) gen_reg('R_HI', globals()) PC_init = ExprId("PC_init") +PC_FETCH_init = ExprId("PC_FETCH_init") regs32_str = ["ZERO", 'AT', 'V0', 'V1'] +\ ['A%d'%i for i in xrange(4)] +\ @@ -50,9 +52,9 @@ regs_flt_expr, regs_flt_init, fltregs = gen_regs(regs_flt_str, globals(), sz=64) regs_fcc_expr, regs_fcc_init, fccregs = gen_regs(regs_fcc_str, globals()) -all_regs_ids = [PC, R_LO, R_HI] + gpregs_expr + regs_flt_expr + regs_fcc_expr +all_regs_ids = [PC, PC_FETCH, R_LO, R_HI] + gpregs_expr + regs_flt_expr + regs_fcc_expr all_regs_ids_byname = dict([(x.name, x) for x in all_regs_ids]) -all_regs_ids_init = [PC_init, R_LO_init, R_HI_init] + gpregs_init + regs_flt_init + regs_fcc_init +all_regs_ids_init = [PC_init, PC_FETCH_init, R_LO_init, R_HI_init] + gpregs_init + regs_flt_init + regs_fcc_init all_regs_ids_no_alias = all_regs_ids[:] regs_init = {} diff --git a/miasm2/arch/mips32/sem.py b/miasm2/arch/mips32/sem.py index 41f38b3d..10986a99 100644 --- a/miasm2/arch/mips32/sem.py +++ b/miasm2/arch/mips32/sem.py @@ -490,3 +490,39 @@ class ir_mips32(ir): def get_next_break_label(self, instr): l = self.symbol_pool.getby_offset_create(instr.offset + 8) return l + + def add_bloc(self, bloc, gen_pc_updt = False): + c = None + ir_blocs_all = [] + for l in bloc.lines: + if c is None: + # print 'new c' + label = self.get_label(l) + c = irbloc(label) + ir_blocs_all.append(c) + bloc_dst = None + # print 'Translate', l + dst, ir_bloc_cur, ir_blocs_extra = self.instr2ir(l) + # print ir_bloc_cur + # for xxx in ir_bloc_cur: + # print "\t", xxx + assert((dst is None) or (bloc_dst is None)) + bloc_dst = dst + #if bloc_dst is not None: + # c.dst = bloc_dst + if dst is not None: + ir_bloc_cur.append(ExprAff(PC_FETCH, dst)) + c.dst = PC_FETCH + if gen_pc_updt is not False: + self.gen_pc_update(c, l) + + c.irs.append(ir_bloc_cur) + c.lines.append(l) + if ir_blocs_extra: + # print 'split' + for b in ir_blocs_extra: + b.lines = [l] * len(b.irs) + ir_blocs_all += ir_blocs_extra + c = None + self.post_add_bloc(bloc, ir_blocs_all) + return ir_blocs_all |