diff options
Diffstat (limited to '')
| -rw-r--r-- | miasm2/arch/aarch64/sem.py | 1 | ||||
| -rw-r--r-- | miasm2/arch/arm/sem.py | 4 | ||||
| -rw-r--r-- | miasm2/arch/mips32/sem.py | 1 | ||||
| -rw-r--r-- | miasm2/arch/msp430/sem.py | 1 |
4 files changed, 7 insertions, 0 deletions
diff --git a/miasm2/arch/aarch64/sem.py b/miasm2/arch/aarch64/sem.py index 697fa981..2799df7a 100644 --- a/miasm2/arch/aarch64/sem.py +++ b/miasm2/arch/aarch64/sem.py @@ -813,6 +813,7 @@ class ir_aarch64l(IntermediateRepresentation): self.pc = PC self.sp = SP self.IRDst = m2_expr.ExprId('IRDst', 64) + self.addrsize = 64 def get_ir(self, instr): args = instr.args diff --git a/miasm2/arch/arm/sem.py b/miasm2/arch/arm/sem.py index c2afeef5..395eb1cb 100644 --- a/miasm2/arch/arm/sem.py +++ b/miasm2/arch/arm/sem.py @@ -1233,6 +1233,7 @@ class ir_arml(IntermediateRepresentation): self.pc = PC self.sp = SP self.IRDst = ExprId('IRDst', 32) + self.addrsize = 32 def get_ir(self, instr): args = instr.args @@ -1263,6 +1264,7 @@ class ir_armb(ir_arml): self.pc = PC self.sp = SP self.IRDst = ExprId('IRDst', 32) + self.addrsize = 32 class ir_armtl(IntermediateRepresentation): def __init__(self, symbol_pool=None): @@ -1270,6 +1272,7 @@ class ir_armtl(IntermediateRepresentation): self.pc = PC self.sp = SP self.IRDst = ExprId('IRDst', 32) + self.addrsize = 32 def get_ir(self, instr): return get_mnemo_expr(self, instr, *instr.args) @@ -1280,4 +1283,5 @@ class ir_armtb(ir_armtl): self.pc = PC self.sp = SP self.IRDst = ExprId('IRDst', 32) + self.addrsize = 32 diff --git a/miasm2/arch/mips32/sem.py b/miasm2/arch/mips32/sem.py index 855cb6c8..789491f6 100644 --- a/miasm2/arch/mips32/sem.py +++ b/miasm2/arch/mips32/sem.py @@ -436,6 +436,7 @@ class ir_mips32l(IntermediateRepresentation): self.pc = mn_mips32.getpc() self.sp = mn_mips32.getsp() self.IRDst = m2_expr.ExprId('IRDst', 32) + self.addrsize = 32 def get_ir(self, instr): args = instr.args diff --git a/miasm2/arch/msp430/sem.py b/miasm2/arch/msp430/sem.py index 5fd96ae2..dd24abb1 100644 --- a/miasm2/arch/msp430/sem.py +++ b/miasm2/arch/msp430/sem.py @@ -419,6 +419,7 @@ class ir_msp430(IntermediateRepresentation): self.pc = PC self.sp = SP self.IRDst = ExprId('IRDst', 16) + self.addrsize = 16 def mod_pc(self, instr, instr_ir, extra_ir): pass |