diff options
Diffstat (limited to '')
| -rw-r--r-- | miasm2/arch/aarch64/arch.py | 6 | ||||
| -rw-r--r-- | miasm2/arch/arm/arch.py | 4 | ||||
| -rw-r--r-- | miasm2/arch/arm/sem.py | 4 | ||||
| -rw-r--r-- | miasm2/arch/mep/arch.py | 6 | ||||
| -rw-r--r-- | miasm2/arch/mep/sem.py | 8 | ||||
| -rw-r--r-- | miasm2/arch/msp430/arch.py | 2 | ||||
| -rw-r--r-- | miasm2/arch/msp430/ctype.py | 2 | ||||
| -rw-r--r-- | miasm2/arch/sh4/arch.py | 2 | ||||
| -rw-r--r-- | miasm2/arch/x86/arch.py | 4 | ||||
| -rw-r--r-- | miasm2/arch/x86/ctype.py | 4 | ||||
| -rw-r--r-- | miasm2/arch/x86/sem.py | 34 |
11 files changed, 38 insertions, 38 deletions
diff --git a/miasm2/arch/aarch64/arch.py b/miasm2/arch/aarch64/arch.py index 598aca83..38cffc47 100644 --- a/miasm2/arch/aarch64/arch.py +++ b/miasm2/arch/aarch64/arch.py @@ -444,7 +444,7 @@ class mn_aarch64(cls_mn): return 0 o = 0 if n > bs.getlen() * 8: - raise ValueError('not enought bits %r %r' % (n, len(bs.bin) * 8)) + raise ValueError('not enough bits %r %r' % (n, len(bs.bin) * 8)) while n: offset = start / 8 n_offset = cls.endian_offset(attrib, offset) @@ -1068,7 +1068,7 @@ class bits(object): __slots__ = ["size", "value"] def __init__(self, size, value): - """Instanciate a bitvector of size @size with value @value""" + """Instantiate a bitvector of size @size with value @value""" self.size = size if value & self.mask != value: raise ValueError("Value %s is too large for %d bits", @@ -2065,7 +2065,7 @@ aarch64op("fmsub", [bs('0'), bs('00'), bs('11111'), bs('0'), sdsize1, bs('0'), s aarch64op("fnmadd",[bs('0'), bs('00'), bs('11111'), bs('0'), sdsize1, bs('1'), sdm_32_64, bs('0'), sda_32_64, sdn_32_64, sdd_32_64], [sdd_32_64, sdn_32_64, sdm_32_64, sda_32_64]) aarch64op("fnmsub",[bs('0'), bs('00'), bs('11111'), bs('0'), sdsize1, bs('1'), sdm_32_64, bs('1'), sda_32_64, sdn_32_64, sdd_32_64], [sdd_32_64, sdn_32_64, sdm_32_64, sda_32_64]) -# convertion float integer p.235 +# conversion float integer p.235 aarch64op("scvtf", [sf, bs('0'), bs('0'), bs('11110'), bs('0'), sdsize1, bs('1'), bs('00'), bs('010'), bs('000000'), rn, sdd_32_64], [sdd_32_64, rn]) aarch64op("ucvtf", [sf, bs('0'), bs('0'), bs('11110'), bs('0'), sdsize1, bs('1'), bs('00'), bs('011'), bs('000000'), rn, sdd_32_64], [sdd_32_64, rn]) diff --git a/miasm2/arch/arm/arch.py b/miasm2/arch/arm/arch.py index 5fbaa946..d4b7d05a 100644 --- a/miasm2/arch/arm/arch.py +++ b/miasm2/arch/arm/arch.py @@ -608,7 +608,7 @@ class mn_arm(cls_mn): return 0 o = 0 if n > bs.getlen() * 8: - raise ValueError('not enought bits %r %r' % (n, len(bs.bin) * 8)) + raise ValueError('not enough bits %r %r' % (n, len(bs.bin) * 8)) while n: offset = start / 8 n_offset = cls.endian_offset(attrib, offset) @@ -709,7 +709,7 @@ class mn_armt(cls_mn): return 0 o = 0 if n > bs.getlen() * 8: - raise ValueError('not enought bits %r %r' % (n, len(bs.bin) * 8)) + raise ValueError('not enough bits %r %r' % (n, len(bs.bin) * 8)) while n: offset = start / 8 n_offset = cls.endian_offset(attrib, offset) diff --git a/miasm2/arch/arm/sem.py b/miasm2/arch/arm/sem.py index ac1d9ce9..4af177d2 100644 --- a/miasm2/arch/arm/sem.py +++ b/miasm2/arch/arm/sem.py @@ -778,7 +778,7 @@ def st_ld_r(ir, instr, a, a2, b, store=False, size=32, s_ext=False, z_ext=False) else: ad = base + off - # PC base lookup uses PC 4 byte alignemnt + # PC base lookup uses PC 4 byte alignment ad = ad.replace_expr({PC: PC & ExprInt(0xFFFFFFFC, 32)}) dmem = False @@ -1700,7 +1700,7 @@ class ir_arml(IntermediateRepresentation): cond_eq = tab_cond[cond_num] if not index + len(it_hints) <= len(block.lines): - raise NotImplementedError("Splitted IT block non supported yet") + raise NotImplementedError("Split IT block non supported yet") ir_blocks_all = [] diff --git a/miasm2/arch/mep/arch.py b/miasm2/arch/mep/arch.py index 3cfa55a6..e4d66a63 100644 --- a/miasm2/arch/mep/arch.py +++ b/miasm2/arch/mep/arch.py @@ -313,7 +313,7 @@ class mn_mep(cls_mn): all_mn_inst = defaultdict(list) # mnemonics objects # Note: # - the key is the mnemonic Python class - # - the data is an instanciated object + # - the data is an instantiated object bintree = dict() # Variable storing internal values used to guess a # mnemonic during disassembly @@ -321,7 +321,7 @@ class mn_mep(cls_mn): # Defines the instruction set that will be used instruction = instruction_mep - # Python module that stores registers informations + # Python module that stores registers information regs = mep_regs_module # Default delay slot @@ -826,7 +826,7 @@ class mep_copro_reg_split(mep_copro_reg): class mep_deref_inc_reg(mep_deref_reg): - """Generic Toshiba MeP-c4 coprocess dereferenced & incremented registe + """Generic Toshiba MeP-c4 coprocess dereferenced & incremented register """ parser = deref_inc_reg_parser diff --git a/miasm2/arch/mep/sem.py b/miasm2/arch/mep/sem.py index 9e0cba6b..fb67becd 100644 --- a/miasm2/arch/mep/sem.py +++ b/miasm2/arch/mep/sem.py @@ -265,18 +265,18 @@ def advck3(r0, rn, rm): @sbuild.parse def sub(reg1, reg2): - """SUB - Substract one register to another.""" + """SUB - Subtract one register to another.""" # Rn <- Rn - Rm reg1 = reg1 - reg2 def sbvck3(ir, instr, r0, rn, rm): - """SBVCK3 - Check substraction overflow""" + """SBVCK3 - Check subtraction overflow""" # if(Overflow(Rn-Rm)) R0<-1 else R0<-0 (Signed) - # Substract registers + # Subtract registers reg_sub = ExprOp("+", rn, rm) # Get the register storing the highest value @@ -1160,7 +1160,7 @@ class ir_mepb(IntermediateRepresentation): return instr_ir, extra_ir def get_next_break_loc_key(self, instr): - """Returns a new label that identifies where the instuction is going. + """Returns a new label that identifies where the instruction is going. Note: it eases linking IR blocs """ diff --git a/miasm2/arch/msp430/arch.py b/miasm2/arch/msp430/arch.py index a8f75f39..f0db98f3 100644 --- a/miasm2/arch/msp430/arch.py +++ b/miasm2/arch/msp430/arch.py @@ -236,7 +236,7 @@ class mn_msp430(cls_mn): return 0 o = 0 if n > bs.getlen() * 8: - raise ValueError('not enought bits %r %r' % (n, len(bs.bin) * 8)) + raise ValueError('not enough bits %r %r' % (n, len(bs.bin) * 8)) while n: i = start / 8 c = cls.getbytes(bs, i) diff --git a/miasm2/arch/msp430/ctype.py b/miasm2/arch/msp430/ctype.py index adb0a953..464adaf8 100644 --- a/miasm2/arch/msp430/ctype.py +++ b/miasm2/arch/msp430/ctype.py @@ -3,7 +3,7 @@ from miasm2.core.ctypesmngr import CTypeId, CTypePtr class CTypeMSP430_unk(CLeafTypes): - """Define C types sizes/alignement for msp430 architecture""" + """Define C types sizes/alignment for msp430 architecture""" obj_pad = ObjCDecl(PADDING_TYPE_NAME, 1, 1) # __padding__ is size 1/align 1 diff --git a/miasm2/arch/sh4/arch.py b/miasm2/arch/sh4/arch.py index c6dea0d6..88d734a3 100644 --- a/miasm2/arch/sh4/arch.py +++ b/miasm2/arch/sh4/arch.py @@ -508,7 +508,7 @@ class mn_sh4(cls_mn): return 0 o = 0 if n > bs.getlen() * 8: - raise ValueError('not enought bits %r %r' % (n, len(bs.bin) * 8)) + raise ValueError('not enough bits %r %r' % (n, len(bs.bin) * 8)) while n: i = start / 8 c = cls.getbytes(bs, i) diff --git a/miasm2/arch/x86/arch.py b/miasm2/arch/x86/arch.py index feafcd44..77744ccd 100644 --- a/miasm2/arch/x86/arch.py +++ b/miasm2/arch/x86/arch.py @@ -275,7 +275,7 @@ class x86_arg(m_arg): loc_key = loc_db.get_or_create_name_location(value.name) return ExprLoc(loc_key, size_hint) if isinstance(value, AstOp): - # First pass to retreive fixed_size + # First pass to retrieve fixed_size if value.op == "segm": segm = self.asm_ast_to_expr(value.args[0], loc_db) ptr = self.asm_ast_to_expr(value.args[1], loc_db, None, fixed_size) @@ -930,7 +930,7 @@ class bs_modname_size(bs_divert): (dct['mode'], dct['opmode'], dct['admode'])) mode = dct['mode'] size, opmode, admode = dct['mode'], dct['opmode'], dct['admode'] - # no mode64 existance in name means no 64bit version of mnemo + # no mode64 exinstance in name means no 64bit version of mnemo if mode == 64: if mode in self.args['name']: nfields = fields[:] diff --git a/miasm2/arch/x86/ctype.py b/miasm2/arch/x86/ctype.py index 5e16f945..5d1be0de 100644 --- a/miasm2/arch/x86/ctype.py +++ b/miasm2/arch/x86/ctype.py @@ -3,7 +3,7 @@ from miasm2.core.ctypesmngr import CTypeId, CTypePtr class CTypeAMD64_unk(CLeafTypes): - """Define C types sizes/alignement for x86_64 architecture""" + """Define C types sizes/alignment for x86_64 architecture""" obj_pad = ObjCDecl(PADDING_TYPE_NAME, 1, 1) # __padding__ is size 1/align 1 @@ -72,7 +72,7 @@ class CTypeAMD64_unk(CLeafTypes): class CTypeX86_unk(CLeafTypes): - """Define C types sizes/alignement for x86_32 architecture""" + """Define C types sizes/alignment for x86_32 architecture""" obj_pad = ObjCDecl(PADDING_TYPE_NAME, 1, 1) # __padding__ is size 1/align 1 diff --git a/miasm2/arch/x86/sem.py b/miasm2/arch/x86/sem.py index b8317ea7..244aff30 100644 --- a/miasm2/arch/x86/sem.py +++ b/miasm2/arch/x86/sem.py @@ -314,8 +314,8 @@ def fix_mem_args_size(instr, *args): def mem2double(instr, arg): """ - Add float convertion if argument is an ExprMem - @arg: argument to tranform + Add float conversion if argument is an ExprMem + @arg: argument to transform """ if isinstance(arg, m2_expr.ExprMem): if arg.size > 64: @@ -341,8 +341,8 @@ def gen_jcc(ir, instr, cond, dst, jmp_if): Macro to generate jcc semantic @ir: ir instance @instr: instruction - @cond: condtion of the jcc - @dst: the dstination if jcc is taken + @cond: condition of the jcc + @dst: the destination if jcc is taken @jmp_if: jump if/notif cond """ @@ -733,7 +733,7 @@ def _shift_tpl(op, ir, instr, a, b, c=None, op_inv=None, left=False, isize = m2_expr.ExprInt(a.size, size=a.size) mask = m2_expr.ExprOp(op_inv, i1, (isize - shifter)) - i1 - # An overflow can occured, emulate the 'undefined behavior' + # An overflow can occurred, emulate the 'undefined behavior' # Overflow behavior if (shift / size % 2) base_cond_overflow = shifter if left else ( shifter - m2_expr.ExprInt(1, size=shifter.size)) @@ -755,7 +755,7 @@ def _shift_tpl(op, ir, instr, a, b, c=None, op_inv=None, left=False, cf_from_src = cf_from_src.msb() if left else cf_from_src[:1] new_cf = m2_expr.ExprCond(cond_overflow, cf_from_src, cf_from_dst) - # Overflow flag, only occured when shifter is equal to 1 + # Overflow flag, only occurred when shifter is equal to 1 if custom_of is None: value_of = a.msb() ^ a[-2:-1] if left else b[:1] ^ a.msb() else: @@ -3641,12 +3641,12 @@ def movd(_, instr, dst, src): def movdqu(_, instr, dst, src): - # XXX TODO alignement check + # XXX TODO alignment check return [m2_expr.ExprAssign(dst, src)], [] def movapd(_, instr, dst, src): - # XXX TODO alignement check + # XXX TODO alignment check return [m2_expr.ExprAssign(dst, src)], [] @@ -3899,7 +3899,7 @@ def _average(expr): arg1 = expr.args[0].zeroExtend(expr.size * 2) arg2 = expr.args[1].zeroExtend(expr.size * 2) one = m2_expr.ExprInt(1, arg1.size) - # avg(unsigned) = (a + b + 1) >> 1, addition beeing at least on one more bit + # avg(unsigned) = (a + b + 1) >> 1, addition being at least on one more bit return ((arg1 + arg2 + one) >> one)[:expr.size] pavgb = vec_vertical_instr('avg', 8, _average) @@ -4843,7 +4843,7 @@ def _saturation_sub_unsigned(expr): def _saturation_sub_signed(expr): assert expr.is_op("+") and len(expr.args) == 2 and expr.args[-1].is_op("-") - # Compute the substraction on two more bits, see _saturation_sub_unsigned + # Compute the subtraction on two more bits, see _saturation_sub_unsigned arg1 = expr.args[0].signExtend(expr.size + 2) arg2 = expr.args[1].args[0].signExtend(expr.size + 2) return _signed_saturation(arg1 - arg2, expr.size) @@ -4857,7 +4857,7 @@ def _saturation_add(expr): arg1 = expr.args[0].zeroExtend(expr.size + 1) arg2 = expr.args[1].zeroExtend(expr.size + 1) - # We can also use _unsigned_saturation with two additionnal bits (to + # We can also use _unsigned_saturation with two additional bits (to # distinguish minus and overflow case) # The resulting expression being more complicated with an impossible case # (signed=True), we rewrite the rule here @@ -4868,7 +4868,7 @@ def _saturation_add(expr): def _saturation_add_signed(expr): assert expr.is_op("+") and len(expr.args) == 2 - # Compute the substraction on two more bits, see _saturation_add_unsigned + # Compute the subtraction on two more bits, see _saturation_add_unsigned arg1 = expr.args[0].signExtend(expr.size + 2) arg2 = expr.args[1].signExtend(expr.size + 2) @@ -5306,10 +5306,10 @@ mnemo_func = {'mov': mov, "movd": movd, "movdqu": movdqu, "movdqa": movdqu, - "movapd": movapd, # XXX TODO alignement check - "movupd": movapd, # XXX TODO alignement check - "movaps": movapd, # XXX TODO alignement check - "movups": movapd, # XXX TODO alignement check + "movapd": movapd, # XXX TODO alignment check + "movupd": movapd, # XXX TODO alignment check + "movaps": movapd, # XXX TODO alignment check + "movups": movapd, # XXX TODO alignment check "andps": andps, "andpd": andps, "andnps": andnps, @@ -5600,7 +5600,7 @@ class ir_x86_16(IntermediateRepresentation): self.IRDst = m2_expr.ExprId('IRDst', 16) # Size of memory pointer access in IR # 16 bit mode memory accesses may be greater than 16 bits - # 32 bit size may be enought + # 32 bit size may be enough self.addrsize = 32 def mod_pc(self, instr, instr_ir, extra_ir): |