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-rw-r--r--miasm2/arch/x86/arch.py2
-rw-r--r--miasm2/arch/x86/sem.py8
2 files changed, 5 insertions, 5 deletions
diff --git a/miasm2/arch/x86/arch.py b/miasm2/arch/x86/arch.py
index 11c1e00f..7f9d50e6 100644
--- a/miasm2/arch/x86/arch.py
+++ b/miasm2/arch/x86/arch.py
@@ -902,7 +902,7 @@ class mn_x86(cls_mn):
             if hasattr(c, "fadmode") and v_admode(c) != c.fadmode.mode:
                 continue
             # relative dstflow must not have opmode set
-            # (affect IP instead of EIP for instance)
+            # (assign IP instead of EIP for instance)
             if (instr.dstflow() and
                 instr.name not in ["JCXZ", "JECXZ", "JRCXZ"] and
                 len(instr.args) == 1 and
diff --git a/miasm2/arch/x86/sem.py b/miasm2/arch/x86/sem.py
index e01adcbc..862240e5 100644
--- a/miasm2/arch/x86/sem.py
+++ b/miasm2/arch/x86/sem.py
@@ -1710,7 +1710,7 @@ def div(ir, instr, src1):
     c_d = m2_expr.ExprOp('udiv', src2, src1.zeroExtend(src2.size))
     c_r = m2_expr.ExprOp('umod', src2, src1.zeroExtend(src2.size))
 
-    # if 8 bit div, only ax is affected
+    # if 8 bit div, only ax is assigned
     if size == 8:
         e.append(m2_expr.ExprAssign(src2, m2_expr.ExprCompose(c_d[:8], c_r[:8])))
     else:
@@ -1757,7 +1757,7 @@ def idiv(ir, instr, src1):
     c_d = m2_expr.ExprOp('sdiv', src2, src1.signExtend(src2.size))
     c_r = m2_expr.ExprOp('smod', src2, src1.signExtend(src2.size))
 
-    # if 8 bit div, only ax is affected
+    # if 8 bit div, only ax is assigned
     if size == 8:
         e.append(m2_expr.ExprAssign(src2, m2_expr.ExprCompose(c_d[:8], c_r[:8])))
     else:
@@ -4026,7 +4026,7 @@ cmpordsd = vec_op_clip('ord', 64, lambda x: _float_compare_to_mask(x))
 def pand(_, instr, dst, src):
     e = []
     result = dst & src
-    # No flag affected
+    # No flag assigned
     e.append(m2_expr.ExprAssign(dst, result))
     return e, []
 
@@ -4034,7 +4034,7 @@ def pand(_, instr, dst, src):
 def pandn(_, instr, dst, src):
     e = []
     result = (dst ^ dst.mask) & src
-    # No flag affected
+    # No flag assigned
     e.append(m2_expr.ExprAssign(dst, result))
     return e, []