6 files changed, 4 insertions, 8 deletions
diff --git a/miasm2/arch/aarch64/arch.py b/miasm2/arch/aarch64/arch.py
index 460c134e..f352f547 100644
--- a/miasm2/arch/aarch64/arch.py
+++ b/miasm2/arch/aarch64/arch.py
@@ -8,7 +8,7 @@ from collections import defaultdict
 from miasm2.core.bin_stream import bin_stream
 import regs as regs_module
 from regs import *
-from miasm2.core.asmbloc import asm_label
+from miasm2.core.asmbloc import AsmLabel
 from miasm2.core.cpu import log as log_cpu
 from miasm2.expression.modint import uint32, uint64
 import math
@@ -207,7 +207,7 @@ simdregs_h_zero = (simd32_info.parser |
 
 def ast_id2expr(t):
     if not t in mn_aarch64.regs.all_regs_ids_byname:
-        r = m2_expr.ExprId(asm_label(t))
+        r = m2_expr.ExprId(AsmLabel(t))
     else:
         r = mn_aarch64.regs.all_regs_ids_byname[t]
     return r
diff --git a/miasm2/arch/arm/arch.py b/miasm2/arch/arm/arch.py
index d9bf42ba..54a168af 100644
--- a/miasm2/arch/arm/arch.py
+++ b/miasm2/arch/arm/arch.py
@@ -8,7 +8,6 @@ from collections import defaultdict
 from miasm2.core.bin_stream import bin_stream
 import miasm2.arch.arm.regs as regs_module
 from miasm2.arch.arm.regs import *
-from miasm2.core.asmbloc import asm_label
 
 # A1 encoding
 
diff --git a/miasm2/arch/mips32/arch.py b/miasm2/arch/mips32/arch.py
index 79176205..f11c6e3a 100644
--- a/miasm2/arch/mips32/arch.py
+++ b/miasm2/arch/mips32/arch.py
@@ -9,7 +9,6 @@ from miasm2.expression.expression import ExprMem, ExprInt, ExprInt32, ExprId
 from miasm2.core.bin_stream import bin_stream
 import miasm2.arch.mips32.regs as regs
 import miasm2.core.cpu as cpu
-from miasm2.core.asmbloc import asm_label
 
 log = logging.getLogger("mips32dis")
 console_handler = logging.StreamHandler()
diff --git a/miasm2/arch/msp430/arch.py b/miasm2/arch/msp430/arch.py
index d7463f3d..07ba3019 100644
--- a/miasm2/arch/msp430/arch.py
+++ b/miasm2/arch/msp430/arch.py
@@ -8,7 +8,6 @@ from collections import defaultdict
 from miasm2.core.bin_stream import bin_stream
 import miasm2.arch.msp430.regs as regs_module
 from miasm2.arch.msp430.regs import *
-from miasm2.core.asmbloc import asm_label
 
 log = logging.getLogger("msp430dis")
 console_handler = logging.StreamHandler()
diff --git a/miasm2/arch/sh4/arch.py b/miasm2/arch/sh4/arch.py
index ae96fef1..634cbf43 100644
--- a/miasm2/arch/sh4/arch.py
+++ b/miasm2/arch/sh4/arch.py
@@ -6,7 +6,6 @@ from miasm2.expression.expression import *
 from collections import defaultdict
 import miasm2.arch.sh4.regs as regs_module
 from miasm2.arch.sh4.regs import *
-from miasm2.core.asmbloc import asm_label
 
 jra = ExprId('jra')
 jrb = ExprId('jrb')
diff --git a/miasm2/arch/x86/arch.py b/miasm2/arch/x86/arch.py
index 8ae6cd31..55775a1a 100644
--- a/miasm2/arch/x86/arch.py
+++ b/miasm2/arch/x86/arch.py
@@ -7,7 +7,7 @@ from miasm2.core.cpu import *
 from collections import defaultdict
 import miasm2.arch.x86.regs as regs_module
 from miasm2.arch.x86.regs import *
-from miasm2.core.asmbloc import asm_label
+from miasm2.core.asmbloc import AsmLabel
 
 log = logging.getLogger("x86_arch")
 console_handler = logging.StreamHandler()
@@ -489,7 +489,7 @@ class instruction_x86(instruction):
             return
         expr = self.args[0]
         if isinstance(expr, ExprId):
-            if not isinstance(expr.name, asm_label) and expr not in all_regs_ids:
+            if not isinstance(expr.name, AsmLabel) and expr not in all_regs_ids:
                 raise ValueError("ExprId must be a label or a register")
         elif isinstance(expr, ExprInt):
             ad = expr.arg + int(self.offset)