diff options
Diffstat (limited to 'miasm2/arch')
28 files changed, 513 insertions, 414 deletions
diff --git a/miasm2/arch/aarch64/arch.py b/miasm2/arch/aarch64/arch.py index 015464d6..3a4f6446 100644 --- a/miasm2/arch/aarch64/arch.py +++ b/miasm2/arch/aarch64/arch.py @@ -1,13 +1,16 @@ #-*- coding:utf-8 -*- +from builtins import range +from future.utils import viewitems, viewvalues + import logging from pyparsing import * from miasm2.expression import expression as m2_expr from miasm2.core.cpu import * from collections import defaultdict from miasm2.core.bin_stream import bin_stream -import regs as regs_module -from regs import * +from miasm2.arch.aarch64 import regs as regs_module +from miasm2.arch.aarch64.regs import * from miasm2.core.cpu import log as log_cpu from miasm2.expression.modint import uint32, uint64, mod_size2int from miasm2.core.asm_ast import AstInt, AstId, AstMem, AstOp @@ -182,7 +185,7 @@ def cb_deref_nooff(t): def cb_deref_post(t): assert len(t) == 2 if isinstance(t[1], AstId) and isinstance(t[1].name, ExprId): - raise StopIteration + return result = AstOp("postinc", *t) return result @@ -190,7 +193,7 @@ def cb_deref_post(t): def cb_deref_pre(t): assert len(t) == 2 if isinstance(t[1], AstId) and isinstance(t[1].name, ExprId): - raise StopIteration + return result = AstOp("preinc", *t) return result @@ -198,7 +201,7 @@ def cb_deref_pre(t): def cb_deref_pre_wb(t): assert len(t) == 2 if isinstance(t[1], AstId) and isinstance(t[1].name, ExprId): - raise StopIteration + return result = AstOp("preinc_wb", *t) return result @@ -234,7 +237,7 @@ def cb_deref_ext2op(t): deref_ext2 = (LBRACK + gpregs_32_64 + COMMA + gpregs_32_64 + Optional(all_extend2_t + base_expr) + RBRACK).setParseAction(cb_deref_ext2op) -class additional_info: +class additional_info(object): def __init__(self): self.except_on_instr = False @@ -275,7 +278,7 @@ class aarch64_arg(m_arg): if isinstance(value.name, ExprId): fixed_size.add(value.name.size) return value.name - loc_key = loc_db.get_or_create_name_location(value.name) + loc_key = loc_db.get_or_create_name_location(value.name.encode()) return m2_expr.ExprLoc(loc_key, size_hint) if isinstance(value, AstInt): assert size_hint is not None @@ -446,7 +449,7 @@ class mn_aarch64(cls_mn): if n > bs.getlen() * 8: raise ValueError('not enough bits %r %r' % (n, len(bs.bin) * 8)) while n: - offset = start / 8 + offset = start // 8 n_offset = cls.endian_offset(attrib, offset) c = cls.getbytes(bs, n_offset, 1) if not c: @@ -897,11 +900,14 @@ class aarch64_gpreg_ext(reg_noarg, aarch64_arg): reg, m2_expr.ExprInt(self.parent.imm.value, reg.size)) return True -EXT2_OP = {0b010: 'UXTW', - 0b011: 'LSL', - 0b110: 'SXTW', - 0b111: 'SXTX'} -EXT2_OP_INV = dict([(items[1], items[0]) for items in EXT2_OP.items()]) +EXT2_OP = { + 0b010: 'UXTW', + 0b011: 'LSL', + 0b110: 'SXTW', + 0b111: 'SXTX' +} + +EXT2_OP_INV = dict((value, key) for key, value in viewitems(EXT2_OP)) class aarch64_gpreg_ext2(reg_noarg, aarch64_arg): @@ -933,7 +939,7 @@ class aarch64_gpreg_ext2(reg_noarg, aarch64_arg): reg = arg1 self.parent.option.value = 0b011 is_reg = True - elif isinstance(arg1, m2_expr.ExprOp) and arg1.op in EXT2_OP.values(): + elif isinstance(arg1, m2_expr.ExprOp) and arg1.op in viewvalues(EXT2_OP): reg = arg1.args[0] else: return False @@ -1069,10 +1075,15 @@ class bits(object): def __init__(self, size, value): """Instantiate a bitvector of size @size with value @value""" - self.size = size + value = int(value) + self.size = int(size) if value & self.mask != value: - raise ValueError("Value %s is too large for %d bits", - hex(value), size) + raise ValueError( + "Value %r is too large for %r bits (mask %r)", + value, + size, + self.mask + ) self.value = value def concat_left(self, other_bits): @@ -1123,11 +1134,11 @@ class bits(object): def __str__(self): return "'%s'" % "".join('1' if self.value & (1 << i) else '0' - for i in reversed(xrange(self.size))) + for i in reversed(range(self.size))) # From J1-6035 def HighestSetBit(x): - for i in reversed(xrange(x.size)): + for i in reversed(range(x.size)): if x.value & (1 << i): return i return - 1 @@ -1198,7 +1209,7 @@ def DecodeBitMasks(M, immN, imms, immr, immediate): def EncodeBitMasks(wmask): # Find replicate M = wmask.size - for i in xrange(1, M + 1): + for i in range(1, M + 1): if M % i != 0: continue if wmask == Replicate(wmask[:i], M): @@ -1211,7 +1222,7 @@ def EncodeBitMasks(wmask): esize = welem_after_ror.size S = welem_after_ror.pop_count - 1 welem = ZeroExtend(Ones(S + 1), esize) - for i in xrange(welem_after_ror.size): + for i in range(welem_after_ror.size): if ROR(welem, i) == welem_after_ror: break else: @@ -1219,7 +1230,7 @@ def EncodeBitMasks(wmask): R = i # Find len value - for i in xrange(M): + for i in range(M): if (1 << i) == esize: break else: @@ -1340,7 +1351,7 @@ class aarch64_imm_hw(aarch64_arg): return False value = int(self.expr) mask = (1 << size) - 1 - for i in xrange(size / 16): + for i in range(size // 16): if ((0xffff << (i * 16)) ^ mask) & value: continue self.parent.hw.value = i @@ -1384,10 +1395,10 @@ class aarch64_imm_hw_sc(aarch64_arg): arg, amount = [int(arg) for arg in self.expr.args] if arg > 0xFFFF: return False - if amount % 16 or amount / 16 > 4: + if amount % 16 or amount // 16 > 4: return False self.value = arg - self.parent.hw.value = amount / 16 + self.parent.hw.value = amount // 16 return True @@ -1852,8 +1863,8 @@ bcond = bs_mod_name(l=4, fname='cond', mn_mod=['EQ', 'NE', 'CS', 'CC', 'HI', 'LS', 'GE', 'LT', 'GT', 'LE', 'AL', 'NV']) -cond_arg = bs(l=4, cls=(aarch64_cond_arg,), fname=cond) -cond_inv_arg = bs(l=4, cls=(aarch64_cond_inv_arg,), fname=cond) +cond_arg = bs(l=4, cls=(aarch64_cond_arg,), fname="cond") +cond_inv_arg = bs(l=4, cls=(aarch64_cond_inv_arg,), fname="cond") # unconditional branch (ret) aarch64op("br", [bs('1101011'), bs('0000'), bs('11111'), bs('000000'), rn64, bs('00000')], [rn64]) aarch64op("blr", [bs('1101011'), bs('0001'), bs('11111'), bs('000000'), rn64, bs('00000')], [rn64]) @@ -2037,7 +2048,7 @@ aarch64op("fcvt", [bs('000'), bs('11110'), bs('01'), bs('1'), bs('0001'), bs('0 -swapargs = bs_swapargs(l=1, fname="swap", mn_mod=range(1 << 1)) +swapargs = bs_swapargs(l=1, fname="swap", mn_mod=list(range(1 << 1))) aarch64op("fmov", [bs('0'), bs('00'), bs('11110'), bs('00'), bs('1'), bs('00'), bs('110'), bs('000000'), sn32, rd32], [rd32, sn32]) aarch64op("fmov", [bs('0'), bs('00'), bs('11110'), bs('00'), bs('1'), bs('00'), bs('111'), bs('000000'), rn32, sd32], [sd32, rn32]) diff --git a/miasm2/arch/aarch64/jit.py b/miasm2/arch/aarch64/jit.py index 9873464a..57b896d3 100644 --- a/miasm2/arch/aarch64/jit.py +++ b/miasm2/arch/aarch64/jit.py @@ -1,3 +1,4 @@ +from builtins import range import logging from miasm2.jitter.jitload import Jitter, named_arguments @@ -35,9 +36,9 @@ class jitter_aarch64l(Jitter): @named_arguments def func_args_stdcall(self, n_args): args = [] - for i in xrange(min(n_args, self.max_reg_arg)): + for i in range(min(n_args, self.max_reg_arg)): args.append(getattr(self.cpu, 'X%d' % i)) - for i in xrange(max(0, n_args - self.max_reg_arg)): + for i in range(max(0, n_args - self.max_reg_arg)): args.append(self.get_stack_arg(i)) ret_ad = self.cpu.LR return ret_ad, args @@ -56,9 +57,9 @@ class jitter_aarch64l(Jitter): return arg def func_prepare_stdcall(self, ret_addr, *args): - for index in xrange(min(len(args), 4)): + for index in range(min(len(args), 4)): setattr(self.cpu, 'X%d' % index, args[index]) - for index in xrange(4, len(args)): + for index in range(4, len(args)): self.vm.set_mem(self.cpu.SP + 8 * (index - 4), pck64(args[index])) self.cpu.LR = ret_addr diff --git a/miasm2/arch/aarch64/regs.py b/miasm2/arch/aarch64/regs.py index 1c693b4c..7ddcc0b8 100644 --- a/miasm2/arch/aarch64/regs.py +++ b/miasm2/arch/aarch64/regs.py @@ -1,5 +1,6 @@ #-*- coding:utf-8 -*- +from builtins import range from miasm2.expression.expression import ExprId from miasm2.core.cpu import gen_reg, gen_regs @@ -7,40 +8,40 @@ exception_flags = ExprId('exception_flags', 32) interrupt_num = ExprId('interrupt_num', 32) -gpregs32_str = ["W%d" % i for i in xrange(0x1f)] + ["WSP"] +gpregs32_str = ["W%d" % i for i in range(0x1f)] + ["WSP"] gpregs32_expr, gpregs32_init, gpregs32_info = gen_regs( gpregs32_str, globals(), 32) -gpregs64_str = ["X%d" % i for i in xrange(0x1E)] + ["LR", "SP"] +gpregs64_str = ["X%d" % i for i in range(0x1E)] + ["LR", "SP"] gpregs64_expr, gpregs64_init, gpregs64_info = gen_regs( gpregs64_str, globals(), 64) -gpregsz32_str = ["W%d" % i for i in xrange(0x1f)] + ["WZR"] +gpregsz32_str = ["W%d" % i for i in range(0x1f)] + ["WZR"] gpregsz32_expr, gpregsz32_init, gpregsz32_info = gen_regs( gpregsz32_str, globals(), 32) -gpregsz64_str = ["X%d" % i for i in xrange(0x1e)] + ["LR", "XZR"] +gpregsz64_str = ["X%d" % i for i in range(0x1e)] + ["LR", "XZR"] gpregsz64_expr, gpregsz64_init, gpregsz64_info = gen_regs( gpregsz64_str, globals(), 64) -cr_str = ["c%d" % i for i in xrange(0xf)] +cr_str = ["c%d" % i for i in range(0xf)] cr_expr, cr_init, cr_info = gen_regs(cr_str, globals(), 32) -simd08_str = ["B%d" % i for i in xrange(0x20)] +simd08_str = ["B%d" % i for i in range(0x20)] simd08_expr, simd08_init, simd08_info = gen_regs(simd08_str, globals(), 8) -simd16_str = ["H%d" % i for i in xrange(0x20)] +simd16_str = ["H%d" % i for i in range(0x20)] simd16_expr, simd16_init, simd16_info = gen_regs(simd16_str, globals(), 16) -simd32_str = ["S%d" % i for i in xrange(0x20)] +simd32_str = ["S%d" % i for i in range(0x20)] simd32_expr, simd32_init, simd32_info = gen_regs(simd32_str, globals(), 32) -simd64_str = ["D%d" % i for i in xrange(0x20)] +simd64_str = ["D%d" % i for i in range(0x20)] simd64_expr, simd64_init, simd64_info = gen_regs(simd64_str, globals(), 64) -simd128_str = ["Q%d" % i for i in xrange(0x20)] +simd128_str = ["Q%d" % i for i in range(0x20)] simd128_expr, simd128_init, simd128_info = gen_regs( simd128_str, globals(), 128) diff --git a/miasm2/arch/aarch64/sem.py b/miasm2/arch/aarch64/sem.py index 7052f423..a840f6b6 100644 --- a/miasm2/arch/aarch64/sem.py +++ b/miasm2/arch/aarch64/sem.py @@ -1,3 +1,6 @@ +from builtins import range +from future.utils import viewitems + from miasm2.expression.expression import ExprId, ExprInt, ExprLoc, ExprMem, \ ExprCond, ExprCompose, ExprOp, ExprAssign from miasm2.ir.ir import IntermediateRepresentation, IRBlock, AssignBlock @@ -675,7 +678,7 @@ def stp(ir, instr, arg1, arg2, arg3): addr, updt = get_mem_access(arg3) e.append(ExprAssign(ExprMem(addr, arg1.size), arg1)) e.append( - ExprAssign(ExprMem(addr + ExprInt(arg1.size / 8, addr.size), arg2.size), arg2)) + ExprAssign(ExprMem(addr + ExprInt(arg1.size // 8, addr.size), arg2.size), arg2)) if updt: e.append(updt) return e, [] @@ -686,7 +689,7 @@ def ldp(ir, instr, arg1, arg2, arg3): addr, updt = get_mem_access(arg3) e.append(ExprAssign(arg1, ExprMem(addr, arg1.size))) e.append( - ExprAssign(arg2, ExprMem(addr + ExprInt(arg1.size / 8, addr.size), arg2.size))) + ExprAssign(arg2, ExprMem(addr + ExprInt(arg1.size // 8, addr.size), arg2.size))) if updt: e.append(updt) return e, [] @@ -1012,7 +1015,7 @@ def nop(): def rev(ir, instr, arg1, arg2): out = [] - for i in xrange(0, arg2.size, 8): + for i in range(0, arg2.size, 8): out.append(arg2[i:i+8]) out.reverse() e = [] @@ -1023,7 +1026,7 @@ def rev(ir, instr, arg1, arg2): def rev16(ir, instr, arg1, arg2): out = [] - for i in xrange(0, arg2.size / 8): + for i in range(0, arg2.size // 8): index = (i & ~1) + (1 - (i & 1)) out.append(arg2[index * 8:(index + 1) * 8]) e = [] @@ -1248,8 +1251,8 @@ def casp(ir, instr, arg1, arg2, arg3): blk_store = IRBlock(loc_store.loc_key, [AssignBlock(e_store, instr)]) e_do = [] - e_do.append(ExprAssign(regs[index1], data[:data.size / 2])) - e_do.append(ExprAssign(regs[index1 + 1], data[data.size / 2:])) + e_do.append(ExprAssign(regs[index1], data[:data.size // 2])) + e_do.append(ExprAssign(regs[index1 + 1], data[data.size // 2:])) e_do.append(ExprAssign(ir.IRDst, loc_next)) blk_do = IRBlock(loc_do.loc_key, [AssignBlock(e_do, instr)]) @@ -1399,7 +1402,7 @@ def get_mnemo_expr(ir, instr, *args): return instr, extra_ir -class aarch64info: +class aarch64info(object): mode = "aarch64" # offset @@ -1438,7 +1441,7 @@ class ir_aarch64l(IntermediateRepresentation): irs = [] for assignblk in irblock: new_assignblk = dict(assignblk) - for dst, src in assignblk.iteritems(): + for dst, src in viewitems(assignblk): del(new_assignblk[dst]) # Special case for 64 bits: # If destination is a 32 bit reg, zero extend the 64 bit reg @@ -1480,8 +1483,10 @@ class ir_aarch64l(IntermediateRepresentation): for irblock in extra_ir: irs = [] for assignblk in irblock: - new_dsts = {dst:src for dst, src in assignblk.iteritems() - if dst not in regs_to_fix} + new_dsts = { + dst:src for dst, src in viewitems(assignblk) + if dst not in regs_to_fix + } irs.append(AssignBlock(new_dsts, assignblk.instr)) new_irblocks.append(IRBlock(irblock.loc_key, irs)) diff --git a/miasm2/arch/arm/arch.py b/miasm2/arch/arm/arch.py index c50748e4..3cafad59 100644 --- a/miasm2/arch/arm/arch.py +++ b/miasm2/arch/arm/arch.py @@ -1,5 +1,8 @@ #-*- coding:utf-8 -*- +from builtins import range +from future.utils import viewitems + import logging from pyparsing import * from miasm2.expression.expression import * @@ -24,7 +27,7 @@ reg_dum = ExprId('DumReg', 32) PC, _ = gen_reg('PC') # GP -regs_str = ['R%d' % r for r in xrange(0x10)] +regs_str = ['R%d' % r for r in range(0x10)] regs_str[13] = 'SP' regs_str[14] = 'LR' regs_str[15] = 'PC' @@ -49,9 +52,9 @@ gpregs_nosp = reg_info(regs_str[:13] + [str(reg_dum), regs_str[14], regs_str[15] sr_flags = "cxsf" cpsr_regs_str = [] spsr_regs_str = [] -for i in xrange(0x10): +for i in range(0x10): o = "" - for j in xrange(4): + for j in range(4): if i & (1 << j): o += sr_flags[j] cpsr_regs_str.append("CPSR_%s" % o) @@ -69,13 +72,13 @@ cpsr_regs = reg_info(cpsr_regs_str, cpsr_regs_expr) spsr_regs = reg_info(spsr_regs_str, spsr_regs_expr) # CP -cpregs_str = ['c%d' % r for r in xrange(0x10)] +cpregs_str = ['c%d' % r for r in range(0x10)] cpregs_expr = [ExprId(x, 32) for x in cpregs_str] cp_regs = reg_info(cpregs_str, cpregs_expr) # P -pregs_str = ['p%d' % r for r in xrange(0x10)] +pregs_str = ['p%d' % r for r in range(0x10)] pregs_expr = [ExprId(x, 32) for x in pregs_str] p_regs = reg_info(pregs_str, pregs_expr) @@ -110,7 +113,7 @@ def cb_tok_reg_duo(tokens): i1 = gpregs.expr.index(tokens[0].name) i2 = gpregs.expr.index(tokens[1].name) o = [] - for i in xrange(i1, i2 + 1): + for i in range(i1, i2 + 1): o.append(AstId(gpregs.expr[i])) return o @@ -155,7 +158,7 @@ allshifts_armt = ['<<', '>>', 'a>>', '>>>', 'rrx'] shift2expr_dct = {'LSL': '<<', 'LSR': '>>', 'ASR': 'a>>', 'ROR': ">>>", 'RRX': "rrx"} -expr2shift_dct = dict([(x[1], x[0]) for x in shift2expr_dct.items()]) +expr2shift_dct = dict((value, key) for key, value in viewitems(shift2expr_dct)) def op_shift2expr(tokens): @@ -321,13 +324,13 @@ def permut_args(order, args): for i, x in enumerate(order): l.append((x.__class__, i)) l = dict(l) - out = [None for x in xrange(len(args))] + out = [None for x in range(len(args))] for a in args: out[l[a.__class__]] = a return out -class additional_info: +class additional_info(object): def __init__(self): self.except_on_instr = False @@ -400,8 +403,10 @@ class instruction_arm(instruction): else: r, s = expr.args[0].args if isinstance(s, ExprOp) and s.op in expr2shift_dct: - s = ' '.join([str(x) - for x in s.args[0], expr2shift_dct[s.op], s.args[1]]) + s = ' '.join( + str(x) + for x in (s.args[0], expr2shift_dct[s.op], s.args[1]) + ) if isinstance(expr, ExprOp) and expr.op == 'postinc': o = '[%s]' % r @@ -563,7 +568,7 @@ class instruction_armt(instruction_arm): def get_asm_offset(self, expr): # ADR XXX, PC, imm => PC is 4 aligned + imm - new_offset = ((self.offset+self.l)/4)*4 + new_offset = ((self.offset + self.l) // 4) * 4 return ExprInt(new_offset, expr.size) @@ -610,7 +615,7 @@ class mn_arm(cls_mn): if n > bs.getlen() * 8: raise ValueError('not enough bits %r %r' % (n, len(bs.bin) * 8)) while n: - offset = start / 8 + offset = start // 8 n_offset = cls.endian_offset(attrib, offset) c = cls.getbytes(bs, n_offset, 1) if not c: @@ -711,7 +716,7 @@ class mn_armt(cls_mn): if n > bs.getlen() * 8: raise ValueError('not enough bits %r %r' % (n, len(bs.bin) * 8)) while n: - offset = start / 8 + offset = start // 8 n_offset = cls.endian_offset(attrib, offset) c = cls.getbytes(bs, n_offset, 1) if not c: @@ -784,7 +789,7 @@ class arm_arg(m_arg): return arg.name if arg.name in gpregs.str: return None - loc_key = loc_db.get_or_create_name_location(arg.name) + loc_key = loc_db.get_or_create_name_location(arg.name.encode()) return ExprLoc(loc_key, 32) if isinstance(arg, AstOp): args = [self.asm_ast_to_expr(tmp, loc_db) for tmp in arg.args] @@ -1025,10 +1030,10 @@ class arm_op2(arm_arg): def str_to_imm_rot_form(self, s, neg=False): if neg: s = -s & 0xffffffff - for i in xrange(0, 32, 2): + for i in range(0, 32, 2): v = myrol32(s, i) if 0 <= v < 0x100: - return ((i / 2) << 8) | v + return ((i // 2) << 8) | v return None def decode(self, v): @@ -1267,7 +1272,7 @@ class arm_rlist(arm_arg): def decode(self, v): v = v & self.lmask out = [] - for i in xrange(0x10): + for i in range(0x10): if 1 << i & v: out.append(gpregs.expr[i]) if not out: @@ -1616,7 +1621,7 @@ data_test_name = {'TST': 8, 'TEQ': 9, 'CMP': 10, 'CMN': 11} data_name = {} for i, n in enumerate(op_list): - if n in data_mov_name.keys() + data_test_name.keys(): + if n in list(data_mov_name) + list(data_test_name): continue data_name[n] = i bs_data_name = bs_name(l=4, name=data_name) @@ -1740,7 +1745,7 @@ class arm_rm_rot2(arm_arg): value = int(value) if not value in [8, 16, 24]: return False - self.parent.rot2.value = value / 8 + self.parent.rot2.value = value // 8 return True class arm_gpreg_nopc(reg_noarg): @@ -2052,7 +2057,7 @@ class armt_rlist(arm_arg): def decode(self, v): v = v & self.lmask out = [] - for i in xrange(0x10): + for i in range(0x10): if 1 << i & v: out.append(gpregs.expr[i]) if not out: @@ -2093,7 +2098,7 @@ class armt_rlist13(armt_rlist): def decode(self, v): v = v & self.lmask out = [] - for i in xrange(13): + for i in range(13): if 1 << i & v: out.append(gpregs_l_13.expr[i]) @@ -2141,7 +2146,7 @@ class armt_rlist13_pc_lr(armt_rlist): def decode(self, v): v = v & self.lmask out = [] - for i in xrange(13): + for i in range(13): if 1 << i & v: out.append(gpregs_l_13.expr[i]) @@ -2184,7 +2189,7 @@ class armt_rlist_pclr(armt_rlist): def decode(self, v): v = v & self.lmask out = [] - for i in xrange(0x10): + for i in range(0x10): if 1 << i & v: out.append(gpregs.expr[i]) @@ -2522,7 +2527,7 @@ class armt2_imm12(arm_imm): value = (3 << 8) | ((v >> 16) & 0xff) else: # rol encoding - for i in xrange(32): + for i in range(32): o = myrol32(v, i) if 0x80 <= o <= 0xFF: value = (i << 7) | (o & 0x7F) @@ -2860,7 +2865,7 @@ class armt_itmask(bs_divert): def divert(self, i, candidates): out = [] for cls, _, bases, dct, fields in candidates: - for value in xrange(1, 0x10): + for value in range(1, 0x10): nfields = fields[:] s = int2bin(value, self.args['l']) args = dict(self.args) @@ -2881,7 +2886,7 @@ class armt_itmask(bs_divert): values = ['E', 'T'] if inv== 1: values.reverse() - for index in xrange(3 - count): + for index in range(3 - count): if value & (1 << (3 - index)): out.append(values[0]) else: @@ -2896,7 +2901,7 @@ class armt_cond_lsb(bs_divert): def divert(self, i, candidates): out = [] for cls, _, bases, dct, fields in candidates: - for value in xrange(2): + for value in range(2): nfields = fields[:] s = int2bin(value, self.args['l']) args = dict(self.args) diff --git a/miasm2/arch/arm/disasm.py b/miasm2/arch/arm/disasm.py index 5e21778d..2a443cc2 100644 --- a/miasm2/arch/arm/disasm.py +++ b/miasm2/arch/arm/disasm.py @@ -1,3 +1,5 @@ +from future.utils import viewvalues + from miasm2.core.asmblock import AsmConstraint, disasmEngine from miasm2.arch.arm.arch import mn_arm, mn_armt @@ -19,7 +21,7 @@ def cb_arm_fix_call(mn, cur_bloc, loc_db, offsets_to_dis, *args, **kwargs): if l2.name != "MOV": return - values = mn.pc.values() + values = viewvalues(mn.pc) if not l1.args[0] in values: return if not l2.args[1] in values: diff --git a/miasm2/arch/arm/jit.py b/miasm2/arch/arm/jit.py index 06fba210..128baffb 100644 --- a/miasm2/arch/arm/jit.py +++ b/miasm2/arch/arm/jit.py @@ -1,3 +1,4 @@ +from builtins import range import logging from miasm2.jitter.jitload import Jitter, named_arguments @@ -85,7 +86,7 @@ class jitter_arml(Jitter): @named_arguments def func_args_stdcall(self, n_args): - args = [self.get_arg_n_stdcall(i) for i in xrange(n_args)] + args = [self.get_arg_n_stdcall(i) for i in range(n_args)] ret_ad = self.cpu.LR return ret_ad, args @@ -98,9 +99,9 @@ class jitter_arml(Jitter): return True def func_prepare_stdcall(self, ret_addr, *args): - for index in xrange(min(len(args), 4)): + for index in range(min(len(args), 4)): setattr(self.cpu, 'R%d' % index, args[index]) - for index in reversed(xrange(4, len(args))): + for index in reversed(range(4, len(args))): self.push_uint32_t(args[index]) self.cpu.LR = ret_addr diff --git a/miasm2/arch/arm/regs.py b/miasm2/arch/arm/regs.py index e20b00bd..f39f2161 100644 --- a/miasm2/arch/arm/regs.py +++ b/miasm2/arch/arm/regs.py @@ -1,11 +1,12 @@ #-*- coding:utf-8 -*- +from builtins import range from miasm2.expression.expression import * # GP -regs32_str = ["R%d" % i for i in xrange(13)] + ["SP", "LR", "PC"] +regs32_str = ["R%d" % i for i in range(13)] + ["SP", "LR", "PC"] regs32_expr = [ExprId(x, 32) for x in regs32_str] exception_flags = ExprId('exception_flags', 32) diff --git a/miasm2/arch/arm/sem.py b/miasm2/arch/arm/sem.py index 782a99fb..6622a42a 100644 --- a/miasm2/arch/arm/sem.py +++ b/miasm2/arch/arm/sem.py @@ -1,3 +1,6 @@ +from builtins import range +from future.utils import viewitems, viewvalues + from miasm2.expression.expression import * from miasm2.ir.ir import IntermediateRepresentation, IRBlock, AssignBlock from miasm2.arch.arm.arch import mn_arm, mn_armt @@ -1053,7 +1056,7 @@ def rors(ir, instr, a, b): def push(ir, instr, a): e = [] regs = list(a.args) - for i in xrange(len(regs)): + for i in range(len(regs)): r = SP + ExprInt(-4 * len(regs) + 4 * i, 32) e.append(ExprAssign(ExprMem(r, 32), regs[i])) r = SP + ExprInt(-4 * len(regs), 32) @@ -1065,7 +1068,7 @@ def pop(ir, instr, a): e = [] regs = list(a.args) dst = None - for i in xrange(len(regs)): + for i in range(len(regs)): r = SP + ExprInt(4 * i, 32) e.append(ExprAssign(regs[i], ExprMem(r, 32))) if regs[i] == ir.pc: @@ -1271,7 +1274,7 @@ def uadd8(ir, instr, a, b, c): e = [] sums = [] ges = [] - for i in xrange(0, 32, 8): + for i in range(0, 32, 8): sums.append(b[i:i+8] + c[i:i+8]) ges.append((b[i:i+8].zeroExtend(9) + c[i:i+8].zeroExtend(9))[8:9]) @@ -1286,7 +1289,7 @@ def sel(ir, instr, a, b, c): e = [] cond = nf ^ of ^ ExprInt(1, 1) parts = [] - for i in xrange(4): + for i in range(4): parts.append(ExprCond(ge_regs[i], b[i*8:(i+1)*8], c[i*8:(i+1)*8])) result = ExprCompose(*parts) e.append(ExprAssign(a, result)) @@ -1382,7 +1385,7 @@ cond_dct = { # COND_NV: "NV", } -cond_dct_inv = dict((name, num) for num, name in cond_dct.iteritems()) +cond_dct_inv = dict((name, num) for num, name in viewitems(cond_dct)) """ @@ -1425,7 +1428,7 @@ tab_cond = {COND_EQ: ExprOp("CC_EQ", zf), def is_pc_written(ir, instr_ir): - all_pc = ir.mn.pc.values() + all_pc = viewvalues(ir.mn.pc) for ir in instr_ir: if ir.dst in all_pc: return True, ir.dst @@ -1613,8 +1616,8 @@ mn_cond_x = [mnemo_condm0, mnemo_condm2] for index, mn_base in enumerate(mn_cond_x): - for mn, mf in mn_base.items(): - for cond, cn in cond_dct.items(): + for mn, mf in viewitems(mn_base): + for cond, cn in viewitems(cond_dct): if cond == COND_AL: cn = "" cn = cn.lower() @@ -1625,7 +1628,7 @@ for index, mn_base in enumerate(mn_cond_x): # print mn_mod mnemo_func_cond[mn_mod] = cond, mf -for name, mf in mnemo_nocond.items(): +for name, mf in viewitems(mnemo_nocond): mnemo_func_cond[name] = COND_AL, mf @@ -1652,7 +1655,7 @@ def get_mnemo_expr(ir, instr, *args): get_arm_instr_expr = get_mnemo_expr -class arminfo: +class arminfo(object): mode = "arm" # offset @@ -1775,7 +1778,7 @@ class ir_arml(IntermediateRepresentation): for assignment in assignments: assignment = AssignBlock( { - dst:src for (dst, src) in assignment.iteritems() + dst: src for (dst, src) in viewitems(assignment) if dst not in [zf, nf, of, cf] }, assignment.instr @@ -1789,7 +1792,7 @@ class ir_arml(IntermediateRepresentation): for tmp_assignment in irblock: assignment = AssignBlock( { - dst:src for (dst, src) in assignment.iteritems() + dst: src for (dst, src) in viewitems(assignment) if dst not in [zf, nf, of, cf] }, assignment.instr diff --git a/miasm2/arch/mep/arch.py b/miasm2/arch/mep/arch.py index e4d66a63..2266b596 100644 --- a/miasm2/arch/mep/arch.py +++ b/miasm2/arch/mep/arch.py @@ -1,6 +1,7 @@ # Toshiba MeP-c4 - miasm architecture definition # Guillaume Valadon <guillaume@valadon.net> +from builtins import range from miasm2.core.cpu import * from miasm2.core.utils import Disasm_Exception from miasm2.expression.expression import Expr, ExprId, ExprInt, ExprLoc, \ @@ -279,7 +280,7 @@ class instruction_mep(instruction): self.args[num] = ExprInt(off, 32) -class mep_additional_info: +class mep_additional_info(object): """Additional MeP instructions information """ @@ -432,7 +433,7 @@ class mn_mep(cls_mn): o = 0 # the returned value while n: # Get a byte, the offset is adjusted according to the endianness - offset = start / 8 # the offset in bytes + offset = start // 8 # the offset in bytes n_offset = cls.endian_offset(attrib, offset) # the adjusted offset c = cls.getbytes(bitstream, n_offset, 1) if not c: @@ -552,7 +553,7 @@ class mep_arg(m_arg): return arg.name if isinstance(arg.name, str) and arg.name in gpr_names: return None # GV: why? - loc_key = loc_db.get_or_create_name_location(arg.name) + loc_key = loc_db.get_or_create_name_location(arg.name.encode()) return ExprLoc(loc_key, 32) elif isinstance(arg, AstMem): diff --git a/miasm2/arch/mep/regs.py b/miasm2/arch/mep/regs.py index a515e76a..88248823 100644 --- a/miasm2/arch/mep/regs.py +++ b/miasm2/arch/mep/regs.py @@ -1,6 +1,7 @@ # Toshiba MeP-c4 - miasm registers definition # Guillaume Valadon <guillaume@valadon.net> +from builtins import range from miasm2.expression.expression import ExprId from miasm2.core.cpu import reg_info, gen_reg, gen_regs @@ -19,7 +20,7 @@ in_erepeat_init = ExprId("take_jmp_init", 32) # General-purpose registers (R0 to R15) names -gpr_names = ["R%d" % r for r in xrange(13)] # register names +gpr_names = ["R%d" % r for r in range(13)] # register names gpr_names += ["TP", "GP", "SP"] # according to the manual GP does not exist gpr_exprs, gpr_inits, gpr_infos = gen_regs(gpr_names, globals()) # sz=32 bits (default) @@ -53,7 +54,7 @@ RPC = csr_exprs[6] # Repeat Counter. On MeP, it is the special register R6 # Coprocesssor general-purpose registers (C0 to C15) names # Note: a processor extension allows up to 32 coprocessor general-purpose registers -copro_gpr_names = ["C%d" % r for r in xrange(32)] # register names +copro_gpr_names = ["C%d" % r for r in range(32)] # register names copro_gpr_exprs, copro_gpr_inits, copro_gpr_infos = gen_regs(copro_gpr_names, globals()) diff --git a/miasm2/arch/mep/sem.py b/miasm2/arch/mep/sem.py index fb67becd..c346c535 100644 --- a/miasm2/arch/mep/sem.py +++ b/miasm2/arch/mep/sem.py @@ -929,15 +929,15 @@ def div(rn, rm): tmp_rm_inv = rm_inv if rm_inv else i32(1) # Results if only rn, or rm is negative - LO_rn_neg = (~(rn_inv / tmp_rm) + i32(1)) if sign_rn else (~(rn / tmp_rm_inv) + i32(1)) + LO_rn_neg = (~(rn_inv // tmp_rm) + i32(1)) if sign_rn else (~(rn // tmp_rm_inv) + i32(1)) HI_rn_neg = (~(rn_inv % tmp_rm) + i32(1)) if sign_rn else (~(rn % tmp_rm_inv) + i32(1)) # Results if both numbers are positive - LO_pos = rn / tmp_rm if are_both_pos else LO_rn_neg + LO_pos = rn // tmp_rm if are_both_pos else LO_rn_neg HI_pos = rn % tmp_rm if are_both_pos else HI_rn_neg # Results if both numbers are negative - LO_neg = rn_inv / tmp_rm_inv if are_both_neg else LO_pos + LO_neg = rn_inv // tmp_rm_inv if are_both_neg else LO_pos HI_neg = rn_inv % tmp_rm_inv if are_both_neg else HI_pos # Results if rm is equal to zero @@ -954,7 +954,7 @@ def divu(rn, rm): # LO <- Rn / Rm, HI <- Rn % Rm (Unsigned) tmp_rm = rm if rm else i32(1) # used to delay the arithmetic computations - LO = rn / tmp_rm if rm else LO + LO = rn // tmp_rm if rm else LO HI = rn % tmp_rm if rm else HI exception_flags = i32(0) if rm else i32(EXCEPT_DIV_BY_ZERO) diff --git a/miasm2/arch/mips32/arch.py b/miasm2/arch/mips32/arch.py index 75a1aff0..6046b12c 100644 --- a/miasm2/arch/mips32/arch.py +++ b/miasm2/arch/mips32/arch.py @@ -42,7 +42,7 @@ deref_nooff = (LPARENTHESIS + gpregs.parser + RPARENTHESIS).setParseAction(cb_de deref = deref_off | deref_nooff -class additional_info: +class additional_info(object): def __init__(self): self.except_on_instr = False @@ -200,7 +200,7 @@ class mn_mips32(cpu.cls_mn): return 0 o = 0 while n: - offset = start / 8 + offset = start // 8 n_offset = cls.endian_offset(attrib, offset) c = cls.getbytes(bitstream, n_offset, 1) if not c: @@ -265,7 +265,7 @@ class mips32_arg(cpu.m_arg): return arg.name if arg.name in gpregs.str: return None - loc_key = loc_db.get_or_create_name_location(arg.name) + loc_key = loc_db.get_or_create_name_location(arg.name.encode()) return ExprLoc(loc_key, 32) if isinstance(arg, AstOp): args = [self.asm_ast_to_expr(tmp, loc_db) for tmp in arg.args] diff --git a/miasm2/arch/mips32/jit.py b/miasm2/arch/mips32/jit.py index 4abe0cd4..04690a3e 100644 --- a/miasm2/arch/mips32/jit.py +++ b/miasm2/arch/mips32/jit.py @@ -1,3 +1,4 @@ +from builtins import range import logging from miasm2.jitter.jitload import Jitter, named_arguments @@ -109,7 +110,7 @@ class jitter_mips32l(Jitter): @named_arguments def func_args_stdcall(self, n_args): - args = [self.get_arg_n_stdcall(i) for i in xrange(n_args)] + args = [self.get_arg_n_stdcall(i) for i in range(n_args)] ret_ad = self.cpu.RA return ret_ad, args @@ -122,9 +123,9 @@ class jitter_mips32l(Jitter): return True def func_prepare_stdcall(self, ret_addr, *args): - for index in xrange(min(len(args), 4)): + for index in range(min(len(args), 4)): setattr(self.cpu, 'A%d' % index, args[index]) - for index in xrange(4, len(args)): + for index in range(4, len(args)): self.vm.set_mem(self.cpu.SP + 4 * (index - 4), pck32(args[index])) self.cpu.RA = ret_addr diff --git a/miasm2/arch/mips32/regs.py b/miasm2/arch/mips32/regs.py index ddaaff79..d1d14bdc 100644 --- a/miasm2/arch/mips32/regs.py +++ b/miasm2/arch/mips32/regs.py @@ -1,5 +1,6 @@ #-*- coding:utf-8 -*- +from builtins import range from miasm2.expression.expression import ExprId from miasm2.core.cpu import gen_reg, gen_regs @@ -16,19 +17,19 @@ PC_init = ExprId("PC_init", 32) PC_FETCH_init = ExprId("PC_FETCH_init", 32) regs32_str = ["ZERO", 'AT', 'V0', 'V1'] +\ - ['A%d'%i for i in xrange(4)] +\ - ['T%d'%i for i in xrange(8)] +\ - ['S%d'%i for i in xrange(8)] +\ - ['T%d'%i for i in xrange(8, 10)] +\ + ['A%d'%i for i in range(4)] +\ + ['T%d'%i for i in range(8)] +\ + ['S%d'%i for i in range(8)] +\ + ['T%d'%i for i in range(8, 10)] +\ ['K0', 'K1'] +\ ['GP', 'SP', 'FP', 'RA'] regs32_expr = [ExprId(x, 32) for x in regs32_str] ZERO = regs32_expr[0] -regs_flt_str = ['F%d'%i for i in xrange(0x20)] +regs_flt_str = ['F%d'%i for i in range(0x20)] -regs_fcc_str = ['FCC%d'%i for i in xrange(8)] +regs_fcc_str = ['FCC%d'%i for i in range(8)] R_LO = ExprId('R_LO', 32) R_HI = ExprId('R_HI', 32) @@ -37,7 +38,7 @@ R_LO_init = ExprId('R_LO_init', 32) R_HI_init = ExprId('R_HI_init', 32) -cpr0_str = ["CPR0_%d"%x for x in xrange(0x100)] +cpr0_str = ["CPR0_%d"%x for x in range(0x100)] cpr0_str[0] = "INDEX" cpr0_str[16] = "ENTRYLO0" cpr0_str[24] = "ENTRYLO1" diff --git a/miasm2/arch/msp430/arch.py b/miasm2/arch/msp430/arch.py index f0db98f3..fd31f6c4 100644 --- a/miasm2/arch/msp430/arch.py +++ b/miasm2/arch/msp430/arch.py @@ -1,5 +1,7 @@ #-*- coding:utf-8 -*- +from builtins import range + import logging from pyparsing import * from miasm2.expression.expression import * @@ -69,7 +71,7 @@ class msp430_arg(m_arg): index = gpregs.str.index(name) reg = gpregs.expr[index] return reg - loc_key = loc_db.get_or_create_name_location(value.name) + loc_key = loc_db.get_or_create_name_location(value.name.encode()) return ExprLoc(loc_key, 16) if isinstance(value, AstOp): args = [self.asm_ast_to_expr(tmp, loc_db) for tmp in value.args] @@ -86,7 +88,7 @@ class msp430_arg(m_arg): return None -class additional_info: +class additional_info(object): def __init__(self): self.except_on_instr = False @@ -238,7 +240,7 @@ class mn_msp430(cls_mn): if n > bs.getlen() * 8: raise ValueError('not enough bits %r %r' % (n, len(bs.bin) * 8)) while n: - i = start / 8 + i = start // 8 c = cls.getbytes(bs, i) if not c: raise IOError @@ -255,8 +257,8 @@ class mn_msp430(cls_mn): @classmethod def getbytes(cls, bs, offset, l=1): - out = "" - for _ in xrange(l): + out = b"" + for _ in range(l): n_offset = (offset & ~1) + 1 - offset % 2 out += bs.getbytes(n_offset, 1) offset += 1 @@ -266,7 +268,7 @@ class mn_msp430(cls_mn): tmp = super(mn_msp430, self).decoded2bytes(result) out = [] for x in tmp: - o = "" + o = b"" while x: o += x[:2][::-1] x = x[2:] @@ -524,7 +526,7 @@ class msp430_offs(imm_noarg, msp430_arg): def encodeval(self, v): plen = self.parent.l + self.l assert(plen % 8 == 0) - v -= plen / 8 + v -= plen // 8 if v % 2 != 0: return False return v >> 1 diff --git a/miasm2/arch/msp430/regs.py b/miasm2/arch/msp430/regs.py index 11385779..a3e714b2 100644 --- a/miasm2/arch/msp430/regs.py +++ b/miasm2/arch/msp430/regs.py @@ -1,10 +1,11 @@ +from builtins import range from miasm2.expression.expression import * from miasm2.core.cpu import reg_info # GP -regs16_str = ["PC", "SP", "SR"] + ["R%d" % i for i in xrange(3, 16)] +regs16_str = ["PC", "SP", "SR"] + ["R%d" % i for i in range(3, 16)] regs16_expr = [ExprId(x, 16) for x in regs16_str] exception_flags = ExprId('exception_flags', 32) diff --git a/miasm2/arch/msp430/sem.py b/miasm2/arch/msp430/sem.py index e0110d24..b939c224 100644 --- a/miasm2/arch/msp430/sem.py +++ b/miasm2/arch/msp430/sem.py @@ -96,10 +96,10 @@ def mng_autoinc(a, b, size): return e, a, b a_r = a.args[0] - e.append(ExprAssign(a_r, a_r + ExprInt(size / 8, a_r.size))) + e.append(ExprAssign(a_r, a_r + ExprInt(size // 8, a_r.size))) a = ExprMem(a_r, size) if isinstance(b, ExprMem) and a_r in b.arg: - b = ExprMem(b.arg + ExprInt(size / 8, 16), b.size) + b = ExprMem(b.arg + ExprInt(size // 8, 16), b.size) return e, a, b # Mnemonics diff --git a/miasm2/arch/ppc/arch.py b/miasm2/arch/ppc/arch.py index 37acc1c5..e7661371 100644 --- a/miasm2/arch/ppc/arch.py +++ b/miasm2/arch/ppc/arch.py @@ -1,3 +1,4 @@ +from builtins import range import logging from pyparsing import * @@ -40,7 +41,7 @@ class ppc_arg(m_arg): return arg.name if arg.name in gpregs.str: return None - loc_key = loc_db.get_or_create_name_location(arg.name) + loc_key = loc_db.get_or_create_name_location(arg.name.encode()) return ExprLoc(loc_key, 32) if isinstance(arg, AstOp): args = [self.asm_ast_to_expr(tmp, loc_db) for tmp in arg.args] @@ -57,7 +58,7 @@ class ppc_arg(m_arg): return None -class additional_info: +class additional_info(object): def __init__(self): self.except_on_instr = False @@ -227,7 +228,7 @@ class mn_ppc(cls_mn): if n > bs.getlen() * 8: raise ValueError('not enough bits %r %r' % (n, len(bs.bin) * 8)) while n: - offset = start / 8 + offset = start // 8 n_offset = cls.endian_offset(attrib, offset) c = cls.getbytes(bs, n_offset, 1) if not c: @@ -468,7 +469,7 @@ def ppc_bo_bi_to_mnemo(bo, bi, prefer_taken=True, default_taken=True): def ppc_all_bo_bi(): for bo in [0, 2, 4, 8, 10, 12, 16, 18, 20]: - for bi in xrange(4): + for bi in range(4): yield bo, bi class ppc_divert_conditional_branch(bs_divert): diff --git a/miasm2/arch/ppc/jit.py b/miasm2/arch/ppc/jit.py index 14c203a9..8dc4aa99 100644 --- a/miasm2/arch/ppc/jit.py +++ b/miasm2/arch/ppc/jit.py @@ -1,3 +1,4 @@ +from builtins import range from miasm2.jitter.jitload import Jitter, named_arguments from miasm2.core.locationdb import LocationDB from miasm2.arch.ppc.sem import ir_ppc32b @@ -34,7 +35,7 @@ class jitter_ppc32b(Jitter): @named_arguments def func_args_systemv(self, n_args): - args = [self.get_arg_n_systemv(i) for i in xrange(n_args)] + args = [self.get_arg_n_systemv(i) for i in range(n_args)] ret_ad = self.cpu.LR return ret_ad, args @@ -47,9 +48,9 @@ class jitter_ppc32b(Jitter): return True def func_prepare_systemv(self, ret_addr, *args): - for index in xrange(min(len(args), self.max_reg_arg)): + for index in range(min(len(args), self.max_reg_arg)): setattr(self.cpu, 'R%d' % (index + 3), args[index]) - for index in xrange(len(args) - 1, self.max_reg_arg - 1, -1): + for index in range(len(args) - 1, self.max_reg_arg - 1, -1): self.push_uint32_t(args[index]) # reserve room for LR save word and backchain diff --git a/miasm2/arch/ppc/regs.py b/miasm2/arch/ppc/regs.py index 70b49f82..e70afce2 100644 --- a/miasm2/arch/ppc/regs.py +++ b/miasm2/arch/ppc/regs.py @@ -1,4 +1,5 @@ +from builtins import range from miasm2.expression.expression import * from miasm2.core.cpu import gen_reg, gen_regs @@ -14,13 +15,13 @@ SPR_ACCESS_SPR_OFF = 0 SPR_ACCESS_GPR_MASK = 0x0001F000 SPR_ACCESS_GPR_OFF = 12 -gpregs_str = ["R%d" % i for i in xrange(32)] +gpregs_str = ["R%d" % i for i in range(32)] gpregs_expr, gpregs_init, gpregs = gen_regs(gpregs_str, globals(), 32) -crfregs_str = ["CR%d" % i for i in xrange(8)] +crfregs_str = ["CR%d" % i for i in range(8)] crfregs_expr, crfregs_init, crfregs = gen_regs(crfregs_str, globals(), 4) -crfbitregs_str = ["CR%d_%s" % (i, flag) for i in xrange(8) +crfbitregs_str = ["CR%d_%s" % (i, flag) for i in range(8) for flag in ['LT', 'GT', 'EQ', 'SO'] ] crfbitregs_expr, crfbitregs_init, crfbitregs = gen_regs(crfbitregs_str, globals(), 1) @@ -38,8 +39,8 @@ otherregs_str = ["PC", "CTR", "LR" ] otherregs_expr, otherregs_init, otherregs = gen_regs(otherregs_str, globals(), 32) -superregs_str = (["SPRG%d" % i for i in xrange(4)] + - ["SRR%d" % i for i in xrange(2)] + +superregs_str = (["SPRG%d" % i for i in range(4)] + + ["SRR%d" % i for i in range(2)] + ["DAR", "DSISR", "MSR", "PIR", "PVR", "DEC", "TBL", "TBU"]) superregs_expr, superregs_init, superregs = gen_regs(superregs_str, diff --git a/miasm2/arch/ppc/sem.py b/miasm2/arch/ppc/sem.py index 558450b2..ef44ffe3 100644 --- a/miasm2/arch/ppc/sem.py +++ b/miasm2/arch/ppc/sem.py @@ -1,3 +1,6 @@ +from __future__ import print_function +from builtins import range + import miasm2.expression.expression as expr from miasm2.ir.ir import AssignBlock, IntermediateRepresentation, IRBlock from miasm2.arch.ppc.arch import mn_ppc @@ -15,7 +18,7 @@ spr_dict = { crf_dict = dict((ExprId("CR%d" % i, 4), dict( (bit, ExprId("CR%d_%s" % (i, bit), 1)) for bit in ['LT', 'GT', 'EQ', 'SO' ] )) - for i in xrange(8) ) + for i in range(8) ) ctx = { 'crf_dict': crf_dict, @@ -112,7 +115,7 @@ def mn_do_cntlzw(ir, instr, ra, rs): def crbit_to_reg(bit): bit = bit.arg.arg - crid = bit / 4 + crid = bit // 4 bitname = [ 'LT', 'GT', 'EQ', 'SO' ][bit % 4] return all_regs_ids_byname["CR%d_%s" % (crid, bitname)] @@ -217,8 +220,8 @@ def mn_do_exts(ir, instr, ra, rs): return ret, [] def byte_swap(expr): - nbytes = expr.size / 8 - bytes = [ expr[i*8:i*8+8] for i in xrange(nbytes - 1, -1, -1) ] + nbytes = expr.size // 8 + bytes = [ expr[i*8:i*8+8] for i in range(nbytes - 1, -1, -1) ] return ExprCompose(bytes) def mn_do_load(ir, instr, arg1, arg2, arg3=None): @@ -325,7 +328,7 @@ def mn_do_mcrxr(ir, instr, crfd): def mn_do_mfcr(ir, instr, rd): return ([ ExprAssign(rd, ExprCompose(*[ all_regs_ids_byname["CR%d_%s" % (i, b)] - for i in xrange(7, -1, -1) + for i in range(7, -1, -1) for b in ['SO', 'EQ', 'GT', 'LT']]))], []) @@ -350,7 +353,7 @@ def mn_mfspr(ir, instr, arg1, arg2): def mn_mtcrf(ir, instr, crm, rs): ret = [] - for i in xrange(8): + for i in range(8): if crm.arg.arg & (1 << (7 - i)): j = (28 - 4 * i) + 3 for b in ['LT', 'GT', 'EQ', 'SO']: @@ -361,7 +364,7 @@ def mn_mtcrf(ir, instr, crm, rs): return ret, [] def mn_mtmsr(ir, instr, rs): - print "%08x: MSR assigned" % instr.offset + print("%08x: MSR assigned" % instr.offset) return [ ExprAssign(MSR, rs) ], [] def mn_mtspr(ir, instr, arg1, arg2): @@ -746,7 +749,7 @@ def mn_do_cond_branch(ir, instr, dest): return ret, [] def mn_do_nop_warn(ir, instr, *args): - print "Warning, instruction %s implemented as NOP" % instr + print("Warning, instruction %s implemented as NOP" % instr) return [], [] @sbuild.parse diff --git a/miasm2/arch/sh4/arch.py b/miasm2/arch/sh4/arch.py index 88d734a3..c7ff6ab0 100644 --- a/miasm2/arch/sh4/arch.py +++ b/miasm2/arch/sh4/arch.py @@ -1,5 +1,8 @@ #-*- coding:utf-8 -*- +from __future__ import print_function +from builtins import range + from pyparsing import * from miasm2.core.cpu import * from miasm2.expression.expression import * @@ -102,7 +105,7 @@ class sh4_arg(m_arg): return arg.name if arg.name in gpregs.str: return None - loc_key = loc_db.get_or_create_name_location(arg.name) + loc_key = loc_db.get_or_create_name_location(arg.name.encode()) return ExprLoc(loc_key, 32) if isinstance(arg, AstOp): args = [self.asm_ast_to_expr(tmp, loc_db) for tmp in arg.args] @@ -235,7 +238,7 @@ class sh4_dgpreg_imm(sh4_dgpreg): p = self.parent r = gpregs.expr[v] s = self.sz - d = ExprInt(p.disp.value * s / 8, 32) + d = ExprInt((p.disp.value * s) // 8, 32) e = ExprMem(r + d, s) self.expr = e return True @@ -258,7 +261,7 @@ class sh4_dgpreg_imm(sh4_dgpreg): if not isinstance(res[jrb], ExprInt): return False d = int(res[jrb]) - p.disp.value = d / (s / 8) + p.disp.value = d // (s // 8) if not res[jra] in gpregs.expr: return False v = gpregs.expr.index(res[jra]) @@ -301,7 +304,7 @@ class sh4_dpc16imm(sh4_dgpreg): return True def calcdisp(self, v): - v = (int(v) - 4) / 2 + v = (int(v) - 4) // 2 if not 0 < v <= 0xff: return None return v @@ -324,7 +327,7 @@ class sh4_dgbrimm8(sh4_dgpreg): def decode(self, v): s = self.sz - self.expr = ExprMem(GBR + ExprInt(v * s / 8, 32), s) + self.expr = ExprMem(GBR + ExprInt((v * s) // 8, 32), s) return True def encode(self): @@ -338,7 +341,7 @@ class sh4_dgbrimm8(sh4_dgpreg): return False if not isinstance(res[jra], ExprInt): return False - self.value = int(res[jra]) / (s / 8) + self.value = int(res[jra]) // (s // 8) return True @@ -351,7 +354,7 @@ class sh4_dpc32imm(sh4_dpc16imm): return True def calcdisp(self, v): - v = (int(v) - 4) / 4 + v = (int(v) - 4) // 4 if not 0 < v <= 0xff: return None return v @@ -383,13 +386,13 @@ class sh4_pc32imm(sh4_arg): return False if not isinstance(res[jra], ExprInt): return False - v = (int(res[jra]) - 4) / 4 + v = (int(res[jra]) - 4) // 4 if v is None: return False self.value = v return True -class additional_info: +class additional_info(object): def __init__(self): self.except_on_instr = False @@ -423,8 +426,10 @@ class instruction_sh4(instruction): elif ptr.op == "postinc": s = '%s+' % ptr.args[0] else: - s = ','.join([str(x).replace('(', '').replace(')', '') - for x in ptr.args]) + s = ','.join( + str(x).replace('(', '').replace(')', '') + for x in ptr.args + ) s = "(%s)"%s s = "@%s" % s elif isinstance(ptr, ExprId): @@ -473,11 +478,11 @@ class instruction_sh4(instruction): log.debug('dyn dst %r', e) return off = e.arg - (self.offset + 4 + self.l) - print hex(off) + print(hex(off)) if int(off % 4): raise ValueError('strange offset! %r' % off) self.args[0] = ExprInt(off, 32) - print 'final', self.args[0] + print('final', self.args[0]) def get_args_expr(self): args = [a for a in self.args] @@ -510,7 +515,7 @@ class mn_sh4(cls_mn): if n > bs.getlen() * 8: raise ValueError('not enough bits %r %r' % (n, len(bs.bin) * 8)) while n: - i = start / 8 + i = start // 8 c = cls.getbytes(bs, i) if not c: raise IOError @@ -527,8 +532,8 @@ class mn_sh4(cls_mn): @classmethod def getbytes(cls, bs, offset, l=1): - out = "" - for _ in xrange(l): + out = b"" + for _ in range(l): n_offset = (offset & ~1) + 1 - offset % 2 out += bs.getbytes(n_offset, 1) offset += 1 diff --git a/miasm2/arch/sh4/regs.py b/miasm2/arch/sh4/regs.py index 148e74ba..c294eb8c 100644 --- a/miasm2/arch/sh4/regs.py +++ b/miasm2/arch/sh4/regs.py @@ -1,20 +1,21 @@ +from builtins import range from miasm2.expression.expression import * from miasm2.core.cpu import reg_info, gen_reg # GP -gpregs_str = ['R%d' % r for r in xrange(0x10)] +gpregs_str = ['R%d' % r for r in range(0x10)] gpregs_expr = [ExprId(x, 32) for x in gpregs_str] gpregs = reg_info(gpregs_str, gpregs_expr) -bgpregs_str = ['R%d_BANK' % r for r in xrange(0x8)] +bgpregs_str = ['R%d_BANK' % r for r in range(0x8)] bgpregs_expr = [ExprId(x, 32) for x in bgpregs_str] bgpregs = reg_info(bgpregs_str, bgpregs_expr) -fregs_str = ['FR%d' % r for r in xrange(0x10)] +fregs_str = ['FR%d' % r for r in range(0x10)] fregs_expr = [ExprId(x, 32) for x in fregs_str] fregs = reg_info(fregs_str, fregs_expr) -dregs_str = ['DR%d' % r for r in xrange(0x8)] +dregs_str = ['DR%d' % r for r in range(0x8)] dregs_expr = [ExprId(x, 32) for x in dregs_str] dregs = reg_info(dregs_str, dregs_expr) diff --git a/miasm2/arch/x86/arch.py b/miasm2/arch/x86/arch.py index b625647e..7a2c371c 100644 --- a/miasm2/arch/x86/arch.py +++ b/miasm2/arch/x86/arch.py @@ -1,6 +1,12 @@ #-*- coding:utf-8 -*- +from __future__ import print_function +from builtins import range import re + +from future.utils import viewitems + +from miasm2.core.utils import int_to_byte from miasm2.expression.expression import * from pyparsing import * from miasm2.core.cpu import * @@ -123,7 +129,7 @@ replace_regs = {16: replace_regs16, segm2enc = {CS: 1, SS: 2, DS: 3, ES: 4, FS: 5, GS: 6} -enc2segm = dict([(x[1], x[0]) for x in segm2enc.items()]) +enc2segm = dict((value, key) for key, value in viewitems(segm2enc)) segm_info = reg_info_dct(enc2segm) @@ -215,7 +221,7 @@ XMMWORD = Literal('XMMWORD') MEMPREFIX2SIZE = {'BYTE': 8, 'WORD': 16, 'DWORD': 32, 'QWORD': 64, 'TBYTE': 80, 'XMMWORD': 128} -SIZE2MEMPREFIX = dict((x[1], x[0]) for x in MEMPREFIX2SIZE.items()) +SIZE2MEMPREFIX = dict((value, key) for key, value in viewitems(MEMPREFIX2SIZE)) def cb_deref_mem(tokens): if len(tokens) == 2: @@ -272,7 +278,7 @@ class x86_arg(m_arg): if value.name in ["FAR"]: return None - loc_key = loc_db.get_or_create_name_location(value.name) + loc_key = loc_db.get_or_create_name_location(value.name.encode()) return ExprLoc(loc_key, size_hint) if isinstance(value, AstOp): # First pass to retrieve fixed_size @@ -430,13 +436,13 @@ repeat_mn = ["INS", "OUTS", ] -class group: +class group(object): def __init__(self): self.value = None -class additional_info: +class additional_info(object): def __init__(self): self.except_on_instr = False @@ -446,7 +452,7 @@ class additional_info: self.stk = False self.v_opmode = None self.v_admode = None - self.prefixed = '' + self.prefixed = b'' class instruction_x86(instruction): @@ -537,7 +543,7 @@ class instruction_x86(instruction): self.additional_info.v_opmode = c.v_opmode() self.additional_info.v_admode = c.v_admode() self.additional_info.prefix = c.prefix - self.additional_info.prefixed = getattr(c, "prefixed", "") + self.additional_info.prefixed = getattr(c, "prefixed", b"") def __str__(self): return self.to_string() @@ -547,13 +553,13 @@ class instruction_x86(instruction): if self.additional_info.g1.value & 1: o = "LOCK %s" % o if self.additional_info.g1.value & 2: - if getattr(self.additional_info.prefixed, 'default', "") != "\xF2": + if getattr(self.additional_info.prefixed, 'default', b"") != b"\xF2": o = "REPNE %s" % o if self.additional_info.g1.value & 8: - if getattr(self.additional_info.prefixed, 'default', "") != "\xF3": + if getattr(self.additional_info.prefixed, 'default', b"") != b"\xF3": o = "REP %s" % o elif self.additional_info.g1.value & 4: - if getattr(self.additional_info.prefixed, 'default', "") != "\xF3": + if getattr(self.additional_info.prefixed, 'default', b"") != b"\xF3": o = "REPE %s" % o return o @@ -650,7 +656,7 @@ class mn_x86(cls_mn): info.g2.value = self.g2.value info.stk = hasattr(self, 'stk') info.v_opmode = self.v_opmode() - info.prefixed = "" + info.prefixed = b"" if hasattr(self, 'prefixed'): info.prefixed = self.prefixed.default return info @@ -705,40 +711,40 @@ class mn_x86(cls_mn): 'rex_r': 0, 'rex_x': 0, 'rex_b': 0, - 'prefix': "", - 'prefixed': "", + 'prefix': b"", + 'prefixed': b"", } while True: c = v.getbytes(offset) - if c == '\x66': + if c == b'\x66': pre_dis_info['opmode'] = 1 - elif c == '\x67': + elif c == b'\x67': pre_dis_info['admode'] = 1 - elif c == '\xf0': + elif c == b'\xf0': pre_dis_info['g1'] = 1 - elif c == '\xf2': + elif c == b'\xf2': pre_dis_info['g1'] = 2 - elif c == '\xf3': + elif c == b'\xf3': pre_dis_info['g1'] = 12 - elif c == '\x2e': + elif c == b'\x2e': pre_dis_info['g2'] = 1 - elif c == '\x36': + elif c == b'\x36': pre_dis_info['g2'] = 2 - elif c == '\x3e': + elif c == b'\x3e': pre_dis_info['g2'] = 3 - elif c == '\x26': + elif c == b'\x26': pre_dis_info['g2'] = 4 - elif c == '\x64': + elif c == b'\x64': pre_dis_info['g2'] = 5 - elif c == '\x65': + elif c == b'\x65': pre_dis_info['g2'] = 6 else: break pre_dis_info['prefix'] += c offset += 1 - if mode == 64 and c in '@ABCDEFGHIJKLMNO': + if mode == 64 and c in b'@ABCDEFGHIJKLMNO': x = ord(c) pre_dis_info['rex_p'] = 1 pre_dis_info['rex_w'] = (x >> 3) & 1 @@ -746,7 +752,7 @@ class mn_x86(cls_mn): pre_dis_info['rex_x'] = (x >> 1) & 1 pre_dis_info['rex_b'] = (x >> 0) & 1 offset += 1 - elif pre_dis_info.get('g1', None) == 12 and c in ['\xa6', '\xa7', '\xae', '\xaf']: + elif pre_dis_info.get('g1', None) == 12 and c in [b'\xa6', b'\xa7', b'\xae', b'\xaf']: pre_dis_info['g1'] = 4 return pre_dis_info, v, mode, offset, offset - offset_o @@ -793,14 +799,14 @@ class mn_x86(cls_mn): def add_pre_dis_info(self, pre_dis_info=None): if pre_dis_info is None: return True - if hasattr(self, "prefixed") and self.prefixed.default == "\x66": + if hasattr(self, "prefixed") and self.prefixed.default == b"\x66": pre_dis_info['opmode'] = 0 self.opmode = pre_dis_info['opmode'] self.admode = pre_dis_info['admode'] if hasattr(self, 'no_xmm_pref') and\ pre_dis_info['prefix'] and\ - pre_dis_info['prefix'][-1] in '\x66\xf2\xf3': + pre_dis_info['prefix'][-1] in b'\x66\xf2\xf3': return False if (hasattr(self, "prefixed") and not pre_dis_info['prefix'].endswith(self.prefixed.default)): @@ -831,7 +837,7 @@ class mn_x86(cls_mn): def gen_prefix(self): - v = "" + v = b"" rex = 0x40 if self.g1.value is None: self.g1.value = 0 @@ -847,36 +853,40 @@ class mn_x86(cls_mn): if self.rex_b.value: rex |= 0x1 if rex != 0x40 or self.rex_p.value == 1: - v = chr(rex) + v + v = int_to_byte(rex) + v if hasattr(self, 'no_rex'): return None - - if hasattr(self, 'prefixed'): v = self.prefixed.default + v if self.g1.value & 1: - v = "\xf0" + v + v = b"\xf0" + v if self.g1.value & 2: if hasattr(self, 'no_xmm_pref'): return None - v = "\xf2" + v + v = b"\xf2" + v if self.g1.value & 12: if hasattr(self, 'no_xmm_pref'): return None - v = "\xf3" + v + v = b"\xf3" + v if self.g2.value: - v = {1: '\x2e', 2: '\x36', 3: '\x3e', 4: - '\x26', 5: '\x64', 6: '\x65'}[self.g2.value] + v + v = { + 1: b'\x2e', + 2: b'\x36', + 3: b'\x3e', + 4: b'\x26', + 5: b'\x64', + 6: b'\x65' + }[self.g2.value] + v # mode prefix if hasattr(self, "admode") and self.admode: - v = "\x67" + v + v = b"\x67" + v if hasattr(self, "opmode") and self.opmode: if hasattr(self, 'no_xmm_pref'): return None - v = "\x66" + v + v = b"\x66" + v return v def encodefields(self, decoded): @@ -1436,25 +1446,25 @@ def gen_modrm_form(): sib_u32 = [{f_isad: True} for i in range(0x100)] sib_u64 = [] - for rex_x in xrange(2): + for rex_x in range(2): o = [] - for rex_b in xrange(2): + for rex_b in range(2): x = [{f_isad: True} for i in range(0x100)] o.append(x) sib_u64.append(o) sib_u64_ebp = [] - for rex_x in xrange(2): + for rex_x in range(2): o = [] - for rex_b in xrange(2): + for rex_b in range(2): x = [{f_isad: True} for i in range(0x100)] o.append(x) sib_u64_ebp.append(o) sib_64_s08_ebp = [] - for rex_x in xrange(2): + for rex_x in range(2): o = [] - for rex_b in xrange(2): + for rex_b in range(2): x = [{f_isad: True} for i in range(0x100)] o.append(x) sib_64_s08_ebp.append(o) @@ -1479,17 +1489,17 @@ def gen_modrm_form(): elif sib_rez == sib_u32: sib_rez[index][f_imm] = f_u32 elif sib_rez == sib_u64_ebp: - for rex_b in xrange(2): - for rex_x in xrange(2): + for rex_b in range(2): + for rex_x in range(2): sib_rez[rex_x][rex_b][index][f_imm] = f_u32 sib_rez[rex_x][rex_b][index][ebp + 8 * rex_b] = 1 elif sib_rez == sib_u64: - for rex_b in xrange(2): - for rex_x in xrange(2): + for rex_b in range(2): + for rex_x in range(2): sib_rez[rex_x][rex_b][index][f_imm] = f_u32 elif sib_rez == sib_64_s08_ebp: - for rex_b in xrange(2): - for rex_x in xrange(2): + for rex_b in range(2): + for rex_x in range(2): sib_rez[rex_x][rex_b][index][f_imm] = f_s08 sib_rez[rex_x][rex_b][index][ebp + 8 * rex_b] = 1 @@ -1503,17 +1513,17 @@ def gen_modrm_form(): elif sib_rez == sib_u32: sib_rez[index][b] = 1 elif sib_rez == sib_u64_ebp: - for rex_b in xrange(2): - for rex_x in xrange(2): + for rex_b in range(2): + for rex_x in range(2): sib_rez[rex_x][rex_b][index][b + 8 * rex_b] = 1 sib_rez[rex_x][rex_b][index][f_imm] = f_u32 elif sib_rez == sib_u64: - for rex_b in xrange(2): - for rex_x in xrange(2): + for rex_b in range(2): + for rex_x in range(2): sib_rez[rex_x][rex_b][index][b + 8 * rex_b] = 1 elif sib_rez == sib_64_s08_ebp: - for rex_b in xrange(2): - for rex_x in xrange(2): + for rex_b in range(2): + for rex_x in range(2): sib_rez[rex_x][rex_b][index][f_imm] = f_s08 sib_rez[rex_x][rex_b][index][b + 8 * rex_b] = 1 @@ -1526,8 +1536,8 @@ def gen_modrm_form(): sib_rez[index][tmp] = 0 # 1 << ss sib_rez[index][tmp] += 1 << ss else: - for rex_b in xrange(2): - for rex_x in xrange(2): + for rex_b in range(2): + for rex_x in range(2): tmp = i + 8 * rex_x if i == 0b100 and rex_x == 0: continue @@ -1649,18 +1659,16 @@ def gen_modrm_form(): 32: defaultdict(list), 64: defaultdict(list), } - for size, db_afs in byte2modrm.items(): + for size, db_afs in viewitems(byte2modrm): for i, modrm in enumerate(db_afs): if not isinstance(modrm, list): - modrm = modrm.items() - modrm.sort() - modrm = tuple(modrm) + # We only need sort for determinism + modrm = tuple(sorted(viewitems(modrm), key=str)) modrm2byte[size][modrm].append(i) continue for j, modrm_f in enumerate(modrm): - modrm_f = modrm_f.items() - modrm_f.sort() - modrm_f = tuple(modrm_f) + # We only need sort for determinism + modrm_f = tuple(sorted(viewitems(modrm_f), key=str)) modrm2byte[size][modrm_f].append((i, j)) return byte2modrm, modrm2byte @@ -1870,7 +1878,7 @@ def expr2modrm(expr, parent, w8, sx=0, xmm=0, mm=0, bnd=0): def modrm2expr(modrm, parent, w8, sx=0, xmm=0, mm=0, bnd=0): o = [] if not modrm[f_isad]: - modrm_k = [x[0] for x in modrm.iteritems() if x[1] == 1] + modrm_k = [key for key, value in viewitems(modrm) if value == 1] if len(modrm_k) != 1: raise ValueError('strange reg encoding %r' % modrm) modrm_k = modrm_k[0] @@ -1895,8 +1903,8 @@ def modrm2expr(modrm, parent, w8, sx=0, xmm=0, mm=0, bnd=0): return expr admode = parent.v_admode() opmode = parent.v_opmode() - for modrm_k, scale in modrm.items(): - if isinstance(modrm_k, (int, long)): + for modrm_k, scale in viewitems(modrm): + if isinstance(modrm_k, int): expr = size2gpregs[admode].expr[modrm_k] if scale != 1: expr = ExprInt(scale, admode) * expr @@ -1965,9 +1973,9 @@ class x86_rm_arg(x86_arg): def gen_cand(self, v_cand, admode): if not admode in modrm2byte: # XXX TODO: 64bit - raise StopIteration + return if not v_cand: - raise StopIteration + return p = self.parent o_rex_x = p.rex_x.value @@ -1995,9 +2003,8 @@ class x86_rm_arg(x86_arg): v[f_imm] = size vo = v - v = v.items() - v.sort() - v = tuple(v) + # We only need sort for determinism + v = tuple(sorted(viewitems(v), key=str)) admode = 64 if p.mode == 64 else admode if not v in modrm2byte[admode]: continue @@ -2047,11 +2054,11 @@ class x86_rm_arg(x86_arg): yield True - raise StopIteration + return def encode(self): if isinstance(self.expr, ExprInt): - raise StopIteration + return p = self.parent admode = p.v_admode() mode = self.expr.size @@ -2091,11 +2098,11 @@ class x86_rm_mem_far(x86_rm_arg): def encode(self): if not (isinstance(self.expr, m2_expr.ExprOp) and self.expr.op == 'far'): - raise StopIteration + return expr = self.expr.args[0] if isinstance(expr, ExprInt): - raise StopIteration + return p = self.parent admode = p.v_admode() mode = expr.size @@ -2115,7 +2122,7 @@ class x86_rm_w8(x86_rm_arg): def encode(self): if isinstance(self.expr, ExprInt): - raise StopIteration + return p = self.parent if p.w8.value is None: if self.expr.size == 8: @@ -2140,7 +2147,7 @@ class x86_rm_sx(x86_rm_arg): def encode(self): if isinstance(self.expr, ExprInt): - raise StopIteration + return p = self.parent if p.w8.value is None: if self.expr.size == 8: @@ -2164,7 +2171,7 @@ class x86_rm_sxd(x86_rm_arg): def encode(self): if isinstance(self.expr, ExprInt): - raise StopIteration + return p = self.parent v_cand, segm, ok = expr2modrm(self.expr, p, 1, 2) if segm: @@ -2195,10 +2202,10 @@ class x86_rm_sd(x86_rm_arg): def encode(self): if isinstance(self.expr, ExprInt): - raise StopIteration + return p = self.parent if not self.expr.size in [32, 64]: - raise StopIteration + return self.set_s_value(0) v_cand, segm, ok = expr2modrm(self.expr, p, 1) for x in self.gen_cand(v_cand, p.v_admode()): @@ -2214,7 +2221,7 @@ class x86_rm_wd(x86_rm_sd): def encode(self): if isinstance(self.expr, ExprInt): - raise StopIteration + return p = self.parent p.wd.value = 0 v_cand, segm, ok = expr2modrm(self.expr, p, 1) @@ -2237,7 +2244,7 @@ class x86_rm_08(x86_rm_arg): def encode(self): if isinstance(self.expr, ExprInt): - raise StopIteration + return p = self.parent v_cand, segm, ok = expr2modrm(self.expr, p, 0, 0, 0, 0) for x in self.gen_cand(v_cand, p.v_admode()): @@ -2257,7 +2264,7 @@ class x86_rm_reg_m08(x86_rm_arg): def encode(self): if isinstance(self.expr, ExprInt): - raise StopIteration + return p = self.parent if isinstance(self.expr, ExprMem): expr = ExprMem(self.expr.ptr, 32) @@ -2284,7 +2291,7 @@ class x86_rm_m64(x86_rm_arg): def encode(self): if isinstance(self.expr, ExprInt): - raise StopIteration + return p = self.parent v_cand, segm, ok = expr2modrm(self.expr, p, 0, 0, 0, 1) for x in self.gen_cand(v_cand, p.v_admode()): @@ -2296,9 +2303,9 @@ class x86_rm_m80(x86_rm_m64): def encode(self): if isinstance(self.expr, ExprInt): - raise StopIteration + return if not isinstance(self.expr, ExprMem) or self.expr.size != self.msize: - raise StopIteration + return p = self.parent mode = p.mode if mode == 64: @@ -2320,7 +2327,7 @@ class x86_rm_m08(x86_rm_arg): def encode(self): if self.expr.size != 8: - raise StopIteration + return p = self.parent mode = p.mode v_cand, segm, ok = expr2modrm(self.expr, p, 0) @@ -2354,9 +2361,9 @@ class x86_rm_mm(x86_rm_m80): def encode(self): expr = self.expr if isinstance(expr, ExprInt): - raise StopIteration + return if isinstance(expr, ExprMem) and expr.size != self.msize: - raise StopIteration + return p = self.parent mode = p.mode if mode == 64: @@ -2458,7 +2465,7 @@ class x86_rm_reg_noarg(object): self.parent.w8.value = 0 return start, stop try: - result, start, stop = self.parser.scanString(text).next() + result, start, stop = next(self.parser.scanString(text)) except StopIteration: return None, None expr = self.asm_ast_to_expr(result[0], loc_db) @@ -2753,7 +2760,7 @@ class bs_cond_imm(bs_cond_scale, x86_arg): expr, start, stop = parser_result[self.parser] else: try: - expr, start, stop = self.parser.scanString(text).next() + expr, start, stop = next(self.parser.scanString(text)) except StopIteration: expr = None self.expr = expr @@ -2788,7 +2795,7 @@ class bs_cond_imm(bs_cond_scale, x86_arg): def encode(self): if not isinstance(self.expr, ExprInt): - raise StopIteration + return arg0_expr = self.parent.args[0].expr self.parent.rex_w.value = 0 # special case for push @@ -2800,10 +2807,10 @@ class bs_cond_imm(bs_cond_scale, x86_arg): self.l = l mask = ((1 << self.l) - 1) if v != sign_ext(v & mask, self.l, l): - raise StopIteration + return self.value = swap_uint(self.l, v & ((1 << self.l) - 1)) yield True - raise StopIteration + return # assume 2 args; use first arg to guess op size if arg0_expr.size == 64: @@ -2813,7 +2820,7 @@ class bs_cond_imm(bs_cond_scale, x86_arg): v = int(self.expr) if arg0_expr.size == 8: if not hasattr(self.parent, 'w8'): - raise StopIteration + return self.parent.w8.value = 0 l = 8 if hasattr(self.parent, 'se'): @@ -2838,7 +2845,7 @@ class bs_cond_imm(bs_cond_scale, x86_arg): mask = ((1 << self.l) - 1) if v != sign_ext(v & mask, self.l, l): - raise StopIteration + return self.value = swap_uint(self.l, v & ((1 << self.l) - 1)) yield True @@ -2880,7 +2887,7 @@ class bs_rel_off(bs_cond_imm): expr, start, stop = parser_result[self.parser] else: try: - expr, start, stop = self.parser.scanString(text).next() + expr, start, stop = next(self.parser.scanString(text)) except StopIteration: expr = None self.expr = expr @@ -2901,7 +2908,7 @@ class bs_rel_off(bs_cond_imm): def encode(self): if not isinstance(self.expr, ExprInt): - raise StopIteration + return arg0_expr = self.parent.args[0].expr if self.l == 0: l = self.parent.v_opmode() @@ -2911,14 +2918,14 @@ class bs_rel_off(bs_cond_imm): parent_len = len(prefix) * 8 + self.parent.l + self.l assert(parent_len % 8 == 0) - v = int(self.expr.arg - parent_len/8) + v = int(self.expr.arg) - parent_len // 8 if prefix is None: - raise StopIteration + return mask = ((1 << self.l) - 1) if self.l > l: - raise StopIteration + return if v != sign_ext(v & mask, self.l, l): - raise StopIteration + return self.value = swap_uint(self.l, v & ((1 << self.l) - 1)) yield True @@ -2939,7 +2946,7 @@ class bs_s08(bs_rel_off): def encode(self): if not isinstance(self.expr, ExprInt): - raise StopIteration + return arg0_expr = self.parent.args[0].expr if self.l != 0: l = self.l @@ -2950,9 +2957,9 @@ class bs_s08(bs_rel_off): v = int(self.expr) mask = ((1 << self.l) - 1) if self.l > l: - raise StopIteration + return if v != sign_ext(v & mask, self.l, l): - raise StopIteration + return self.value = swap_uint(self.l, v & ((1 << self.l) - 1)) yield True @@ -2983,12 +2990,12 @@ class bs_moff(bsi): def encode(self): if not hasattr(self.parent, "mseg"): - raise StopIteration + return m = self.parent.mseg.expr if not (isinstance(m, ExprOp) and m.op == 'segm'): - raise StopIteration + return if not isinstance(m.args[1], ExprInt): - raise StopIteration + return l = self.parent.v_opmode() if l == 16: self.l = 16 @@ -2997,7 +3004,7 @@ class bs_moff(bsi): v = int(m.args[1]) mask = ((1 << self.l) - 1) if v != sign_ext(v & mask, self.l, l): - raise StopIteration + return self.value = swap_uint(self.l, v & ((1 << self.l) - 1)) yield True @@ -3027,7 +3034,7 @@ class bs_movoff(x86_arg): return None, None return start, stop try: - v, start, stop = self.parser.scanString(text).next() + v, start, stop = next(self.parser.scanString(text)) except StopIteration: return None, None if not isinstance(e, ExprMem): @@ -3051,12 +3058,12 @@ class bs_movoff(x86_arg): def encode(self): p = self.parent if not isinstance(self.expr, ExprMem) or not isinstance(self.expr.ptr, ExprInt): - raise StopIteration + return self.l = p.v_admode() v = int(self.expr.ptr) mask = ((1 << self.l) - 1) if v != mask & v: - raise StopIteration + return self.value = swap_uint(self.l, v & ((1 << self.l) - 1)) yield True @@ -3092,7 +3099,7 @@ class bs_msegoff(x86_arg): return None, None return start, stop try: - v, start, stop = self.parser.scanString(text).next() + v, start, stop = next(self.parser.scanString(text)) except StopIteration: return None, None self.expr = v[0] @@ -3103,16 +3110,16 @@ class bs_msegoff(x86_arg): def encode(self): if not (isinstance(self.expr, ExprOp) and self.expr.op == 'segm'): - raise StopIteration + return if not isinstance(self.expr.args[0], ExprInt): - raise StopIteration + return if not isinstance(self.expr.args[1], ExprInt): - raise StopIteration + return l = self.parent.v_opmode() v = int(self.expr.args[0]) mask = ((1 << self.l) - 1) if v != sign_ext(v & mask, self.l, l): - raise StopIteration + return self.value = swap_uint(self.l, v & ((1 << self.l) - 1)) yield True @@ -3148,9 +3155,9 @@ sxd = bs(l=0, fname="sx") xmmreg = bs(l=0, fname="xmmreg") mmreg = bs(l=0, fname="mmreg") -pref_f2 = bs(l=0, fname="prefixed", default="\xf2") -pref_f3 = bs(l=0, fname="prefixed", default="\xf3") -pref_66 = bs(l=0, fname="prefixed", default="\x66") +pref_f2 = bs(l=0, fname="prefixed", default=b"\xf2") +pref_f3 = bs(l=0, fname="prefixed", default=b"\xf3") +pref_66 = bs(l=0, fname="prefixed", default=b"\x66") no_xmm_pref = bs(l=0, fname="no_xmm_pref") no_rex = bs(l=0, fname="no_rex") @@ -3186,7 +3193,7 @@ wd = bs(l=1, fname="wd") stk = bs(l=0, fname="stk") -class field_size: +class field_size(object): prio = default_prio def __init__(self, d=None): @@ -3287,7 +3294,7 @@ rm_arg_bnd_m128 = bs(l=0, cls=(x86_rm_bnd_m128,), fname='rmarg') rm_arg_bnd_reg = bs(l=0, cls=(x86_rm_bnd_reg,), fname='rmarg') -swapargs = bs_swapargs(l=1, fname="swap", mn_mod=range(1 << 1)) +swapargs = bs_swapargs(l=1, fname="swap", mn_mod=list(range(1 << 1))) class bs_op_mode(bsi): @@ -4626,5 +4633,5 @@ mod reg r/m def print_size(e): - print e, e.size + print(e, e.size) return e diff --git a/miasm2/arch/x86/jit.py b/miasm2/arch/x86/jit.py index f0a9875e..14418902 100644 --- a/miasm2/arch/x86/jit.py +++ b/miasm2/arch/x86/jit.py @@ -1,3 +1,4 @@ +from builtins import range import logging from miasm2.jitter.jitload import Jitter, named_arguments @@ -53,12 +54,12 @@ class jitter_x86_16(Jitter): return self.orig_irbloc_fix_regs_for_mode(irblock, 64) def push_uint16_t(self, value): - self.cpu.SP -= self.ir_arch.sp.size / 8 + self.cpu.SP -= self.ir_arch.sp.size // 8 self.vm.set_u16(self.cpu.SP, value) def pop_uint16_t(self): value = self.vm.get_u16(self.cpu.SP) - self.cpu.SP += self.ir_arch.sp.size / 8 + self.cpu.SP += self.ir_arch.sp.size // 8 return value def get_stack_arg(self, index): @@ -86,21 +87,21 @@ class jitter_x86_32(Jitter): return self.orig_irbloc_fix_regs_for_mode(irblock, 64) def push_uint16_t(self, value): - self.cpu.ESP -= self.ir_arch.sp.size / 8 + self.cpu.ESP -= self.ir_arch.sp.size // 8 self.vm.set_u16(self.cpu.ESP, value) def pop_uint16_t(self): value = self.vm.get_u16(self.cpu.ESP) - self.cpu.ESP += self.ir_arch.sp.size / 8 + self.cpu.ESP += self.ir_arch.sp.size // 8 return value def push_uint32_t(self, value): - self.cpu.ESP -= self.ir_arch.sp.size / 8 + self.cpu.ESP -= self.ir_arch.sp.size // 8 self.vm.set_u32(self.cpu.ESP, value) def pop_uint32_t(self): value = self.vm.get_u32(self.cpu.ESP) - self.cpu.ESP += self.ir_arch.sp.size / 8 + self.cpu.ESP += self.ir_arch.sp.size // 8 return value def get_stack_arg(self, index): @@ -116,7 +117,7 @@ class jitter_x86_32(Jitter): @named_arguments def func_args_stdcall(self, n_args): ret_ad = self.pop_uint32_t() - args = [self.pop_uint32_t() for _ in xrange(n_args)] + args = [self.pop_uint32_t() for _ in range(n_args)] return ret_ad, args def func_ret_stdcall(self, ret_addr, ret_value1=None, ret_value2=None): @@ -137,7 +138,7 @@ class jitter_x86_32(Jitter): @named_arguments def func_args_cdecl(self, n_args): ret_ad = self.pop_uint32_t() - args = [self.get_stack_arg(i) for i in xrange(n_args)] + args = [self.get_stack_arg(i) for i in range(n_args)] return ret_ad, args def func_ret_cdecl(self, ret_addr, ret_value1=None, ret_value2=None): @@ -162,13 +163,13 @@ class jitter_x86_32(Jitter): args_regs = ['ECX', 'EDX'] ret_ad = self.pop_uint32_t() args = [] - for i in xrange(n_args): + for i in range(n_args): args.append(self.get_arg_n_fastcall(i)) return ret_ad, args def func_prepare_fastcall(self, ret_addr, *args): args_regs = ['ECX', 'EDX'] - for i in xrange(min(len(args), len(args_regs))): + for i in range(min(len(args), len(args_regs))): setattr(self.cpu, args_regs[i], args[i]) remaining_args = args[len(args_regs):] for arg in reversed(remaining_args): @@ -202,12 +203,12 @@ class jitter_x86_64(Jitter): return self.orig_irbloc_fix_regs_for_mode(irblock, 64) def push_uint64_t(self, value): - self.cpu.RSP -= self.ir_arch.sp.size / 8 + self.cpu.RSP -= self.ir_arch.sp.size // 8 self.vm.set_u64(self.cpu.RSP, value) def pop_uint64_t(self): value = self.vm.get_u64(self.cpu.RSP) - self.cpu.RSP += self.ir_arch.sp.size / 8 + self.cpu.RSP += self.ir_arch.sp.size // 8 return value def get_stack_arg(self, index): @@ -225,15 +226,15 @@ class jitter_x86_64(Jitter): args_regs = self.args_regs_stdcall ret_ad = self.pop_uint64_t() args = [] - for i in xrange(min(n_args, 4)): + for i in range(min(n_args, 4)): args.append(self.cpu.get_gpreg()[args_regs[i]]) - for i in xrange(max(0, n_args - 4)): + for i in range(max(0, n_args - 4)): args.append(self.get_stack_arg(i)) return ret_ad, args def func_prepare_stdcall(self, ret_addr, *args): args_regs = self.args_regs_stdcall - for i in xrange(min(len(args), len(args_regs))): + for i in range(min(len(args), len(args_regs))): setattr(self.cpu, args_regs[i], args[i]) remaining_args = args[len(args_regs):] for arg in reversed(remaining_args): @@ -262,7 +263,7 @@ class jitter_x86_64(Jitter): @named_arguments def func_args_systemv(self, n_args): ret_ad = self.pop_uint64_t() - args = [self.get_arg_n_systemv(index) for index in xrange(n_args)] + args = [self.get_arg_n_systemv(index) for index in range(n_args)] return ret_ad, args func_ret_systemv = func_ret_cdecl @@ -270,7 +271,7 @@ class jitter_x86_64(Jitter): def func_prepare_systemv(self, ret_addr, *args): args_regs = self.args_regs_systemv self.push_uint64_t(ret_addr) - for i in xrange(min(len(args), len(args_regs))): + for i in range(min(len(args), len(args_regs))): setattr(self.cpu, args_regs[i], args[i]) remaining_args = args[len(args_regs):] for arg in reversed(remaining_args): diff --git a/miasm2/arch/x86/regs.py b/miasm2/arch/x86/regs.py index ef1095e2..b3f6534b 100644 --- a/miasm2/arch/x86/regs.py +++ b/miasm2/arch/x86/regs.py @@ -1,3 +1,4 @@ +from builtins import range from miasm2.expression.expression import ExprId from miasm2.core.cpu import reg_info @@ -12,20 +13,20 @@ interrupt_num = ExprId('interrupt_num', 8) regs08_str = ["AL", "CL", "DL", "BL", "AH", "CH", "DH", "BH"] + \ - ["R%dB" % (i + 8) for i in xrange(8)] + ["R%dB" % (i + 8) for i in range(8)] regs08_expr = [ExprId(x, 8) for x in regs08_str] regs08_64_str = ["AL", "CL", "DL", "BL", "SPL", "BPL", "SIL", "DIL"] + \ - ["R%dB" % (i + 8) for i in xrange(8)] + ["R%dB" % (i + 8) for i in range(8)] regs08_64_expr = [ExprId(x, 8) for x in regs08_64_str] regs16_str = ["AX", "CX", "DX", "BX", "SP", "BP", "SI", "DI"] + \ - ["R%dW" % (i + 8) for i in xrange(8)] + ["R%dW" % (i + 8) for i in range(8)] regs16_expr = [ExprId(x, 16) for x in regs16_str] regs32_str = ["EAX", "ECX", "EDX", "EBX", "ESP", "EBP", "ESI", "EDI"] + \ - ["R%dD" % (i + 8) for i in xrange(8)] + ["R%dD" % (i + 8) for i in range(8)] regs32_expr = [ExprId(x, 32) for x in regs32_str] regs64_str = ["RAX", "RCX", "RDX", "RBX", "RSP", "RBP", "RSI", "RDI", @@ -34,13 +35,13 @@ regs64_str = ["RAX", "RCX", "RDX", "RBX", "RSP", "RBP", "RSI", "RDI", regs64_expr = [ExprId(x, 64) for x in regs64_str] -regs_xmm_str = ["XMM%d" % i for i in xrange(16)] +regs_xmm_str = ["XMM%d" % i for i in range(16)] regs_xmm_expr = [ExprId(x, 128) for x in regs_xmm_str] -regs_mm_str = ["MM%d" % i for i in xrange(16)] +regs_mm_str = ["MM%d" % i for i in range(16)] regs_mm_expr = [ExprId(x, 64) for x in regs_mm_str] -regs_bnd_str = ["BND%d" % i for i in xrange(4)] +regs_bnd_str = ["BND%d" % i for i in range(4)] regs_bnd_expr = [ExprId(x, 128) for x in regs_bnd_str] gpregs08 = reg_info(regs08_str, regs08_expr) @@ -74,17 +75,17 @@ selectr_str = ["ES", "CS", "SS", "DS", "FS", "GS"] selectr_expr = [ExprId(x, 16) for x in selectr_str] segmreg = reg_info(selectr_str, selectr_expr) -crregs32_str = ["CR%d" % i for i in xrange(8)] +crregs32_str = ["CR%d" % i for i in range(8)] crregs32_expr = [ExprId(x, 32) for x in crregs32_str] crregs = reg_info(crregs32_str, crregs32_expr) -drregs32_str = ["DR%d" % i for i in xrange(8)] +drregs32_str = ["DR%d" % i for i in range(8)] drregs32_expr = [ExprId(x, 32) for x in drregs32_str] drregs = reg_info(drregs32_str, drregs32_expr) -fltregs32_str = ["ST(%d)" % i for i in xrange(8)] +fltregs32_str = ["ST(%d)" % i for i in range(8)] fltregs32_expr = [ExprId(x, 64) for x in fltregs32_str] fltregs = reg_info(fltregs32_str, fltregs32_expr) @@ -345,7 +346,7 @@ float_st7 = ExprId("float_st7", 64) float_list = [float_st0, float_st1, float_st2, float_st3, float_st4, float_st5, float_st6, float_st7] -float_replace = {fltregs32_expr[i]: float_list[i] for i in xrange(8)} +float_replace = {fltregs32_expr[i]: float_list[i] for i in range(8)} float_replace[r_st_all.expr[0]] = float_st0 diff --git a/miasm2/arch/x86/sem.py b/miasm2/arch/x86/sem.py index d03a7cd4..bec09249 100644 --- a/miasm2/arch/x86/sem.py +++ b/miasm2/arch/x86/sem.py @@ -16,6 +16,10 @@ # 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. # +from builtins import range + +from future.utils import viewitems + import logging import miasm2.expression.expression as m2_expr from miasm2.expression.simplifications import expr_simp @@ -882,7 +886,7 @@ def push_gen(ir, instr, src, size): off_size = src.size sp = mRSP[instr.mode] - new_sp = sp - m2_expr.ExprInt(off_size / 8, sp.size) + new_sp = sp - m2_expr.ExprInt(off_size // 8, sp.size) e.append(m2_expr.ExprAssign(sp, new_sp)) if ir.do_stk_segm: new_sp = ir.gen_segm_expr(SS, new_sp) @@ -905,7 +909,7 @@ def pop_gen(ir, instr, src, size): raise ValueError('bad size stacker!') sp = mRSP[instr.mode] - new_sp = sp + m2_expr.ExprInt(src.size / 8, sp.size) + new_sp = sp + m2_expr.ExprInt(src.size // 8, sp.size) # don't generate ESP incrementation on POP ESP if src != ir.sp: e.append(m2_expr.ExprAssign(sp, new_sp)) @@ -1187,7 +1191,7 @@ def cmps(ir, instr, size): src1_sgm = src1 src2_sgm = src2 - offset = m2_expr.ExprInt(size / 8, src1.size) + offset = m2_expr.ExprInt(size // 8, src1.size) e, _ = l_cmp(ir, instr, ir.ExprMem(src1_sgm, size), @@ -1226,7 +1230,7 @@ def scas(ir, instr, size): else: src_sgm = src - offset = m2_expr.ExprInt(size / 8, src.size) + offset = m2_expr.ExprInt(size // 8, src.size) e, extra = l_cmp(ir, instr, mRAX[instr.mode][:size], ir.ExprMem(src_sgm, size)) @@ -1298,7 +1302,7 @@ def popfd(ir, instr): e.append(m2_expr.ExprAssign(vip, m2_expr.ExprSlice(tmp, 20, 21))) e.append(m2_expr.ExprAssign(i_d, m2_expr.ExprSlice(tmp, 21, 22))) e.append(m2_expr.ExprAssign(mRSP[instr.mode], - mRSP[instr.mode] + m2_expr.ExprInt(instr.mode / 8, mRSP[instr.mode].size))) + mRSP[instr.mode] + m2_expr.ExprInt(instr.mode // 8, mRSP[instr.mode].size))) e.append(m2_expr.ExprAssign(exception_flags, m2_expr.ExprCond(m2_expr.ExprSlice(tmp, 8, 9), m2_expr.ExprInt( @@ -1339,7 +1343,7 @@ def pusha_gen(ir, instr, size): e = [] cur_sp = mRSP[instr.mode] for i, reg in enumerate(pa_regs): - stk_ptr = cur_sp + m2_expr.ExprInt(-(size / 8) * (i + 1), instr.mode) + stk_ptr = cur_sp + m2_expr.ExprInt(-(size // 8) * (i + 1), instr.mode) e.append(m2_expr.ExprAssign(ir.ExprMem(stk_ptr, size), reg[size])) e.append(m2_expr.ExprAssign(cur_sp, stk_ptr)) return e, [] @@ -1359,10 +1363,10 @@ def popa_gen(ir, instr, size): for i, reg in enumerate(reversed(pa_regs)): if reg == mRSP: continue - stk_ptr = cur_sp + m2_expr.ExprInt((size / 8) * i, instr.mode) + stk_ptr = cur_sp + m2_expr.ExprInt((size // 8) * i, instr.mode) e.append(m2_expr.ExprAssign(reg[size], ir.ExprMem(stk_ptr, size))) - stk_ptr = cur_sp + m2_expr.ExprInt((size / 8) * (i + 1), instr.mode) + stk_ptr = cur_sp + m2_expr.ExprInt((size // 8) * (i + 1), instr.mode) e.append(m2_expr.ExprAssign(cur_sp, stk_ptr)) return e, [] @@ -1407,19 +1411,19 @@ def call(ir, instr, dst): e.append(m2_expr.ExprAssign(ir.IRDst, m2)) - c = myesp + m2_expr.ExprInt(-s / 8, s) + c = myesp + m2_expr.ExprInt(-s // 8, s) e.append(m2_expr.ExprAssign(ir.ExprMem(c, size=s).zeroExtend(s), CS.zeroExtend(s))) - c = myesp + m2_expr.ExprInt(-2 * s / 8, s) + c = myesp + m2_expr.ExprInt((-2 * s) // 8, s) e.append(m2_expr.ExprAssign(ir.ExprMem(c, size=s).zeroExtend(s), meip.zeroExtend(s))) - c = myesp + m2_expr.ExprInt((-2 * s) / 8, s) + c = myesp + m2_expr.ExprInt((-2 * s) // 8, s) e.append(m2_expr.ExprAssign(myesp, c)) return e, [] - c = myesp + m2_expr.ExprInt((-s / 8), s) + c = myesp + m2_expr.ExprInt(-s // 8, s) e.append(m2_expr.ExprAssign(myesp, c)) if ir.do_stk_segm: c = ir.gen_segm_expr(SS, c) @@ -1437,10 +1441,10 @@ def ret(ir, instr, src=None): myesp = mRSP[instr.mode][:size] if src is None: - value = (myesp + (m2_expr.ExprInt((size / 8), size))) + value = (myesp + (m2_expr.ExprInt(size // 8, size))) else: src = m2_expr.ExprInt(int(src), size) - value = (myesp + (m2_expr.ExprInt((size / 8), size) + src)) + value = (myesp + (m2_expr.ExprInt(size // 8, size) + src)) e.append(m2_expr.ExprAssign(myesp, value)) result = myesp @@ -1473,13 +1477,13 @@ def retf(ir, instr, src=None): e.append(m2_expr.ExprAssign(ir.IRDst, ir.ExprMem(result, size=size).zeroExtend(size))) # e.append(m2_expr.ExprAssign(meip, ir.ExprMem(c, size = s))) - result = myesp + m2_expr.ExprInt(size / 8, size) + result = myesp + m2_expr.ExprInt(size // 8, size) if ir.do_stk_segm: result = ir.gen_segm_expr(SS, result) e.append(m2_expr.ExprAssign(CS, ir.ExprMem(result, size=16))) - value = myesp + (m2_expr.ExprInt((2 * size) / 8, size) + src) + value = myesp + (m2_expr.ExprInt((2 * size) // 8, size) + src) e.append(m2_expr.ExprAssign(myesp, value)) return e, [] @@ -1490,7 +1494,7 @@ def leave(ir, instr): e = [] e.append(m2_expr.ExprAssign(mRBP[size], ir.ExprMem(mRBP[size], size=size))) e.append(m2_expr.ExprAssign(myesp, - m2_expr.ExprInt(size / 8, size) + mRBP[size])) + m2_expr.ExprInt(size // 8, size) + mRBP[size])) return e, [] @@ -1502,12 +1506,12 @@ def enter(ir, instr, src1, src2): src1 = src1.zeroExtend(size) e = [] - esp_tmp = myesp - m2_expr.ExprInt(size / 8, size) + esp_tmp = myesp - m2_expr.ExprInt(size // 8, size) e.append(m2_expr.ExprAssign(ir.ExprMem(esp_tmp, size=size), myebp)) e.append(m2_expr.ExprAssign(myebp, esp_tmp)) e.append(m2_expr.ExprAssign(myesp, - myesp - (src1 + m2_expr.ExprInt(size / 8, size)))) + myesp - (src1 + m2_expr.ExprInt(size // 8, size)))) return e, [] @@ -1930,8 +1934,8 @@ def stos(ir, instr, size): addr_o = mRDI[instr.mode][:instr.v_admode()] addr = addr_o - addr_p = addr + m2_expr.ExprInt(size / 8, addr.size) - addr_m = addr - m2_expr.ExprInt(size / 8, addr.size) + addr_p = addr + m2_expr.ExprInt(size // 8, addr.size) + addr_m = addr - m2_expr.ExprInt(size // 8, addr.size) if ir.do_str_segm: mss = ES if instr.additional_info.g2.value: @@ -1966,8 +1970,8 @@ def lods(ir, instr, size): addr_o = mRSI[instr.mode][:instr.v_admode()] addr = addr_o - addr_p = addr + m2_expr.ExprInt(size / 8, addr.size) - addr_m = addr - m2_expr.ExprInt(size / 8, addr.size) + addr_p = addr + m2_expr.ExprInt(size // 8, addr.size) + addr_m = addr - m2_expr.ExprInt(size // 8, addr.size) if ir.do_str_segm: mss = DS if instr.additional_info.g2.value: @@ -2018,7 +2022,7 @@ def movs(ir, instr, size): src_sgm = src dst_sgm = dst - offset = m2_expr.ExprInt(size / 8, src.size) + offset = m2_expr.ExprInt(size // 8, src.size) e.append(m2_expr.ExprAssign(ir.ExprMem(dst_sgm, size), ir.ExprMem(src_sgm, size))) @@ -2081,12 +2085,12 @@ def float_pop(avoid_flt=None, popcount=1): """ avoid_flt = float_prev(avoid_flt, popcount) e = [] - for i in xrange(8 - popcount): + for i in range(8 - popcount): if avoid_flt != float_list[i]: e.append(m2_expr.ExprAssign(float_list[i], float_list[i + popcount])) fill_value = m2_expr.ExprOp("sint_to_fp", m2_expr.ExprInt(0, 64)) - for i in xrange(8 - popcount, 8): + for i in range(8 - popcount, 8): e.append(m2_expr.ExprAssign(float_list[i], fill_value)) e.append( @@ -2619,20 +2623,45 @@ def fnstenv(ir, instr, dst): size = min(32, s) ad = ir.ExprMem(dst.ptr, size=16) e.append(m2_expr.ExprAssign(ad, float_control)) - ad = ir.ExprMem(dst.ptr + m2_expr.ExprInt(size / - 8 * 1, dst.ptr.size), size=16) + ad = ir.ExprMem( + dst.ptr + m2_expr.ExprInt( + size // (8 * 1), + dst.ptr.size + ), + size=16 + ) e.append(m2_expr.ExprAssign(ad, status_word)) - ad = ir.ExprMem(dst.ptr + m2_expr.ExprInt(size / - 8 * 3, dst.ptr.size), size=size) + ad = ir.ExprMem( + dst.ptr + m2_expr.ExprInt( + size // (8 * 3), + dst.ptr.size + ), + size=size + ) e.append(m2_expr.ExprAssign(ad, float_eip[:size])) - ad = ir.ExprMem(dst.ptr + m2_expr.ExprInt(size / - 8 * 4, dst.ptr.size), size=16) + ad = ir.ExprMem( + dst.ptr + m2_expr.ExprInt( + size // (8 * 4), + dst.ptr.size + ), + size=16 + ) e.append(m2_expr.ExprAssign(ad, float_cs)) - ad = ir.ExprMem(dst.ptr + m2_expr.ExprInt(size / - 8 * 5, dst.ptr.size), size=size) + ad = ir.ExprMem( + dst.ptr + m2_expr.ExprInt( + size // (8 * 5), + dst.ptr.size + ), + size=size + ) e.append(m2_expr.ExprAssign(ad, float_address[:size])) - ad = ir.ExprMem(dst.ptr + m2_expr.ExprInt(size / - 8 * 6, dst.ptr.size), size=16) + ad = ir.ExprMem( + dst.ptr + m2_expr.ExprInt( + size // (8 * 6), + dst.ptr.size + ), + size=16 + ) e.append(m2_expr.ExprAssign(ad, float_ds)) return e, [] @@ -2651,23 +2680,35 @@ def fldenv(ir, instr, src): e.append(m2_expr.ExprAssign(float_control, ad)) # Status word - ad = ir.ExprMem(src.ptr + m2_expr.ExprInt(size / 8 * 1, size=src.ptr.size), - size=16) - e += [m2_expr.ExprAssign(x, y) for x, y in ((float_c0, ad[8:9]), - (float_c1, ad[9:10]), - (float_c2, ad[10:11]), - (float_stack_ptr, ad[11:14]), - (float_c3, ad[14:15])) - ] + ad = ir.ExprMem( + src.ptr + m2_expr.ExprInt( + size // (8 * 1), + size=src.ptr.size + ), + size=16 + ) + e += [ + m2_expr.ExprAssign(x, y) for x, y in ((float_c0, ad[8:9]), + (float_c1, ad[9:10]), + (float_c2, ad[10:11]), + (float_stack_ptr, ad[11:14]), + (float_c3, ad[14:15])) + ] # EIP, CS, Address, DS - for offset, target in ((3, float_eip[:size]), - (4, float_cs), - (5, float_address[:size]), - (6, float_ds)): - ad = ir.ExprMem(src.ptr + m2_expr.ExprInt(size / 8 * offset, - size=src.ptr.size), - size=target.size) + for offset, target in ( + (3, float_eip[:size]), + (4, float_cs), + (5, float_address[:size]), + (6, float_ds) + ): + ad = ir.ExprMem( + src.ptr + m2_expr.ExprInt( + size // ( 8 * offset), + size=src.ptr.size + ), + size=target.size + ) e.append(m2_expr.ExprAssign(target, ad)) return e, [] @@ -3243,7 +3284,7 @@ def sidt(ir, instr, dst): if not isinstance(dst, m2_expr.ExprMem) or dst.size != 32: raise ValueError('not exprmem 32bit instance!!') ptr = dst.ptr - LOG_X86_SEM.warning("DEFAULT SIDT ADDRESS %s!!", str(dst)) + LOG_X86_SEM.warning("DEFAULT SIDT ADDRESS %s!!", dst) e.append(m2_expr.ExprAssign(ir.ExprMem(ptr, 32), m2_expr.ExprInt(0xe40007ff, 32))) e.append( @@ -3253,7 +3294,7 @@ def sidt(ir, instr, dst): def sldt(_, instr, dst): - LOG_X86_SEM.warning("DEFAULT SLDT ADDRESS %s!!", str(dst)) + LOG_X86_SEM.warning("DEFAULT SLDT ADDRESS %s!!", dst) e = [m2_expr.ExprAssign(dst, m2_expr.ExprInt(0, dst.size))] return e, [] @@ -3531,7 +3572,7 @@ def cmpxchg16b(arg1): def lds(ir, instr, dst, src): e = [] e.append(m2_expr.ExprAssign(dst, ir.ExprMem(src.ptr, size=dst.size))) - DS_value = ir.ExprMem(src.ptr + m2_expr.ExprInt(dst.size / 8, src.ptr.size), + DS_value = ir.ExprMem(src.ptr + m2_expr.ExprInt(dst.size // 8, src.ptr.size), size=16) e.append(m2_expr.ExprAssign(DS, DS_value)) return e, [] @@ -3540,7 +3581,7 @@ def lds(ir, instr, dst, src): def les(ir, instr, dst, src): e = [] e.append(m2_expr.ExprAssign(dst, ir.ExprMem(src.ptr, size=dst.size))) - ES_value = ir.ExprMem(src.ptr + m2_expr.ExprInt(dst.size / 8, src.ptr.size), + ES_value = ir.ExprMem(src.ptr + m2_expr.ExprInt(dst.size // 8, src.ptr.size), size=16) e.append(m2_expr.ExprAssign(ES, ES_value)) return e, [] @@ -3549,7 +3590,7 @@ def les(ir, instr, dst, src): def lss(ir, instr, dst, src): e = [] e.append(m2_expr.ExprAssign(dst, ir.ExprMem(src.ptr, size=dst.size))) - SS_value = ir.ExprMem(src.ptr + m2_expr.ExprInt(dst.size / 8, src.ptr.size), + SS_value = ir.ExprMem(src.ptr + m2_expr.ExprInt(dst.size // 8, src.ptr.size), size=16) e.append(m2_expr.ExprAssign(SS, SS_value)) return e, [] @@ -3558,7 +3599,7 @@ def lss(ir, instr, dst, src): def lfs(ir, instr, dst, src): e = [] e.append(m2_expr.ExprAssign(dst, ir.ExprMem(src.ptr, size=dst.size))) - FS_value = ir.ExprMem(src.ptr + m2_expr.ExprInt(dst.size / 8, src.ptr.size), + FS_value = ir.ExprMem(src.ptr + m2_expr.ExprInt(dst.size // 8, src.ptr.size), size=16) e.append(m2_expr.ExprAssign(FS, FS_value)) return e, [] @@ -3567,7 +3608,7 @@ def lfs(ir, instr, dst, src): def lgs(ir, instr, dst, src): e = [] e.append(m2_expr.ExprAssign(dst, ir.ExprMem(src.ptr, size=dst.size))) - GS_value = ir.ExprMem(src.ptr + m2_expr.ExprInt(dst.size / 8, src.ptr.size), + GS_value = ir.ExprMem(src.ptr + m2_expr.ExprInt(dst.size // 8, src.ptr.size), size=16) e.append(m2_expr.ExprAssign(GS, GS_value)) return e, [] @@ -3704,18 +3745,18 @@ def vec_op_clip(op, size, callback=None): def vec_vertical_sem(op, elt_size, reg_size, dst, src, apply_on_output): assert reg_size % elt_size == 0 - n = reg_size / elt_size + n = reg_size // elt_size if op == '-': ops = [ apply_on_output((dst[i * elt_size:(i + 1) * elt_size] - src[i * elt_size:(i + 1) * elt_size])) - for i in xrange(0, n) + for i in range(0, n) ] else: ops = [ apply_on_output(m2_expr.ExprOp(op, dst[i * elt_size:(i + 1) * elt_size], src[i * elt_size:(i + 1) * elt_size])) - for i in xrange(0, n) + for i in range(0, n) ] return m2_expr.ExprCompose(*ops) @@ -3857,7 +3898,7 @@ def pmaddwd(ir, instr, dst, src): sizedst = 32 sizesrc = 16 out = [] - for start in xrange(0, dst.size, sizedst): + for start in range(0, dst.size, sizedst): base = start mul1 = src[base: base + sizesrc].signExtend(sizedst) * dst[base: base + sizesrc].signExtend(sizedst) base += sizesrc @@ -3877,9 +3918,9 @@ def psadbw(ir, instr, dst, src): sizedst = 16 sizesrc = 8 out_dst = [] - for start in xrange(0, dst.size, 64): + for start in range(0, dst.size, 64): out = [] - for src_start in xrange(0, 64, sizesrc): + for src_start in range(0, 64, sizesrc): beg = start + src_start end = beg + sizesrc # Not clear in the doc equations, but in the text, src and dst are: @@ -4311,7 +4352,7 @@ def pshufb(_, instr, dst, src): bit_l = 4 else: raise NotImplementedError("bad size") - for i in xrange(0, src.size, 8): + for i in range(0, src.size, 8): index = src[ i:i + bit_l].zeroExtend(dst.size) << m2_expr.ExprInt(3, dst.size) value = (dst >> index)[:8] @@ -4325,7 +4366,7 @@ def pshufb(_, instr, dst, src): def pshufd(_, instr, dst, src, imm): control = int(imm) out = [] - for i in xrange(4): + for i in range(4): shift = ((control >> (i * 2)) & 3) * 32 # shift is 2 bits long, expr.size is 128 # => shift + 32 <= src.size @@ -4336,7 +4377,7 @@ def pshufd(_, instr, dst, src, imm): def pshuflw(_, instr, dst, src, imm): control = int(imm) out = [] - for i in xrange(4): + for i in range(4): shift = ((control >> (i * 2)) & 3) * 16 out.append(src[shift: shift + 16]) out.append(src[64:]) @@ -4346,7 +4387,7 @@ def pshuflw(_, instr, dst, src, imm): def pshufhw(_, instr, dst, src, imm): control = int(imm) out = [src[:64]] - for i in xrange(4): + for i in range(4): shift = ((control >> (i * 2)) & 3) * 16 out.append(src[shift + 64: shift + 16 + 64]) return [m2_expr.ExprAssign(dst, m2_expr.ExprCompose(*out))], [] @@ -4369,7 +4410,7 @@ def ps_rl_ll(ir, instr, dst, src, op, size): count = expr_simp(count) out = [] - for i in xrange(0, dst.size, size): + for i in range(0, dst.size, size): out.append(m2_expr.ExprOp(op, dst[i:i + size], count)) return [m2_expr.ExprAssign(dst, m2_expr.ExprCompose(*out))], [] @@ -4430,15 +4471,15 @@ def iret(ir, instr): XXX: only support "no-privilege change" """ size = instr.v_opmode() - exprs, _ = retf(ir, instr, m2_expr.ExprInt(size / 8, size=size)) - tmp = mRSP[instr.mode][:size] + m2_expr.ExprInt((2 * size) / 8, size=size) + exprs, _ = retf(ir, instr, m2_expr.ExprInt(size // 8, size=size)) + tmp = mRSP[instr.mode][:size] + m2_expr.ExprInt((2 * size) // 8, size=size) exprs += _tpl_eflags(tmp) return exprs, [] def pcmpeq(_, instr, dst, src, size): e = [] - for i in xrange(0, dst.size, size): + for i in range(0, dst.size, size): test = m2_expr.expr_is_equal(dst[i:i + size], src[i:i + size]) e.append(m2_expr.ExprAssign(dst[i:i + size], m2_expr.ExprCond(test, @@ -4449,7 +4490,7 @@ def pcmpeq(_, instr, dst, src, size): def pcmpgt(_, instr, dst, src, size): e = [] - for i in xrange(0, dst.size, size): + for i in range(0, dst.size, size): test = m2_expr.expr_is_signed_greater(dst[i:i + size], src[i:i + size]) e.append(m2_expr.ExprAssign(dst[i:i + size], m2_expr.ExprCond(test, @@ -4490,7 +4531,7 @@ def pcmpgtq(ir, instr, dst, src): def punpck(_, instr, dst, src, size, off): e = [] slices = [] - for i in xrange(dst.size / (2 * size)): + for i in range(dst.size // (2 * size)): slices.append(dst[size * i + off: size * i + off + size]) slices.append(src[size * i + off: size * i + off + size]) e.append(m2_expr.ExprAssign(dst, m2_expr.ExprCompose(*slices))) @@ -4498,19 +4539,19 @@ def punpck(_, instr, dst, src, size, off): def punpckhbw(ir, instr, dst, src): - return punpck(ir, instr, dst, src, 8, dst.size / 2) + return punpck(ir, instr, dst, src, 8, dst.size // 2) def punpckhwd(ir, instr, dst, src): - return punpck(ir, instr, dst, src, 16, dst.size / 2) + return punpck(ir, instr, dst, src, 16, dst.size // 2) def punpckhdq(ir, instr, dst, src): - return punpck(ir, instr, dst, src, 32, dst.size / 2) + return punpck(ir, instr, dst, src, 32, dst.size // 2) def punpckhqdq(ir, instr, dst, src): - return punpck(ir, instr, dst, src, 64, dst.size / 2) + return punpck(ir, instr, dst, src, 64, dst.size // 2) def punpcklbw(ir, instr, dst, src): @@ -4667,7 +4708,7 @@ def movq2dq(_, instr, dst, src): def sqrt_gen(_, instr, dst, src, size): e = [] out = [] - for i in xrange(src.size / size): + for i in range(src.size // size): out.append(m2_expr.ExprOp('fsqrt', src[i * size: (i + 1) * size])) src = m2_expr.ExprCompose(*out) @@ -4702,7 +4743,7 @@ def sqrtss(_, instr, dst, src): def pmovmskb(_, instr, dst, src): e = [] out = [] - for i in xrange(src.size / 8): + for i in range(src.size // 8): out.append(src[8 * i + 7:8 * (i + 1)]) src = m2_expr.ExprCompose(*out) e.append(m2_expr.ExprAssign(dst, src.zeroExtend(dst.size))) @@ -4807,7 +4848,7 @@ def _unsigned_saturation(expr, dst_size): def packsswb(ir, instr, dst, src): out = [] for source in [dst, src]: - for start in xrange(0, dst.size, 16): + for start in range(0, dst.size, 16): out.append(_signed_saturation(source[start:start + 16], 8)) return [m2_expr.ExprAssign(dst, m2_expr.ExprCompose(*out))], [] @@ -4815,7 +4856,7 @@ def packsswb(ir, instr, dst, src): def packssdw(ir, instr, dst, src): out = [] for source in [dst, src]: - for start in xrange(0, dst.size, 32): + for start in range(0, dst.size, 32): out.append(_signed_saturation(source[start:start + 32], 16)) return [m2_expr.ExprAssign(dst, m2_expr.ExprCompose(*out))], [] @@ -4823,7 +4864,7 @@ def packssdw(ir, instr, dst, src): def packuswb(ir, instr, dst, src): out = [] for source in [dst, src]: - for start in xrange(0, dst.size, 16): + for start in range(0, dst.size, 16): out.append(_unsigned_saturation(source[start:start + 16], 8)) return [m2_expr.ExprAssign(dst, m2_expr.ExprCompose(*out))], [] @@ -4894,13 +4935,13 @@ def maskmovq(ir, instr, src, mask): # For each possibility, check if a write is necessary check_labels = [m2_expr.ExprLoc(ir.loc_db.add_location(), ir.IRDst.size) - for _ in xrange(0, mask.size, 8)] + for _ in range(0, mask.size, 8)] # If the write has to be done, do it (otherwise, nothing happen) write_labels = [m2_expr.ExprLoc(ir.loc_db.add_location(), ir.IRDst.size) - for _ in xrange(0, mask.size, 8)] + for _ in range(0, mask.size, 8)] # Build check blocks - for i, start in enumerate(xrange(0, mask.size, 8)): + for i, start in enumerate(range(0, mask.size, 8)): bit = mask[start + 7: start + 8] cur_label = check_labels[i] next_check_label = check_labels[i + 1] if (i + 1) < len(check_labels) else loc_next_expr @@ -4913,7 +4954,7 @@ def maskmovq(ir, instr, src, mask): # Build write blocks dst_addr = mRDI[instr.mode] - for i, start in enumerate(xrange(0, mask.size, 8)): + for i, start in enumerate(range(0, mask.size, 8)): cur_label = write_labels[i] next_check_label = check_labels[i + 1] if (i + 1) < len(check_labels) else loc_next_expr write_addr = dst_addr + m2_expr.ExprInt(i, dst_addr.size) @@ -4972,7 +5013,7 @@ def _select4(src, control): def shufps(ir, instr, dst, src, imm8): out = [] control = int(imm8) - for i in xrange(4): + for i in range(4): if i < 2: source = dst else: @@ -4990,13 +5031,13 @@ def shufpd(ir, instr, dst, src, imm8): def movmskps(ir, instr, dst, src): out = [] - for i in xrange(4): + for i in range(4): out.append(src[(32 * i) + 31:(32 * i) + 32]) return [m2_expr.ExprAssign(dst, m2_expr.ExprCompose(*out).zeroExtend(dst.size))], [] def movmskpd(ir, instr, dst, src): out = [] - for i in xrange(2): + for i in range(2): out.append(src[(64 * i) + 63:(64 * i) + 64]) return [m2_expr.ExprAssign(dst, m2_expr.ExprCompose(*out).zeroExtend(dst.size))], [] @@ -5720,7 +5761,7 @@ class ir_x86_16(IntermediateRepresentation): irs = [] for assignblk in irblock: new_assignblk = dict(assignblk) - for dst, src in assignblk.iteritems(): + for dst, src in viewitems(assignblk): del new_assignblk[dst] # Special case for 64 bits: # If destination is a 32 bit reg, zero extend the 64 bit reg |