5 files changed, 7 insertions, 7 deletions
diff --git a/miasm2/arch/aarch64/sem.py b/miasm2/arch/aarch64/sem.py
index f22f0c07..e4702a4f 100644
--- a/miasm2/arch/aarch64/sem.py
+++ b/miasm2/arch/aarch64/sem.py
@@ -809,7 +809,7 @@ def udiv(arg1, arg2, arg3):
 @sbuild.parse
 def sdiv(arg1, arg2, arg3):
     if arg3:
-        arg1 = ExprOp('idiv', arg2, arg3)
+        arg1 = ExprOp('sdiv', arg2, arg3)
     else:
         exception_flags = ExprInt(EXCEPT_DIV_BY_ZERO,
                                           exception_flags.size)
diff --git a/miasm2/arch/arm/sem.py b/miasm2/arch/arm/sem.py
index b5ab60d0..64403206 100644
--- a/miasm2/arch/arm/sem.py
+++ b/miasm2/arch/arm/sem.py
@@ -592,7 +592,7 @@ def sdiv(ir, instr, a, b, c=None):
 
 
 
-    r = ExprOp("idiv", b, c)
+    r = ExprOp("sdiv", b, c)
     do_div = []
     do_div.append(ExprAssign(a, r))
     dst = get_dst(a)
diff --git a/miasm2/arch/mips32/sem.py b/miasm2/arch/mips32/sem.py
index a57d2200..62a85355 100644
--- a/miasm2/arch/mips32/sem.py
+++ b/miasm2/arch/mips32/sem.py
@@ -393,8 +393,8 @@ def multu(arg1, arg2):
 @sbuild.parse
 def div(arg1, arg2):
     """Divide (signed) @arg1 by @arg2 and stores the remaining/result in $R_HI/$R_LO"""
-    R_LO = ExprOp('idiv' ,arg1, arg2)
-    R_HI = ExprOp('imod', arg1, arg2)
+    R_LO = ExprOp('sdiv' ,arg1, arg2)
+    R_HI = ExprOp('smod', arg1, arg2)
 
 @sbuild.parse
 def divu(arg1, arg2):
diff --git a/miasm2/arch/ppc/sem.py b/miasm2/arch/ppc/sem.py
index 969a8002..44895624 100644
--- a/miasm2/arch/ppc/sem.py
+++ b/miasm2/arch/ppc/sem.py
@@ -165,7 +165,7 @@ def mn_do_div(ir, instr, rd, ra, rb):
     if has_u:
         op = 'udiv'
     else:
-        op = 'idiv'
+        op = 'sdiv'
 
     rvalue = ExprOp(op, ra, rb)
 
diff --git a/miasm2/arch/x86/sem.py b/miasm2/arch/x86/sem.py
index 244aff30..e01adcbc 100644
--- a/miasm2/arch/x86/sem.py
+++ b/miasm2/arch/x86/sem.py
@@ -1754,8 +1754,8 @@ def idiv(ir, instr, src1):
     else:
         raise ValueError('div arg not impl', src1)
 
-    c_d = m2_expr.ExprOp('idiv', src2, src1.signExtend(src2.size))
-    c_r = m2_expr.ExprOp('imod', src2, src1.signExtend(src2.size))
+    c_d = m2_expr.ExprOp('sdiv', src2, src1.signExtend(src2.size))
+    c_r = m2_expr.ExprOp('smod', src2, src1.signExtend(src2.size))
 
     # if 8 bit div, only ax is affected
     if size == 8: