3 files changed, 47 insertions, 4 deletions
diff --git a/miasm2/arch/mips32/jit.py b/miasm2/arch/mips32/jit.py
new file mode 100644
index 00000000..70e05380
--- /dev/null
+++ b/miasm2/arch/mips32/jit.py
@@ -0,0 +1,37 @@
+from miasm2.jitter.jitload import jitter
+from miasm2.core import asmbloc
+from miasm2.core.utils import *
+from miasm2.arch.mips32.sem import ir_mips32
+
+import logging
+
+log = logging.getLogger('jit_mips32')
+hnd = logging.StreamHandler()
+hnd.setFormatter(logging.Formatter("[%(levelname)s]: %(message)s"))
+log.addHandler(hnd)
+log.setLevel(logging.CRITICAL)
+
+class jitter_mips32(jitter):
+
+    def __init__(self, *args, **kwargs):
+        sp = asmbloc.asm_symbol_pool()
+        jitter.__init__(self, ir_mips32(sp), *args, **kwargs)
+        self.my_ir.jit_pc = self.my_ir.arch.regs.PC
+        self.my_ir.attrib = 'l'
+
+    def vm_push_uint32_t(self, v):
+        self.cpu.SP -= 4
+        self.vm.vm_set_mem(self.cpu.SP, pck32(v))
+
+    def vm_pop_uint32_t(self):
+        x = upck32(self.vm.vm_get_mem(self.cpu.SP, 4))
+        self.cpu.SP += 4
+        return x
+
+    def get_stack_arg(self, n):
+        x = upck32(self.vm.vm_get_mem(self.cpu.SP + 4 * n, 4))
+        return x
+
+    def init_run(self, *args, **kwargs):
+        jitter.init_run(self, *args, **kwargs)
+        self.cpu.PC = self.pc
diff --git a/miasm2/arch/mips32/regs.py b/miasm2/arch/mips32/regs.py
index 2667f482..0f065371 100644
--- a/miasm2/arch/mips32/regs.py
+++ b/miasm2/arch/mips32/regs.py
@@ -9,6 +9,8 @@ gen_reg('PC', globals())
 gen_reg('R_LO', globals())
 gen_reg('R_HI', globals())
 
+PC_init = ExprId("PC_init")
+
 regs32_str = ["ZERO", 'AT', 'V0', 'V1'] +\
     ['A%d'%i for i in xrange(4)] +\
     ['T%d'%i for i in xrange(8)] +\
@@ -42,9 +44,9 @@ regs_flt_expr, regs_flt_init, fltregs = gen_regs(regs_flt_str, globals())
 regs_fcc_expr, regs_fcc_init, fccregs = gen_regs(regs_fcc_str, globals())
 
 
-all_regs_ids = gpregs_expr + regs_flt_expr + regs_fcc_expr
+all_regs_ids = [PC] + gpregs_expr + regs_flt_expr + regs_fcc_expr
 all_regs_ids_byname = dict([(x.name, x) for x in all_regs_ids])
-all_regs_ids_init = gpregs_init + regs_flt_init + regs_fcc_init
+all_regs_ids_init = [PC_init] + gpregs_init + regs_flt_init + regs_fcc_init
 
 regs_init = {}
 for i, r in enumerate(all_regs_ids):
diff --git a/miasm2/arch/mips32/sem.py b/miasm2/arch/mips32/sem.py
index ab2f1c62..41f38b3d 100644
--- a/miasm2/arch/mips32/sem.py
+++ b/miasm2/arch/mips32/sem.py
@@ -59,7 +59,7 @@ def lhu(ir, instr, a, b):
 def beq(ir, instr, a, b, c):
     e = []
     n = ExprId(ir.get_next_break_label(instr))
-    dst_o = ExprCond(a-b, c, n)
+    dst_o = ExprCond(a-b, n, c)
     e = [ExprAff(PC, dst_o)]
     return dst_o, e, []
 
@@ -73,7 +73,7 @@ def bgez(ir, instr, a, b):
 def bne(ir, instr, a, b, c):
     e = []
     n = ExprId(ir.get_next_break_label(instr))
-    dst_o = ExprCond(a-b, n, c)
+    dst_o = ExprCond(a-b, c, n)
     e = [ExprAff(PC, dst_o)]
     return dst_o, e, []
 
@@ -486,3 +486,7 @@ class ir_mips32(ir):
                         {self.pc: ExprInt32(instr.offset + 4)}))
                     irs[i] = x
         return dst, instr_ir, extra_ir
+
+    def get_next_break_label(self, instr):
+        l = self.symbol_pool.getby_offset_create(instr.offset  + 8)
+        return l