6 files changed, 50 insertions, 21 deletions
diff --git a/miasm2/arch/arm/regs.py b/miasm2/arch/arm/regs.py
index 29b2c805..2b31da38 100644
--- a/miasm2/arch/arm/regs.py
+++ b/miasm2/arch/arm/regs.py
@@ -84,3 +84,5 @@ all_regs_ids_init = [R0_init, R1_init, R2_init, R3_init,
 regs_init = {}
 for i, r in enumerate(all_regs_ids):
     regs_init[r] = all_regs_ids_init[i]
+
+regs_flt_expr = []
diff --git a/miasm2/arch/mips32/regs.py b/miasm2/arch/mips32/regs.py
index c87a6412..4999ea51 100644
--- a/miasm2/arch/mips32/regs.py
+++ b/miasm2/arch/mips32/regs.py
@@ -46,7 +46,7 @@ cpr0_str[152] = "WATCHHI"
 regs_cpr0_expr, regs_cpr0_init, regs_cpr0_info = gen_regs(cpr0_str, globals())
 
 gpregs_expr, gpregs_init, gpregs = gen_regs(regs32_str, globals())
-regs_flt_expr, regs_flt_init, fltregs = gen_regs(regs_flt_str, globals())
+regs_flt_expr, regs_flt_init, fltregs = gen_regs(regs_flt_str, globals(), sz=64)
 regs_fcc_expr, regs_fcc_init, fccregs = gen_regs(regs_fcc_str, globals())
 
 
diff --git a/miasm2/arch/msp430/regs.py b/miasm2/arch/msp430/regs.py
index ea86e1fc..60638f26 100644
--- a/miasm2/arch/msp430/regs.py
+++ b/miasm2/arch/msp430/regs.py
@@ -105,3 +105,5 @@ all_regs_ids_init = [PC_init, SP_init, SR_init, R3_init,
 regs_init = {}
 for i, r in enumerate(all_regs_ids):
     regs_init[r] = all_regs_ids_init[i]
+
+regs_flt_expr = []
diff --git a/miasm2/arch/sh4/regs.py b/miasm2/arch/sh4/regs.py
index 6ffe9691..cfbca187 100644
--- a/miasm2/arch/sh4/regs.py
+++ b/miasm2/arch/sh4/regs.py
@@ -80,3 +80,5 @@ regs_init = {}
 for i, r in enumerate(all_regs_ids):
     all_regs_ids_init[i].is_term = True
     regs_init[r] = all_regs_ids_init[i]
+
+regs_flt_expr = []
diff --git a/miasm2/arch/x86/arch.py b/miasm2/arch/x86/arch.py
index a2d5c062..31ee2eb9 100644
--- a/miasm2/arch/x86/arch.py
+++ b/miasm2/arch/x86/arch.py
@@ -55,7 +55,16 @@ replace_regs64 = {
 
     IP: RIP[:16], EIP: RIP[:32],
 
-    float_st0: ExprId("ST(0)", 64),
+    ExprId("ST", 64): float_st0,
+    ExprId("ST(0)", 64): float_st0,
+    ExprId("ST(1)", 64): float_st1,
+    ExprId("ST(2)", 64): float_st2,
+    ExprId("ST(3)", 64): float_st3,
+    ExprId("ST(4)", 64): float_st4,
+    ExprId("ST(5)", 64): float_st5,
+    ExprId("ST(6)", 64): float_st6,
+    ExprId("ST(7)", 64): float_st7,
+
 }
 
 replace_regs32 = {
@@ -67,7 +76,17 @@ replace_regs32 = {
 
     IP: EIP[:16],
 
-    float_st0: ExprId("ST(0)", 64),
+
+    ExprId("ST", 64): float_st0,
+    ExprId("ST(0)", 64): float_st0,
+    ExprId("ST(1)", 64): float_st1,
+    ExprId("ST(2)", 64): float_st2,
+    ExprId("ST(3)", 64): float_st3,
+    ExprId("ST(4)", 64): float_st4,
+    ExprId("ST(5)", 64): float_st5,
+    ExprId("ST(6)", 64): float_st6,
+    ExprId("ST(7)", 64): float_st7,
+
 }
 
 replace_regs16 = {
@@ -77,7 +96,17 @@ replace_regs16 = {
     AX: AX[:16],  CX: CX[:16],  DX: DX[:16],  BX: BX[:16],
     SP: SP[:16],  BP: BP[:16],  SI: SI[:16],  DI: DI[:16],
 
-    float_st0: ExprId("ST(0)", 64),
+
+    ExprId("ST", 64): float_st0,
+    ExprId("ST(0)", 64): float_st0,
+    ExprId("ST(1)", 64): float_st1,
+    ExprId("ST(2)", 64): float_st2,
+    ExprId("ST(3)", 64): float_st3,
+    ExprId("ST(4)", 64): float_st4,
+    ExprId("ST(5)", 64): float_st5,
+    ExprId("ST(6)", 64): float_st6,
+    ExprId("ST(7)", 64): float_st7,
+
 }
 
 replace_regs = {16: replace_regs16,
diff --git a/miasm2/arch/x86/regs.py b/miasm2/arch/x86/regs.py
index a4383249..3fc53545 100644
--- a/miasm2/arch/x86/regs.py
+++ b/miasm2/arch/x86/regs.py
@@ -248,15 +248,6 @@ reg_float_address = 'reg_float_address'
 reg_float_ds = 'reg_float_ds'
 
 
-reg_float_st0 = 'float_st0'
-reg_float_st1 = 'float_st1'
-reg_float_st2 = 'float_st2'
-reg_float_st3 = 'float_st3'
-reg_float_st4 = 'float_st4'
-reg_float_st5 = 'float_st5'
-reg_float_st6 = 'float_st6'
-reg_float_st7 = 'float_st7'
-
 
 dr0 = ExprId(reg_dr0)
 dr1 = ExprId(reg_dr1)
@@ -342,14 +333,14 @@ float_cs = ExprId(reg_float_cs, size=16)
 float_address = ExprId(reg_float_address)
 float_ds = ExprId(reg_float_ds, size=16)
 
-float_st0 = ExprId("ST", 64)
-float_st1 = ExprId("ST(1)", 64)
-float_st2 = ExprId("ST(2)", 64)
-float_st3 = ExprId("ST(3)", 64)
-float_st4 = ExprId("ST(4)", 64)
-float_st5 = ExprId("ST(5)", 64)
-float_st6 = ExprId("ST(6)", 64)
-float_st7 = ExprId("ST(7)", 64)
+float_st0 = ExprId("float_st0", 64)
+float_st1 = ExprId("float_st1", 64)
+float_st2 = ExprId("float_st2", 64)
+float_st3 = ExprId("float_st3", 64)
+float_st4 = ExprId("float_st4", 64)
+float_st5 = ExprId("float_st5", 64)
+float_st6 = ExprId("float_st6", 64)
+float_st7 = ExprId("float_st7", 64)
 
 EAX_init = ExprId('EAX_init')
 EBX_init = ExprId('EBX_init')
@@ -428,6 +419,9 @@ for i, r in enumerate(all_regs_ids):
     all_regs_ids_init[i].is_term = True
     regs_init[r] = all_regs_ids_init[i]
 
+regs_flt_expr = [float_st0, float_st1, float_st2, float_st3,
+                 float_st4, float_st5, float_st6, float_st7,
+             ]
 
 mRAX = {16: AX, 32: EAX, 64: RAX}
 mRBX = {16: BX, 32: EBX, 64: RBX}