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-rw-r--r--miasm2/arch/aarch64/arch.py2
-rw-r--r--miasm2/arch/arm/arch.py6
-rw-r--r--miasm2/arch/arm/regs.py32
-rw-r--r--miasm2/arch/mips32/jit.py10
-rw-r--r--miasm2/arch/mips32/regs.py4
-rw-r--r--miasm2/arch/mips32/sem.py22
-rw-r--r--miasm2/arch/sh4/arch.py6
-rw-r--r--miasm2/arch/x86/regs.py54
8 files changed, 68 insertions, 68 deletions
diff --git a/miasm2/arch/aarch64/arch.py b/miasm2/arch/aarch64/arch.py
index 7af1953a..2712e60a 100644
--- a/miasm2/arch/aarch64/arch.py
+++ b/miasm2/arch/aarch64/arch.py
@@ -219,7 +219,7 @@ simdregs_h_zero = (simd32_info.parser |
 
 def ast_id2expr(t):
     if not t in mn_aarch64.regs.all_regs_ids_byname:
-        r = m2_expr.ExprId(AsmLabel(t))
+        r = m2_expr.ExprId(AsmLabel(t), 32)
     else:
         r = mn_aarch64.regs.all_regs_ids_byname[t]
     return r
diff --git a/miasm2/arch/arm/arch.py b/miasm2/arch/arm/arch.py
index c74d10a8..5e4b02f9 100644
--- a/miasm2/arch/arm/arch.py
+++ b/miasm2/arch/arm/arch.py
@@ -18,7 +18,7 @@ log.addHandler(console_handler)
 log.setLevel(logging.DEBUG)
 
 # arm regs ##############
-reg_dum = ExprId('DumReg')
+reg_dum = ExprId('DumReg', 32)
 
 gen_reg('PC', globals())
 
@@ -66,13 +66,13 @@ spsr_regs = reg_info(spsr_regs_str, spsr_regs_expr)
 
 # CP
 cpregs_str = ['c%d' % r for r in xrange(0x10)]
-cpregs_expr = [ExprId(x) for x in cpregs_str]
+cpregs_expr = [ExprId(x, 32) for x in cpregs_str]
 
 cp_regs = reg_info(cpregs_str, cpregs_expr)
 
 # P
 pregs_str = ['p%d' % r for r in xrange(0x10)]
-pregs_expr = [ExprId(x) for x in pregs_str]
+pregs_expr = [ExprId(x, 32) for x in pregs_str]
 
 p_regs = reg_info(pregs_str, pregs_expr)
 
diff --git a/miasm2/arch/arm/regs.py b/miasm2/arch/arm/regs.py
index 400c6080..8587d7c2 100644
--- a/miasm2/arch/arm/regs.py
+++ b/miasm2/arch/arm/regs.py
@@ -29,22 +29,22 @@ SP = regs32_expr[13]
 LR = regs32_expr[14]
 PC = regs32_expr[15]
 
-R0_init = ExprId("R0_init")
-R1_init = ExprId("R1_init")
-R2_init = ExprId("R2_init")
-R3_init = ExprId("R3_init")
-R4_init = ExprId("R4_init")
-R5_init = ExprId("R5_init")
-R6_init = ExprId("R6_init")
-R7_init = ExprId("R7_init")
-R8_init = ExprId("R8_init")
-R9_init = ExprId("R9_init")
-R10_init = ExprId("R10_init")
-R11_init = ExprId("R11_init")
-R12_init = ExprId("R12_init")
-SP_init = ExprId("SP_init")
-LR_init = ExprId("LR_init")
-PC_init = ExprId("PC_init")
+R0_init = ExprId("R0_init", 32)
+R1_init = ExprId("R1_init", 32)
+R2_init = ExprId("R2_init", 32)
+R3_init = ExprId("R3_init", 32)
+R4_init = ExprId("R4_init", 32)
+R5_init = ExprId("R5_init", 32)
+R6_init = ExprId("R6_init", 32)
+R7_init = ExprId("R7_init", 32)
+R8_init = ExprId("R8_init", 32)
+R9_init = ExprId("R9_init", 32)
+R10_init = ExprId("R10_init", 32)
+R11_init = ExprId("R11_init", 32)
+R12_init = ExprId("R12_init", 32)
+SP_init = ExprId("SP_init", 32)
+LR_init = ExprId("LR_init", 32)
+PC_init = ExprId("PC_init", 32)
 
 
 reg_zf = 'zf'
diff --git a/miasm2/arch/mips32/jit.py b/miasm2/arch/mips32/jit.py
index f3e54a7d..1d2ec483 100644
--- a/miasm2/arch/mips32/jit.py
+++ b/miasm2/arch/mips32/jit.py
@@ -35,8 +35,8 @@ class mipsCGen(CGen):
 
     def __init__(self, ir_arch):
         super(mipsCGen, self).__init__(ir_arch)
-        self.delay_slot_dst = m2_expr.ExprId("branch_dst_irdst")
-        self.delay_slot_set = m2_expr.ExprId("branch_dst_set")
+        self.delay_slot_dst = m2_expr.ExprId("branch_dst_irdst", 32)
+        self.delay_slot_set = m2_expr.ExprId("branch_dst_set", 32)
 
     def block2assignblks(self, block):
         irblocks_list = super(mipsCGen, self).block2assignblks(block)
@@ -58,7 +58,7 @@ class mipsCGen(CGen):
                     assignments[self.delay_slot_set] = m2_expr.ExprInt(1, 32)
                     # Replace IRDst with next instruction
                     assignments[self.ir_arch.IRDst] = m2_expr.ExprId(
-                        self.ir_arch.get_next_instr(assignblock.instr))
+                        self.ir_arch.get_next_instr(assignblock.instr), 32)
                     irs.append(AssignBlock(assignments, assignblock.instr))
                 irblocks[blk_idx] = IRBlock(irblock.label, irs)
 
@@ -72,8 +72,8 @@ class mipsCGen(CGen):
         lbl = self.get_block_post_label(block)
         out = (self.CODE_RETURN_NO_EXCEPTION % (self.label_to_jitlabel(lbl),
                                                 self.C_PC,
-                                                m2_expr.ExprId('branch_dst_irdst'),
-                                                m2_expr.ExprId('branch_dst_irdst'),
+                                                m2_expr.ExprId('branch_dst_irdst', 32),
+                                                m2_expr.ExprId('branch_dst_irdst', 32),
                                                 self.id_to_c(m2_expr.ExprInt(lbl.offset, 32)))
               ).split('\n')
         return out
diff --git a/miasm2/arch/mips32/regs.py b/miasm2/arch/mips32/regs.py
index fbd55a46..afade869 100644
--- a/miasm2/arch/mips32/regs.py
+++ b/miasm2/arch/mips32/regs.py
@@ -12,8 +12,8 @@ gen_reg('R_HI', globals())
 
 exception_flags = ExprId('exception_flags', 32)
 
-PC_init = ExprId("PC_init")
-PC_FETCH_init = ExprId("PC_FETCH_init")
+PC_init = ExprId("PC_init", 32)
+PC_FETCH_init = ExprId("PC_FETCH_init", 32)
 
 regs32_str = ["ZERO", 'AT', 'V0', 'V1'] +\
     ['A%d'%i for i in xrange(4)] +\
diff --git a/miasm2/arch/mips32/sem.py b/miasm2/arch/mips32/sem.py
index 645f9a4f..855cb6c8 100644
--- a/miasm2/arch/mips32/sem.py
+++ b/miasm2/arch/mips32/sem.py
@@ -34,7 +34,7 @@ def jal(arg1):
     "Jumps to the calculated address @arg1 and stores the return address in $RA"
     PC = arg1
     ir.IRDst = arg1
-    RA = ExprId(ir.get_next_break_label(instr))
+    RA = ExprId(ir.get_next_break_label(instr), 32)
 
 @sbuild.parse
 def jalr(arg1, arg2):
@@ -42,13 +42,13 @@ def jalr(arg1, arg2):
     address in another register @arg2"""
     PC = arg1
     ir.IRDst = arg1
-    arg2 = ExprId(ir.get_next_break_label(instr))
+    arg2 = ExprId(ir.get_next_break_label(instr), 32)
 
 @sbuild.parse
 def bal(arg1):
     PC = arg1
     ir.IRDst = arg1
-    RA = ExprId(ir.get_next_break_label(instr))
+    RA = ExprId(ir.get_next_break_label(instr), 32)
 
 @sbuild.parse
 def l_b(arg1):
@@ -75,7 +75,7 @@ def lb(arg1, arg2):
 @sbuild.parse
 def beq(arg1, arg2, arg3):
     "Branches on @arg3 if the quantities of two registers @arg1, @arg2 are eq"
-    dst = ExprId(ir.get_next_break_label(instr)) if arg1 - arg2 else arg3
+    dst = ExprId(ir.get_next_break_label(instr), 32) if arg1 - arg2 else arg3
     PC = dst
     ir.IRDst = dst
 
@@ -83,7 +83,7 @@ def beq(arg1, arg2, arg3):
 def bgez(arg1, arg2):
     """Branches on @arg2 if the quantities of register @arg1 is greater than or
     equal to zero"""
-    dst = ExprId(ir.get_next_break_label(instr)) if arg1.msb() else arg2
+    dst = ExprId(ir.get_next_break_label(instr), 32) if arg1.msb() else arg2
     PC = dst
     ir.IRDst = dst
 
@@ -91,7 +91,7 @@ def bgez(arg1, arg2):
 def bne(arg1, arg2, arg3):
     """Branches on @arg3 if the quantities of two registers @arg1, @arg2 are NOT
     equal"""
-    dst = arg3 if arg1 - arg2 else ExprId(ir.get_next_break_label(instr))
+    dst = arg3 if arg1 - arg2 else ExprId(ir.get_next_break_label(instr), 32)
     PC = dst
     ir.IRDst = dst
 
@@ -229,7 +229,7 @@ def seh(arg1, arg2):
 @sbuild.parse
 def bltz(arg1, arg2):
     """Branches on @arg2 if the register @arg1 is less than zero"""
-    dst_o = arg2 if arg1.msb() else ExprId(ir.get_next_break_label(instr))
+    dst_o = arg2 if arg1.msb() else ExprId(ir.get_next_break_label(instr), 32)
     PC = dst_o
     ir.IRDst = dst_o
 
@@ -237,7 +237,7 @@ def bltz(arg1, arg2):
 def blez(arg1, arg2):
     """Branches on @arg2 if the register @arg1 is less than or equal to zero"""
     cond = (i1(1) if arg1 else i1(0)) | arg1.msb()
-    dst_o = arg2 if cond else ExprId(ir.get_next_break_label(instr))
+    dst_o = arg2 if cond else ExprId(ir.get_next_break_label(instr), 32)
     PC = dst_o
     ir.IRDst = dst_o
 
@@ -245,7 +245,7 @@ def blez(arg1, arg2):
 def bgtz(arg1, arg2):
     """Branches on @arg2 if the register @arg1 is greater than zero"""
     cond = (i1(1) if arg1 else i1(0)) | arg1.msb()
-    dst_o = ExprId(ir.get_next_break_label(instr)) if cond else arg2
+    dst_o = ExprId(ir.get_next_break_label(instr), 32) if cond else arg2
     PC = dst_o
     ir.IRDst = dst_o
 
@@ -345,13 +345,13 @@ def c_le_d(arg1, arg2, arg3):
 
 @sbuild.parse
 def bc1t(arg1, arg2):
-    dst_o = arg2 if arg1 else ExprId(ir.get_next_break_label(instr))
+    dst_o = arg2 if arg1 else ExprId(ir.get_next_break_label(instr), 32)
     PC = dst_o
     ir.IRDst = dst_o
 
 @sbuild.parse
 def bc1f(arg1, arg2):
-    dst_o = ExprId(ir.get_next_break_label(instr)) if arg1 else arg2
+    dst_o = ExprId(ir.get_next_break_label(instr), 32) if arg1 else arg2
     PC = dst_o
     ir.IRDst = dst_o
 
diff --git a/miasm2/arch/sh4/arch.py b/miasm2/arch/sh4/arch.py
index eeafd5f5..d7ae4f12 100644
--- a/miasm2/arch/sh4/arch.py
+++ b/miasm2/arch/sh4/arch.py
@@ -7,9 +7,9 @@ from collections import defaultdict
 import miasm2.arch.sh4.regs as regs_module
 from miasm2.arch.sh4.regs import *
 
-jra = ExprId('jra')
-jrb = ExprId('jrb')
-jrc = ExprId('jrc')
+jra = ExprId('jra', 32)
+jrb = ExprId('jrb', 32)
+jrc = ExprId('jrc', 32)
 
 
 # parser helper ###########
diff --git a/miasm2/arch/x86/regs.py b/miasm2/arch/x86/regs.py
index cb7e0d7b..84590c75 100644
--- a/miasm2/arch/x86/regs.py
+++ b/miasm2/arch/x86/regs.py
@@ -251,23 +251,23 @@ reg_float_address = 'reg_float_address'
 reg_float_ds = 'reg_float_ds'
 
 
-dr0 = ExprId(reg_dr0)
-dr1 = ExprId(reg_dr1)
-dr2 = ExprId(reg_dr2)
-dr3 = ExprId(reg_dr3)
-dr4 = ExprId(reg_dr4)
-dr5 = ExprId(reg_dr5)
-dr6 = ExprId(reg_dr6)
-dr7 = ExprId(reg_dr7)
-
-cr0 = ExprId(reg_cr0)
-cr1 = ExprId(reg_cr1)
-cr2 = ExprId(reg_cr2)
-cr3 = ExprId(reg_cr3)
-cr4 = ExprId(reg_cr4)
-cr5 = ExprId(reg_cr5)
-cr6 = ExprId(reg_cr6)
-cr7 = ExprId(reg_cr7)
+dr0 = ExprId(reg_dr0, 32)
+dr1 = ExprId(reg_dr1, 32)
+dr2 = ExprId(reg_dr2, 32)
+dr3 = ExprId(reg_dr3, 32)
+dr4 = ExprId(reg_dr4, 32)
+dr5 = ExprId(reg_dr5, 32)
+dr6 = ExprId(reg_dr6, 32)
+dr7 = ExprId(reg_dr7, 32)
+
+cr0 = ExprId(reg_cr0, 32)
+cr1 = ExprId(reg_cr1, 32)
+cr2 = ExprId(reg_cr2, 32)
+cr3 = ExprId(reg_cr3, 32)
+cr4 = ExprId(reg_cr4, 32)
+cr5 = ExprId(reg_cr5, 32)
+cr6 = ExprId(reg_cr6, 32)
+cr7 = ExprId(reg_cr7, 32)
 
 mm0 = ExprId(reg_mm0, 64)
 mm1 = ExprId(reg_mm1, 64)
@@ -330,9 +330,9 @@ float_c2 = ExprId(reg_float_c2, size=1)
 float_c3 = ExprId(reg_float_c3, size=1)
 float_stack_ptr = ExprId(reg_float_stack_ptr, size=3)
 float_control = ExprId(reg_float_control, 16)
-float_eip = ExprId(reg_float_eip)
+float_eip = ExprId(reg_float_eip, 32)
 float_cs = ExprId(reg_float_cs, size=16)
-float_address = ExprId(reg_float_address)
+float_address = ExprId(reg_float_address, 32)
 float_ds = ExprId(reg_float_ds, size=16)
 
 float_st0 = ExprId("float_st0", 64)
@@ -352,14 +352,14 @@ float_replace = {fltregs32_expr[i]: float_list[i] for i in xrange(8)}
 float_replace[r_st_all.expr[0]] = float_st0
 
 
-EAX_init = ExprId('EAX_init')
-EBX_init = ExprId('EBX_init')
-ECX_init = ExprId('ECX_init')
-EDX_init = ExprId('EDX_init')
-ESI_init = ExprId('ESI_init')
-EDI_init = ExprId('EDI_init')
-ESP_init = ExprId('ESP_init')
-EBP_init = ExprId('EBP_init')
+EAX_init = ExprId('EAX_init', 32)
+EBX_init = ExprId('EBX_init', 32)
+ECX_init = ExprId('ECX_init', 32)
+EDX_init = ExprId('EDX_init', 32)
+ESI_init = ExprId('ESI_init', 32)
+EDI_init = ExprId('EDI_init', 32)
+ESP_init = ExprId('ESP_init', 32)
+EBP_init = ExprId('EBP_init', 32)
 
 
 RAX_init = ExprId('RAX_init', 64)