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-rw-r--r--miasm2/arch/arm/arch.py26
-rw-r--r--miasm2/arch/arm/sem.py2
-rw-r--r--miasm2/arch/mep/arch.py44
-rw-r--r--miasm2/arch/mep/sem.py48
-rw-r--r--miasm2/arch/mips32/arch.py24
-rw-r--r--miasm2/arch/mips32/sem.py10
-rw-r--r--miasm2/arch/msp430/arch.py44
-rw-r--r--miasm2/arch/ppc/arch.py4
-rw-r--r--miasm2/arch/ppc/sem.py8
-rw-r--r--miasm2/arch/sh4/arch.py36
-rw-r--r--miasm2/arch/x86/arch.py40
-rw-r--r--miasm2/arch/x86/sem.py70
12 files changed, 178 insertions, 178 deletions
diff --git a/miasm2/arch/arm/arch.py b/miasm2/arch/arm/arch.py
index e1b015a5..5fbaa946 100644
--- a/miasm2/arch/arm/arch.py
+++ b/miasm2/arch/arm/arch.py
@@ -385,7 +385,7 @@ class instruction_arm(instruction):
         if not isinstance(expr, ExprMem):
             return str(expr)
 
-        expr = expr.arg
+        expr = expr.ptr
         if isinstance(expr, ExprOp) and expr.op == 'wback':
             wb = True
             expr = expr.args[0]
@@ -946,7 +946,7 @@ class arm_imm8_12(arm_arg):
         e = self.expr
         if not isinstance(e, ExprMem):
             return False
-        e = e.arg
+        e = e.ptr
         if isinstance(e, ExprOp) and e.op == 'wback':
             self.parent.wback.value = 1
             e = e.args[0]
@@ -1171,7 +1171,7 @@ class arm_op2imm(arm_imm8_12):
 
         e = self.expr
         assert(isinstance(e, ExprMem))
-        e = e.arg
+        e = e.ptr
         if e.op == 'wback':
             self.parent.wback.value = 1
             e = e.args[0]
@@ -1481,7 +1481,7 @@ class arm_immed(arm_arg):
         e = self.expr
         if not isinstance(e, ExprMem):
             return False
-        e = e.arg
+        e = e.ptr
         if isinstance(e, ExprOp) and e.op == 'wback':
             self.parent.wback.value = 1
             e = e.args[0]
@@ -1570,7 +1570,7 @@ class arm_mem_rn_imm(arm_arg):
         expr = self.expr
         if not isinstance(expr, ExprMem):
             return False
-        ptr = expr.arg
+        ptr = expr.ptr
         if ptr in gpregs.expr:
             self.value = gpregs.expr.index(ptr)
         elif (isinstance(ptr, ExprOp) and
@@ -1865,7 +1865,7 @@ class arm_offpc(arm_offreg):
         else:
             self.expr = ExprMem(self.off_reg, 32)
 
-        e = self.expr.arg
+        e = self.expr.ptr
         if isinstance(e, ExprOp) and e.op == 'wback':
             self.parent.wback.value = 1
             e = e.args[0]
@@ -1875,7 +1875,7 @@ class arm_offpc(arm_offreg):
         e = self.expr
         if not isinstance(e, ExprMem):
             return False
-        e = e.arg
+        e = e.ptr
         if not (isinstance(e, ExprOp) and e.op == "preinc"):
             log.debug('cannot encode %r', e)
             return False
@@ -1949,7 +1949,7 @@ class arm_deref_reg_imm(arm_arg):
         e = self.expr
         if not isinstance(e, ExprMem):
             return False
-        e = e.arg
+        e = e.ptr
         if not (isinstance(e, ExprOp) and e.op == 'preinc'):
             log.debug('cannot encode %r', e)
             return False
@@ -2733,7 +2733,7 @@ class armt2_imm6_11l(arm_imm):
         v = self.expr.arg.arg - 4
         s = 0
         if v != sign_ext(v & ((1 << 22) - 1), 21, 32):
-            return False 
+            return False
         if v & 0x80000000:
             s = 1
         v &= (1<<22) - 1
@@ -2961,7 +2961,7 @@ class armt_op2imm(arm_imm8_12):
 
         e = self.expr
         assert(isinstance(e, ExprMem))
-        e = e.arg
+        e = e.ptr
         if e.op == 'wback':
             self.parent.wback.value = 1
             e = e.args[0]
@@ -3034,7 +3034,7 @@ class armt_deref_reg(arm_imm8_12):
     def encode(self):
         if not isinstance(self.expr, ExprMem):
             return False
-        ptr = self.expr.arg
+        ptr = self.expr.ptr
         if not ptr.is_op('preinc'):
             return False
         if len(ptr.args) != 2:
@@ -3074,7 +3074,7 @@ class armt_deref_reg_reg(arm_arg):
         expr = self.expr
         if not expr.is_mem():
             return False
-        ptr = expr.arg
+        ptr = expr.ptr
         if not ptr.is_op('+') or len(ptr.args) != 2:
             return False
         reg1, reg2 = ptr.args
@@ -3097,7 +3097,7 @@ class armt_deref_reg_reg_lsl_1(arm_reg):
         expr = self.expr
         if not expr.is_mem():
             return False
-        ptr = expr.arg
+        ptr = expr.ptr
         if not ptr.is_op('+') or len(ptr.args) != 2:
             return False
         reg1, reg_shift = ptr.args
diff --git a/miasm2/arch/arm/sem.py b/miasm2/arch/arm/sem.py
index f955b585..ac1d9ce9 100644
--- a/miasm2/arch/arm/sem.py
+++ b/miasm2/arch/arm/sem.py
@@ -761,7 +761,7 @@ def st_ld_r(ir, instr, a, a2, b, store=False, size=32, s_ext=False, z_ext=False)
     wb = False
     b = b.copy()
     postinc = False
-    b = b.arg
+    b = b.ptr
     if isinstance(b, ExprOp):
         if b.op == "wback":
             wb = True
diff --git a/miasm2/arch/mep/arch.py b/miasm2/arch/mep/arch.py
index cf4fa96d..3cfa55a6 100644
--- a/miasm2/arch/mep/arch.py
+++ b/miasm2/arch/mep/arch.py
@@ -85,11 +85,11 @@ class instruction_mep(instruction):
             else:
                 return str(expr)
 
-        elif isinstance(expr, ExprMem) and (isinstance(expr.arg, ExprId) or isinstance(expr.arg, ExprInt)):
-            return "(%s)" % expr.arg
+        elif isinstance(expr, ExprMem) and (isinstance(expr.ptr, ExprId) or isinstance(expr.ptr, ExprInt)):
+            return "(%s)" % expr.ptr
 
-        elif isinstance(expr, ExprMem) and isinstance(expr.arg, ExprOp):
-            return "0x%X(%s)" % (expr.arg.args[1].arg, expr.arg.args[0])
+        elif isinstance(expr, ExprMem) and isinstance(expr.ptr, ExprOp):
+            return "0x%X(%s)" % (expr.ptr.args[1].arg, expr.ptr.args[0])
 
         # Raise an exception if the expression type was not processed
         message = "instruction_mep.arg2str(): don't know what \
@@ -133,18 +133,18 @@ class instruction_mep(instruction):
             o += ", %s" % ExprInt2SignedString(self.args[2].arg)
 
         elif len(self.args) == 2 and self.name in ["SB", "SH", "LBU", "LB", "LH", "LW"] and \
-                isinstance(self.args[1], ExprMem) and isinstance(self.args[1].arg, ExprOp):  # Major Opcodes #12
+                isinstance(self.args[1], ExprMem) and isinstance(self.args[1].ptr, ExprOp):  # Major Opcodes #12
             # The second operand is an offset to a register
             o += " " + self.arg2str(self.args[0])
-            o += ", %s" % ExprInt2SignedString(self.args[1].arg.args[1], "0x%X")
-            o += "(%s)" % self.arg2str(self.args[1].arg.args[0])
+            o += ", %s" % ExprInt2SignedString(self.args[1].ptr.args[1], "0x%X")
+            o += "(%s)" % self.arg2str(self.args[1].ptr.args[0])
 
         elif len(self.args) == 2 and self.name in ["SWCP", "LWCP", "SMCP", "LMCP"] \
-                and isinstance(self.args[1], ExprMem) and isinstance(self.args[1].arg, ExprOp):  # Major Opcodes #12
+                and isinstance(self.args[1], ExprMem) and isinstance(self.args[1].ptr, ExprOp):  # Major Opcodes #12
             # The second operand is an offset to a register
             o += " " + self.arg2str(self.args[0])
-            o += ", %s" % ExprInt2SignedString(self.args[1].arg.args[1])
-            o += "(%s)" % self.arg2str(self.args[1].arg.args[0])
+            o += ", %s" % ExprInt2SignedString(self.args[1].ptr.args[1])
+            o += "(%s)" % self.arg2str(self.args[1].ptr.args[0])
 
         elif self.name == "SLL" and isinstance(self.args[1], ExprInt):  # Major Opcodes #6
             # The second operand is displayed in hex, not in decimal
@@ -605,11 +605,11 @@ class mep_deref_reg(mep_arg):
 
         if not isinstance(self.expr, ExprMem):
             return False
-        if not isinstance(self.expr.arg, ExprId):
+        if not isinstance(self.expr.ptr, ExprId):
             return False
 
         # Get the ExprId index, i.e. its value
-        self.value = gpr_exprs.index(self.expr.arg)
+        self.value = gpr_exprs.index(self.expr.ptr)
         return True
 
 
@@ -666,14 +666,14 @@ class mep_deref_reg_offset(mep_arg):
         # Verify the expression
         if not isinstance(self.expr, ExprMem):
             return False
-        if not isinstance(self.expr.arg, ExprOp):
+        if not isinstance(self.expr.ptr, ExprOp):
             return False
 
         # Get the integer and check the upper bound
-        v = int(self.expr.arg.args[1].arg & 0xFFFF)
+        v = int(self.expr.ptr.args[1].arg & 0xFFFF)
 
         # Encode the values
-        self.parent.reg04_deref.value = gpr_exprs.index(self.expr.arg.args[0])
+        self.parent.reg04_deref.value = gpr_exprs.index(self.expr.ptr.args[0])
         self.value = v & 0xFFFF
         return True
 
@@ -726,15 +726,15 @@ class mep_deref_sp_offset(mep_deref_reg):
         # Verify the expression
         if not isinstance(self.expr, ExprMem):
             return False
-        if not isinstance(self.expr.arg, ExprOp):
+        if not isinstance(self.expr.ptr, ExprOp):
             return False
-        if self.expr.arg.args[0] != self.implicit_reg:
+        if self.expr.ptr.args[0] != self.implicit_reg:
             return False
 
         if getattr(self.parent, "imm7_align4", False):
 
             # Get the integer and check the upper bound
-            v = int(self.expr.arg.args[1].arg)
+            v = int(self.expr.ptr.args[1].arg)
             if v > 0x80:
                 return False
 
@@ -746,7 +746,7 @@ class mep_deref_sp_offset(mep_deref_reg):
         elif getattr(self.parent, "imm7", False):
 
             # Get the integer and check the upper bound
-            v = int(self.expr.arg.args[1].arg)
+            v = int(self.expr.ptr.args[1].arg)
             if v > 0x80:
                 return False
 
@@ -758,7 +758,7 @@ class mep_deref_sp_offset(mep_deref_reg):
         elif getattr(self.parent, "disp7_align2", False):
 
             # Get the integer and check the upper bound
-            v = int(self.expr.arg.args[1].arg)
+            v = int(self.expr.ptr.args[1].arg)
             if v > 0x80:
                 return False
 
@@ -1231,11 +1231,11 @@ class mep_abs24(mep_imm):
         the other one in imm6.
         """
 
-        if not (isinstance(self.expr, ExprMem) and isinstance(self.expr.arg, ExprInt)):
+        if not (isinstance(self.expr, ExprMem) and isinstance(self.expr.ptr, ExprInt)):
             return False
 
         # Get the integer and check the upper bound
-        v = int(self.expr.arg.arg)
+        v = int(self.expr.ptr.arg)
         if v > 0xffffff:
             return False
 
diff --git a/miasm2/arch/mep/sem.py b/miasm2/arch/mep/sem.py
index 717afd7e..59960fe9 100644
--- a/miasm2/arch/mep/sem.py
+++ b/miasm2/arch/mep/sem.py
@@ -60,7 +60,7 @@ def sb(reg_src, deref_dst):
     # MemByte(Rm31..0) <- Rn7..0
     # MemByte((ZeroExt(disp7)+TP)31..0)) <- Rn7..0
     # MemByte((SignExt(disp16)+Rm)31..0) <- Rn7..0
-    mem8[deref_dst.arg] = reg_src[:8]
+    mem8[deref_dst.ptr] = reg_src[:8]
 
 
 @sbuild.parse
@@ -70,7 +70,7 @@ def sh(reg_src, deref_dst):
     # MemHword(Rm31..1||0) <- Rn15..0
     # MemHword((ZeroExt((disp7)6..1||0)+TP)31..1||0)) <- Rn15..0
     # MemHword((SignExt(disp16)+Rm)31..1||0) <- Rn15..0
-    mem16[deref_dst.arg & i32(0xFFFFFFFE)] = reg_src[:16]
+    mem16[deref_dst.ptr & i32(0xFFFFFFFE)] = reg_src[:16]
 
 
 @sbuild.parse
@@ -83,7 +83,7 @@ def sw(reg_src, deref_dst):
     # MemWord((SignExt(disp16)+Rm)31..2||00) <- Rn31..0
     # MemWord(ZeroExt((abs24)23..2||00)) - Rn31..0
 
-    mem32[deref_dst.arg & i32(0xFFFFFFFC)] = reg_src
+    mem32[deref_dst.ptr & i32(0xFFFFFFFC)] = reg_src
 
 # Without the sembuilder
 #def sw(ir, instr, reg_src, deref_reg_or_imm, deref_reg=None):
@@ -115,7 +115,7 @@ def lb(reg_dst, deref_dst):
     # Rn <- SignExt(MemByte(Rm31..0))
     # Rn <- SignExt(MemByte((ZeroExt(disp7)+TP)31..0))
     # Rn <- SignExt(MemByte((SignExt(disp16)+Rm)31..0)
-    reg_dst = mem8[deref_dst.arg].signExtend(32)
+    reg_dst = mem8[deref_dst.ptr].signExtend(32)
 
 
 @sbuild.parse
@@ -125,7 +125,7 @@ def lh(reg_dst, deref_dst):
     # Rn <- SignExt(MemHword(Rm31..1||0))
     # Rn <- SignExt(MemHword((ZeroExt((disp7)6..1||0)+TP)31..1||0)
     # Rn <- SignExt(MemHword((SignExt(disp16)+Rm)31..1||0))
-    reg_dst = mem16[deref_dst.arg & i32(0xFFFFFFFE)].signExtend(32)
+    reg_dst = mem16[deref_dst.ptr & i32(0xFFFFFFFE)].signExtend(32)
 
 
 @sbuild.parse
@@ -136,7 +136,7 @@ def lw(reg_dst, deref_dst):
     # Rn <- MemWord((ZeroExt((disp7)6..2||00)+TP)31..2||00)
     # Rn <- MemWord((SignExt(disp16)+Rm)31..2||00)
     # Rn <- MemWord(ZeroExt((abs24)23..2||00))
-    reg_dst = mem32[deref_dst.arg & i32(0xFFFFFFFC)]
+    reg_dst = mem32[deref_dst.ptr & i32(0xFFFFFFFC)]
 
 
 @sbuild.parse
@@ -146,7 +146,7 @@ def lbu(reg_dst, deref_dst):
     # Rn <- ZeroExt(MemByte(Rm31..0))
     # Rn <- ZeroExt(MemByte((ZeroExt(disp7)+TP)31..0))
     # Rn <- ZeroExt(MemByte((SignExt(disp16)+Rm)31..0))
-    reg_dst = mem8[deref_dst.arg].zeroExtend(32)
+    reg_dst = mem8[deref_dst.ptr].zeroExtend(32)
 
 
 @sbuild.parse
@@ -156,7 +156,7 @@ def lhu(reg_dst, deref_dst):
     # Rn <- ZeroExt(MemHword(Rm31..1||0))
     # Rn <- ZeroExt(MemHword((SignExt(disp16)+Rm)31..1||0))
     # Rn <- ZeroExt(MemHword((ZeroExt((disp7)6..1||0)+TP)31..1||0))
-    reg_dst = mem16[deref_dst.arg & i32(0xFFFFFFFE)].zeroExtend(32)
+    reg_dst = mem16[deref_dst.ptr & i32(0xFFFFFFFE)].zeroExtend(32)
 
 
 ### Byte/Halfword extension instructions
@@ -767,7 +767,7 @@ def bsetm(rm_deref, imm3):
     """BSETM - Bit Set Memory"""
 
     # MemByte(Rm) <- MemByte(Rm) or (1<<imm3)
-    mem8[rm_deref.arg] = ExprOp("|", mem8[rm_deref.arg], (i8(1) << imm3[:8]))
+    mem8[rm_deref.ptr] = ExprOp("|", mem8[rm_deref.ptr], (i8(1) << imm3[:8]))
 
 
 @sbuild.parse
@@ -776,7 +776,7 @@ def bclrm(rm_deref, imm3):
 
     # MemByte(Rm) <- MemByte(Rm) and ~(1<<imm3)
     shift = ExprOp("<<", i8(1), imm3[:8])
-    mem8[rm_deref.arg] = ExprOp("&", mem8[rm_deref.arg], shift.__invert__())
+    mem8[rm_deref.ptr] = ExprOp("&", mem8[rm_deref.ptr], shift.__invert__())
 
 
 @sbuild.parse
@@ -784,7 +784,7 @@ def bnotm(rm_deref, imm3):
     """BNOTM - Bit Not Memory"""
 
     # MemByte(Rm) <- MemByte(Rm) xor (1<<imm3)
-    mem8[rm_deref.arg] = ExprOp("^", mem8[rm_deref.arg], (i8(1) << imm3[:8]))
+    mem8[rm_deref.ptr] = ExprOp("^", mem8[rm_deref.ptr], (i8(1) << imm3[:8]))
 
 
 @sbuild.parse
@@ -792,7 +792,7 @@ def btstm(r0, rm_deref, imm3):
     """BTSTM - Bit Test Memory"""
 
     # R0 <- ZeroExt( MemByte(Rm) and (1<<imm3) )
-    r0 = ExprOp("&", mem8[rm_deref.arg], i8(1) << imm3[:8]).zeroExtend(32)
+    r0 = ExprOp("&", mem8[rm_deref.ptr], i8(1) << imm3[:8]).zeroExtend(32)
 
 
 @sbuild.parse
@@ -801,8 +801,8 @@ def tas(rn, rm_deref):
 
     # temp <- Rm; Rn <- ZeroExt(MemByte(temp)); MemByte(temp) <- 1
     temp = rm_deref
-    rn = mem8[temp.arg].zeroExtend(32)
-    mem8[temp.arg] = i8(1)
+    rn = mem8[temp.ptr].zeroExtend(32)
+    mem8[temp.ptr] = i8(1)
 
 
 ### Data cache option
@@ -1076,7 +1076,7 @@ def smcp(reg_src, deref_dst):
     """SMCP - Store Word to memory from a coprocessor register"""
 
     # MemDword(Rm31..3||000) <- CRn
-    mem32[deref_dst.arg & i32(0xFFFFFFF8)] = reg_src
+    mem32[deref_dst.ptr & i32(0xFFFFFFF8)] = reg_src
 
 
 @sbuild.parse
@@ -1084,7 +1084,7 @@ def lmcp(reg_dst, deref_src):
     """LMCP - Load Word from memory to a coprocessor register"""
 
     # CRn <- MemDword(Rm31..3||000)
-    reg_dst = mem32[deref_src.arg & i32(0xFFFFFFF8)]
+    reg_dst = mem32[deref_src.ptr & i32(0xFFFFFFF8)]
 
 
 @sbuild.parse
@@ -1092,8 +1092,8 @@ def swcpi(reg_src, deref_dst):
     """SWCPI - Store Word to memory, and increment the address"""
 
     # MemWord(Rm31..2||00) <- CRn 31..0; Rm<-Rm+4
-    mem32[deref_dst.arg & i32(0xFFFFFFFC)] = reg_src
-    deref_dst.arg = deref_dst.arg + i32(4)
+    mem32[deref_dst.ptr & i32(0xFFFFFFFC)] = reg_src
+    deref_dst.ptr = deref_dst.ptr + i32(4)
 
 
 @sbuild.parse
@@ -1101,8 +1101,8 @@ def lwcpi(reg_dst, deref_src):
     """LWCPI - Load Word from memory, and increment the address"""
 
     # CRn <- MemWord(Rm31..2||00); Rm<-Rm+4
-    reg_dst = mem32[deref_src.arg & i32(0xFFFFFFFC)]
-    deref_src.arg = deref_src.arg + i32(4)
+    reg_dst = mem32[deref_src.ptr & i32(0xFFFFFFFC)]
+    deref_src.ptr = deref_src.ptr + i32(4)
 
 
 @sbuild.parse
@@ -1110,8 +1110,8 @@ def smcpi(reg_src, deref_dst):
     """SMCPI - Store Word to memory, and increment the address"""
 
     # MemDword(Rm31..3||000) <- CRn; Rm<-Rm+8
-    mem32[deref_dst.arg & i32(0xFFFFFFF8)] = reg_src
-    deref_dst.arg = deref_dst.arg + i32(8)
+    mem32[deref_dst.ptr & i32(0xFFFFFFF8)] = reg_src
+    deref_dst.ptr = deref_dst.ptr + i32(8)
 
 
 @sbuild.parse
@@ -1119,8 +1119,8 @@ def lmcpi(reg_dst, deref_src):
     """LMCPI - Load Word from memory, and increment the address"""
 
     # CRn <- MemDword(Rm31..3||000); Rm<-Rm+8
-    reg_dst = mem32[deref_src.arg & i32(0xFFFFFFFC)]
-    deref_src.arg = deref_src.arg + i32(8)
+    reg_dst = mem32[deref_src.ptr & i32(0xFFFFFFFC)]
+    deref_src.ptr = deref_src.ptr + i32(8)
 
 
 ### IR MeP definitions
diff --git a/miasm2/arch/mips32/arch.py b/miasm2/arch/mips32/arch.py
index f963737e..75a1aff0 100644
--- a/miasm2/arch/mips32/arch.py
+++ b/miasm2/arch/mips32/arch.py
@@ -69,7 +69,7 @@ class instruction_mips32(cpu.instruction):
             else:
                 return str(expr)
         assert(isinstance(expr, ExprMem))
-        arg = expr.arg
+        arg = expr.ptr
         if isinstance(arg, ExprId):
             return "(%s)"%arg
         assert(len(arg.args) == 2 and arg.op == '+')
@@ -394,13 +394,13 @@ class mips32_dreg_imm(mips32_arg):
         e = self.expr
         if not isinstance(e, ExprMem):
             return False
-        arg = e.arg
-        if isinstance(arg, ExprId):
+        ptr = e.ptr
+        if isinstance(ptr, ExprId):
             self.parent.imm.expr = ExprInt(0, 32)
-            r = arg
-        elif len(arg.args) == 2 and arg.op == "+":
-            self.parent.imm.expr = arg.args[1]
-            r = arg.args[0]
+            r = ptr
+        elif len(ptr.args) == 2 and ptr.op == "+":
+            self.parent.imm.expr = ptr.args[1]
+            r = ptr.args[0]
         else:
             return False
         self.value = gpregs.expr.index(r)
@@ -409,11 +409,11 @@ class mips32_dreg_imm(mips32_arg):
     @staticmethod
     def arg2str(expr, index=None):
         assert(isinstance(expr, ExprMem))
-        arg = expr.arg
-        if isinstance(arg, ExprId):
-            return "(%s)"%arg
-        assert(len(arg.args) == 2 and arg.op == '+')
-        return "%s(%s)"%(arg.args[1], arg.args[0])
+        ptr = expr.ptr
+        if isinstance(ptr, ExprId):
+            return "(%s)"%ptr
+        assert(len(ptr.args) == 2 and ptr.op == '+')
+        return "%s(%s)"%(ptr.args[1], ptr.args[0])
 
 class mips32_esize(mips32_imm, mips32_arg):
     def decode(self, v):
diff --git a/miasm2/arch/mips32/sem.py b/miasm2/arch/mips32/sem.py
index a603e7c3..a57d2200 100644
--- a/miasm2/arch/mips32/sem.py
+++ b/miasm2/arch/mips32/sem.py
@@ -64,18 +64,18 @@ def l_b(arg1):
 def lbu(arg1, arg2):
     """A byte is loaded (unsigned extended) into a register @arg1 from the
     specified address @arg2."""
-    arg1 = mem8[arg2.arg].zeroExtend(32)
+    arg1 = mem8[arg2.ptr].zeroExtend(32)
 
 @sbuild.parse
 def lhu(arg1, arg2):
     """A word is loaded (unsigned extended) into a register @arg1 from the
     specified address @arg2."""
-    arg1 = mem16[arg2.arg].zeroExtend(32)
+    arg1 = mem16[arg2.ptr].zeroExtend(32)
 
 @sbuild.parse
 def lb(arg1, arg2):
     "A byte is loaded into a register @arg1 from the specified address @arg2."
-    arg1 = mem8[arg2.arg].signExtend(32)
+    arg1 = mem8[arg2.ptr].signExtend(32)
 
 @sbuild.parse
 def beq(arg1, arg2, arg3):
@@ -174,11 +174,11 @@ def l_sub(arg1, arg2, arg3):
 def sb(arg1, arg2):
     """The least significant byte of @arg1 is stored at the specified address
     @arg2."""
-    mem8[arg2.arg] = arg1[:8]
+    mem8[arg2.ptr] = arg1[:8]
 
 @sbuild.parse
 def sh(arg1, arg2):
-    mem16[arg2.arg] = arg1[:16]
+    mem16[arg2.ptr] = arg1[:16]
 
 @sbuild.parse
 def movn(arg1, arg2, arg3):
diff --git a/miasm2/arch/msp430/arch.py b/miasm2/arch/msp430/arch.py
index ecf4cb13..a8f75f39 100644
--- a/miasm2/arch/msp430/arch.py
+++ b/miasm2/arch/msp430/arch.py
@@ -115,15 +115,15 @@ class instruction_msp430(instruction):
         elif isinstance(expr, ExprOp) and expr.op == "autoinc":
             o = "@%s+" % str(expr.args[0])
         elif isinstance(expr, ExprMem):
-            if isinstance(expr.arg, ExprId):
+            if isinstance(expr.ptr, ExprId):
                 if index == 0:
-                    o = "@%s" % expr.arg
+                    o = "@%s" % expr.ptr
                 else:
-                    o = "0x0(%s)" % expr.arg
-            elif isinstance(expr.arg, ExprInt):
-                o = "@%s" % expr.arg
-            elif isinstance(expr.arg, ExprOp):
-                o = "%s(%s)" % (expr.arg.args[1], expr.arg.args[0])
+                    o = "0x0(%s)" % expr.ptr
+            elif isinstance(expr.ptr, ExprInt):
+                o = "@%s" % expr.ptr
+            elif isinstance(expr.ptr, ExprOp):
+                o = "%s(%s)" % (expr.ptr.args[1], expr.ptr.args[0])
         else:
             raise NotImplementedError('unknown instance expr = %s' % type(expr))
         return o
@@ -388,20 +388,20 @@ class msp430_sreg_arg(reg_noarg, msp430_arg):
                 self.value = 0
                 self.parent.off_s.value = v
         elif isinstance(e, ExprMem):
-            if isinstance(e.arg, ExprId):
+            if isinstance(e.ptr, ExprId):
                 self.parent.a_s.value = 0b10
-                self.value = self.reg_info.expr.index(e.arg)
-            elif isinstance(e.arg, ExprInt):
+                self.value = self.reg_info.expr.index(e.ptr)
+            elif isinstance(e.ptr, ExprInt):
                 self.parent.a_s.value = 0b01
                 self.value = self.reg_info.expr.index(SR)
-                self.parent.off_s.value = int(e.arg)
-            elif isinstance(e.arg, ExprOp):
+                self.parent.off_s.value = int(e.ptr)
+            elif isinstance(e.ptr, ExprOp):
                 self.parent.a_s.value = 0b01
-                self.value = self.reg_info.expr.index(e.arg.args[0])
-                self.parent.off_s.value = int(e.arg.args[1])
+                self.value = self.reg_info.expr.index(e.ptr.args[0])
+                self.parent.off_s.value = int(e.ptr.args[1])
             else:
                 raise NotImplementedError(
-                    'unknown instance e.arg = %s' % type(e.arg))
+                    'unknown instance e.ptr = %s' % type(e.ptr))
         elif isinstance(e, ExprOp) and e.op == "autoinc":
             self.parent.a_s.value = 0b11
             self.value = self.reg_info.expr.index(e.args[0])
@@ -443,15 +443,15 @@ class msp430_dreg_arg(msp430_sreg_arg):
             self.parent.a_d.value = 0
             self.value = self.reg_info.expr.index(e)
         elif isinstance(e, ExprMem):
-            if isinstance(e.arg, ExprId):
-                r, i = e.arg, ExprInt(0, 16)
-            elif isinstance(e.arg, ExprOp):
-                r, i = e.arg.args[0], e.arg.args[1]
-            elif isinstance(e.arg, ExprInt):
-                r, i = SR, e.arg
+            if isinstance(e.ptr, ExprId):
+                r, i = e.ptr, ExprInt(0, 16)
+            elif isinstance(e.ptr, ExprOp):
+                r, i = e.ptr.args[0], e.ptr.args[1]
+            elif isinstance(e.ptr, ExprInt):
+                r, i = SR, e.ptr
             else:
                 raise NotImplementedError(
-                    'unknown instance e.arg = %s' % type(e.arg))
+                    'unknown instance e.arg = %s' % type(e.ptr))
             self.parent.a_d.value = 1
             self.value = self.reg_info.expr.index(r)
             self.parent.off_d.value = int(i)
diff --git a/miasm2/arch/ppc/arch.py b/miasm2/arch/ppc/arch.py
index f198312e..37acc1c5 100644
--- a/miasm2/arch/ppc/arch.py
+++ b/miasm2/arch/ppc/arch.py
@@ -77,7 +77,7 @@ class instruction_ppc(instruction):
         if isinstance(e, ExprId) or isinstance(e, ExprInt):
             return str(e)
         elif isinstance(e, ExprMem):
-            addr = e.arg
+            addr = e.ptr
             if isinstance(addr, ExprInt) or isinstance(addr, ExprId):
                 out = '(%s)'%addr
             elif isinstance(addr, ExprOp):
@@ -509,7 +509,7 @@ class ppc_deref32(ppc_arg):
         e = self.expr
         if not isinstance(e, ExprMem):
             return False
-        addr = e.arg
+        addr = e.ptr
         if isinstance(addr, ExprId) or isinstance(addr, ExprInt):
             addr = addr + ExprInt(0, 32)
         elif not isinstance(addr, ExprOp):
diff --git a/miasm2/arch/ppc/sem.py b/miasm2/arch/ppc/sem.py
index 3a8ec244..969a8002 100644
--- a/miasm2/arch/ppc/sem.py
+++ b/miasm2/arch/ppc/sem.py
@@ -250,7 +250,7 @@ def mn_do_load(ir, instr, arg1, arg2, arg3=None):
     if arg3 is None:
         assert isinstance(arg2, ExprMem)
 
-        address = arg2.arg
+        address = arg2.ptr
     else:
         address = arg2 + arg3
 
@@ -267,7 +267,7 @@ def mn_do_load(ir, instr, arg1, arg2, arg3=None):
     ret.append(ExprAssign(arg1, src))
     if has_u:
         if arg3 is None:
-            ret.append(ExprAssign(arg2.arg.args[0], address))
+            ret.append(ExprAssign(arg2.ptr.args[0], address))
         else:
             ret.append(ExprAssign(arg2, address))
 
@@ -586,7 +586,7 @@ def mn_do_store(ir, instr, arg1, arg2, arg3=None):
     if arg3 is None:
         assert isinstance(arg2, ExprMem)
 
-        address = arg2.arg
+        address = arg2.ptr
     else:
         address = arg2 + arg3
 
@@ -599,7 +599,7 @@ def mn_do_store(ir, instr, arg1, arg2, arg3=None):
     ret.append(ExprAssign(dest, src))
     if has_u:
         if arg3 is None:
-            ret.append(ExprAssign(arg2.arg.args[0], address))
+            ret.append(ExprAssign(arg2.ptr.args[0], address))
         else:
             ret.append(ExprAssign(arg2, address))
 
diff --git a/miasm2/arch/sh4/arch.py b/miasm2/arch/sh4/arch.py
index d5e9820e..c6dea0d6 100644
--- a/miasm2/arch/sh4/arch.py
+++ b/miasm2/arch/sh4/arch.py
@@ -169,7 +169,7 @@ class sh4_dgpreg(sh4_arg):
         start, stop = super(sh4_dgpreg, self).fromstring(text, loc_db, parser_result)
         if start is None or self.expr == [None]:
             return start, stop
-        self.expr = ExprMem(self.expr.arg, self.sz)
+        self.expr = ExprMem(self.expr.ptr, self.sz)
         return start, stop
 
     def decode(self, v):
@@ -181,9 +181,9 @@ class sh4_dgpreg(sh4_arg):
         e = self.expr
         if not isinstance(e, ExprMem):
             return False
-        if not isinstance(e.arg, ExprId):
+        if not isinstance(e.ptr, ExprId):
             return False
-        v = gpregs.expr.index(e.arg)
+        v = gpregs.expr.index(e.ptr)
         self.value = v
         return True
 
@@ -195,9 +195,9 @@ class sh4_dgpregpinc(sh4_arg):
         start, stop = super(sh4_dgpregpinc, self).fromstring(text, loc_db, parser_result)
         if self.expr == [None]:
             return None, None
-        if not isinstance(self.expr.arg, ExprOp):
+        if not isinstance(self.expr.ptr, ExprOp):
             return None, None
-        if self.expr.arg.op != self.op:
+        if self.expr.ptr.op != self.op:
             return None, None
         return start, stop
 
@@ -211,7 +211,7 @@ class sh4_dgpregpinc(sh4_arg):
         e = self.expr
         if not isinstance(e, ExprMem):
             return False
-        e = e.arg
+        e = e.ptr
         res = match_expr(e, ExprOp(self.op, jra), [jra])
         if not res:
             return False
@@ -246,10 +246,10 @@ class sh4_dgpreg_imm(sh4_dgpreg):
         s = self.sz
         if not isinstance(e, ExprMem):
             return False
-        if isinstance(e.arg, ExprId):
-            v = gpregs.expr.index(e.arg)
+        if isinstance(e.ptr, ExprId):
+            v = gpregs.expr.index(e.ptr)
             p.disp.value = 0
-        elif isinstance(e.arg, ExprOp):
+        elif isinstance(e.ptr, ExprOp):
             res = match_expr(e, ExprMem(jra + jrb, self.sz), [jra, jrb])
             if not res:
                 return False
@@ -415,20 +415,20 @@ class instruction_sh4(instruction):
             else:
                 return str(expr)
         assert(isinstance(expr, ExprMem))
-        expr = expr.arg
+        ptr = expr.ptr
 
-        if isinstance(expr, ExprOp):
-            if expr.op == "predec":
-                s = '-%s' % expr.args[0]
-            elif expr.op == "postinc":
-                s = '%s+' % expr.args[0]
+        if isinstance(ptr, ExprOp):
+            if ptr.op == "predec":
+                s = '-%s' % ptr.args[0]
+            elif ptr.op == "postinc":
+                s = '%s+' % ptr.args[0]
             else:
                 s = ','.join([str(x).replace('(', '').replace(')', '')
-                              for x in expr.args])
+                              for x in ptr.args])
                 s = "(%s)"%s
             s = "@%s" % s
-        elif isinstance(expr, ExprId):
-            s = "@%s" % expr
+        elif isinstance(ptr, ExprId):
+            s = "@%s" % ptr
         else:
             raise NotImplementedError('zarb arg2str')
         return s
diff --git a/miasm2/arch/x86/arch.py b/miasm2/arch/x86/arch.py
index 3b2117f4..025751a6 100644
--- a/miasm2/arch/x86/arch.py
+++ b/miasm2/arch/x86/arch.py
@@ -577,10 +577,10 @@ class instruction_x86(instruction):
             sz = SIZE2MEMPREFIX[expr.size]
             segm = ""
             if expr.is_mem_segm():
-                segm = "%s:" % expr.arg.args[0]
-                expr = expr.arg.args[1]
+                segm = "%s:" % expr.ptr.args[0]
+                expr = expr.ptr.args[1]
             else:
-                expr = expr.arg
+                expr = expr.ptr
             if isinstance(expr, ExprOp):
                 s = str(expr).replace('(', '').replace(')', '')
             else:
@@ -766,7 +766,7 @@ class mn_x86(cls_mn):
                     continue
                 m = a.expr
                 a.expr = ExprMem(
-                    ExprOp('segm', enc2segm[self.g2.value], m.arg), m.size)
+                    ExprOp('segm', enc2segm[self.g2.value], m.ptr), m.size)
         return self
 
     def dup_info(self, infos):
@@ -1701,15 +1701,15 @@ SIZE2BNDREG = {64:gpregs_mm,
 def parse_mem(expr, parent, w8, sx=0, xmm=0, mm=0, bnd=0):
     dct_expr = {}
     opmode = parent.v_opmode()
-    if expr.is_mem_segm() and expr.arg.args[0].is_int():
+    if expr.is_mem_segm() and expr.ptr.args[0].is_int():
         return None, None, False
 
     if expr.is_mem_segm():
-        segm = expr.arg.args[0]
-        ptr = expr.arg.args[1]
+        segm = expr.ptr.args[0]
+        ptr = expr.ptr.args[1]
     else:
         segm = None
-        ptr = expr.arg
+        ptr = expr.ptr
 
     dct_expr[f_isad] = True
     ad_size = ptr.size
@@ -2178,9 +2178,9 @@ class x86_rm_sd(x86_rm_arg):
         if not isinstance(expr, ExprMem):
             return False
         if self.get_s_value() == 0:
-            expr = ExprMem(expr.arg, 32)
+            expr = ExprMem(expr.ptr, 32)
         else:
-            expr = ExprMem(expr.arg, self.out_size)
+            expr = ExprMem(expr.ptr, self.out_size)
         self.expr = expr
         return self.expr is not None
 
@@ -2223,7 +2223,7 @@ class x86_rm_08(x86_rm_arg):
         if not isinstance(expr, ExprMem):
             self.expr = expr
             return True
-        self.expr = ExprMem(expr.arg, self.msize)
+        self.expr = ExprMem(expr.ptr, self.msize)
         return self.expr is not None
 
     def encode(self):
@@ -2243,7 +2243,7 @@ class x86_rm_reg_m08(x86_rm_arg):
             return ret
         if not isinstance(self.expr, ExprMem):
             return True
-        self.expr = ExprMem(self.expr.arg, self.msize)
+        self.expr = ExprMem(self.expr.ptr, self.msize)
         return self.expr is not None
 
     def encode(self):
@@ -2251,7 +2251,7 @@ class x86_rm_reg_m08(x86_rm_arg):
             raise StopIteration
         p = self.parent
         if isinstance(self.expr, ExprMem):
-            expr = ExprMem(self.expr.arg, 32)
+            expr = ExprMem(self.expr.ptr, 32)
         else:
             expr = self.expr
         v_cand, segm, ok = expr2modrm(expr, p, 1, 0, 0, 0)
@@ -2270,7 +2270,7 @@ class x86_rm_m64(x86_rm_arg):
         expr = modrm2expr(xx, p, 1)
         if not isinstance(expr, ExprMem):
             return False
-        self.expr = ExprMem(expr.arg, self.msize)
+        self.expr = ExprMem(expr.ptr, self.msize)
         return self.expr is not None
 
     def encode(self):
@@ -2294,7 +2294,7 @@ class x86_rm_m80(x86_rm_m64):
         mode = p.mode
         if mode == 64:
             mode = 32
-        self.expr = ExprMem(self.expr.arg, mode)
+        self.expr = ExprMem(self.expr.ptr, mode)
         v_cand, segm, ok = expr2modrm(self.expr, p, 1)
         for x in self.gen_cand(v_cand, p.v_admode()):
             yield x
@@ -2337,7 +2337,7 @@ class x86_rm_mm(x86_rm_m80):
             if self.msize is None:
                 return False
             if expr.size != self.msize:
-                expr = ExprMem(expr.arg, self.msize)
+                expr = ExprMem(expr.ptr, self.msize)
         self.expr = expr
         return True
 
@@ -2354,9 +2354,9 @@ class x86_rm_mm(x86_rm_m80):
             mode = 32
         if isinstance(expr, ExprMem):
             if self.is_xmm:
-                expr = ExprMem(expr.arg, 128)
+                expr = ExprMem(expr.ptr, 128)
             elif self.is_mm:
-                expr = ExprMem(expr.arg, 64)
+                expr = ExprMem(expr.ptr, 64)
 
         v_cand, segm, ok = expr2modrm(expr, p, 0, 0, self.is_xmm, self.is_mm,
                                       self.is_bnd)
@@ -3041,10 +3041,10 @@ class bs_movoff(x86_arg):
 
     def encode(self):
         p = self.parent
-        if not isinstance(self.expr, ExprMem) or not isinstance(self.expr.arg, ExprInt):
+        if not isinstance(self.expr, ExprMem) or not isinstance(self.expr.ptr, ExprInt):
             raise StopIteration
         self.l = p.v_admode()
-        v = int(self.expr.arg)
+        v = int(self.expr.ptr)
         mask = ((1 << self.l) - 1)
         if v != mask & v:
             raise StopIteration
diff --git a/miasm2/arch/x86/sem.py b/miasm2/arch/x86/sem.py
index 727d0bc2..a3589344 100644
--- a/miasm2/arch/x86/sem.py
+++ b/miasm2/arch/x86/sem.py
@@ -301,7 +301,7 @@ def fix_mem_args_size(instr, *args):
         if not arg.is_mem():
             out.append(arg)
             continue
-        ptr = arg.arg
+        ptr = arg.ptr
         size = arg.size
         if ptr.is_op('segm'):
             ptr = m2_expr.ExprOp(
@@ -320,7 +320,7 @@ def mem2double(instr, arg):
     if isinstance(arg, m2_expr.ExprMem):
         if arg.size > 64:
             # TODO: move to 80 bits
-            arg = m2_expr.ExprMem(expraddr(instr.mode, arg.arg), size=64)
+            arg = m2_expr.ExprMem(expraddr(instr.mode, arg.ptr), size=64)
         return m2_expr.ExprOp('sint_to_fp', arg.signExtend(64))
     else:
         return arg
@@ -439,7 +439,7 @@ def movsx(_, instr, dst, src):
 
 
 def lea(_, instr, dst, src):
-    ptr = src.arg
+    ptr = src.ptr
     if src.is_mem_segm():
         # Do not use segmentation here
         ptr = ptr.args[1]
@@ -2050,10 +2050,10 @@ def movsd(_, instr, dst, src):
         src = src[:64]
         dst = dst[:64]
     elif dst.is_mem() and src.is_id():
-        dst = m2_expr.ExprMem(dst.arg, 64)
+        dst = m2_expr.ExprMem(dst.ptr, 64)
         src = src[:64]
     else:
-        src = m2_expr.ExprMem(src.arg, 64)
+        src = m2_expr.ExprMem(src.ptr, 64)
         # Erase dst high bits
         src = src.zeroExtend(dst.size)
     return [m2_expr.ExprAssign(dst, src)], []
@@ -2621,22 +2621,22 @@ def fnstenv(ir, instr, dst):
     # The behaviour in 64bit is identical to 32 bit
     # This will truncate addresses
     size = min(32, s)
-    ad = ir.ExprMem(dst.arg, size=16)
+    ad = ir.ExprMem(dst.ptr, size=16)
     e.append(m2_expr.ExprAssign(ad, float_control))
-    ad = ir.ExprMem(dst.arg + m2_expr.ExprInt(size /
-                                              8 * 1, dst.arg.size), size=16)
+    ad = ir.ExprMem(dst.ptr + m2_expr.ExprInt(size /
+                                              8 * 1, dst.ptr.size), size=16)
     e.append(m2_expr.ExprAssign(ad, status_word))
-    ad = ir.ExprMem(dst.arg + m2_expr.ExprInt(size /
-                                              8 * 3, dst.arg.size), size=size)
+    ad = ir.ExprMem(dst.ptr + m2_expr.ExprInt(size /
+                                              8 * 3, dst.ptr.size), size=size)
     e.append(m2_expr.ExprAssign(ad, float_eip[:size]))
-    ad = ir.ExprMem(dst.arg + m2_expr.ExprInt(size /
-                                              8 * 4, dst.arg.size), size=16)
+    ad = ir.ExprMem(dst.ptr + m2_expr.ExprInt(size /
+                                              8 * 4, dst.ptr.size), size=16)
     e.append(m2_expr.ExprAssign(ad, float_cs))
-    ad = ir.ExprMem(dst.arg + m2_expr.ExprInt(size /
-                                              8 * 5, dst.arg.size), size=size)
+    ad = ir.ExprMem(dst.ptr + m2_expr.ExprInt(size /
+                                              8 * 5, dst.ptr.size), size=size)
     e.append(m2_expr.ExprAssign(ad, float_address[:size]))
-    ad = ir.ExprMem(dst.arg + m2_expr.ExprInt(size /
-                                              8 * 6, dst.arg.size), size=16)
+    ad = ir.ExprMem(dst.ptr + m2_expr.ExprInt(size /
+                                              8 * 6, dst.ptr.size), size=16)
     e.append(m2_expr.ExprAssign(ad, float_ds))
     return e, []
 
@@ -2651,11 +2651,11 @@ def fldenv(ir, instr, src):
     size = min(32, s)
 
     # Float control
-    ad = ir.ExprMem(src.arg, size=16)
+    ad = ir.ExprMem(src.ptr, size=16)
     e.append(m2_expr.ExprAssign(float_control, ad))
 
     # Status word
-    ad = ir.ExprMem(src.arg + m2_expr.ExprInt(size / 8 * 1, size=src.arg.size),
+    ad = ir.ExprMem(src.ptr + m2_expr.ExprInt(size / 8 * 1, size=src.ptr.size),
                     size=16)
     e += [m2_expr.ExprAssign(x, y) for x, y in ((float_c0, ad[8:9]),
                                              (float_c1, ad[9:10]),
@@ -2669,8 +2669,8 @@ def fldenv(ir, instr, src):
                            (4, float_cs),
                            (5, float_address[:size]),
                            (6, float_ds)):
-        ad = ir.ExprMem(src.arg + m2_expr.ExprInt(size / 8 * offset,
-                                                  size=src.arg.size),
+        ad = ir.ExprMem(src.ptr + m2_expr.ExprInt(size / 8 * offset,
+                                                  size=src.ptr.size),
                         size=target.size)
         e.append(m2_expr.ExprAssign(target, ad))
 
@@ -3249,7 +3249,7 @@ def sidt(ir, instr, dst):
     e = []
     if not isinstance(dst, m2_expr.ExprMem) or dst.size != 32:
         raise ValueError('not exprmem 32bit instance!!')
-    ptr = dst.arg
+    ptr = dst.ptr
     LOG_X86_SEM.warning("DEFAULT SIDT ADDRESS %s!!", str(dst))
     e.append(m2_expr.ExprAssign(ir.ExprMem(ptr, 32),
                              m2_expr.ExprInt(0xe40007ff, 32)))
@@ -3426,7 +3426,7 @@ def bittest_get(ir, instr, src, index):
     if isinstance(src, m2_expr.ExprMem):
         b_mask = {16: 4, 32: 5, 64: 6}
         b_decal = {16: 1, 32: 3, 64: 7}
-        ptr = src.arg
+        ptr = src.ptr
         segm = src.is_mem_segm()
         if segm:
             ptr = ptr.args[1]
@@ -3439,7 +3439,7 @@ def bittest_get(ir, instr, src, index):
 
         addr = ptr + off_byte
         if segm:
-            addr = ir.gen_segm_expr(src.arg.args[0], addr)
+            addr = ir.gen_segm_expr(src.ptr.args[0], addr)
 
         d = ir.ExprMem(addr, src.size)
     else:
@@ -3537,8 +3537,8 @@ def cmpxchg16b(arg1):
 
 def lds(ir, instr, dst, src):
     e = []
-    e.append(m2_expr.ExprAssign(dst, ir.ExprMem(src.arg, size=dst.size)))
-    DS_value = ir.ExprMem(src.arg + m2_expr.ExprInt(dst.size / 8, src.arg.size),
+    e.append(m2_expr.ExprAssign(dst, ir.ExprMem(src.ptr, size=dst.size)))
+    DS_value = ir.ExprMem(src.ptr + m2_expr.ExprInt(dst.size / 8, src.ptr.size),
                           size=16)
     e.append(m2_expr.ExprAssign(DS, DS_value))
     return e, []
@@ -3546,8 +3546,8 @@ def lds(ir, instr, dst, src):
 
 def les(ir, instr, dst, src):
     e = []
-    e.append(m2_expr.ExprAssign(dst, ir.ExprMem(src.arg, size=dst.size)))
-    ES_value = ir.ExprMem(src.arg + m2_expr.ExprInt(dst.size / 8, src.arg.size),
+    e.append(m2_expr.ExprAssign(dst, ir.ExprMem(src.ptr, size=dst.size)))
+    ES_value = ir.ExprMem(src.ptr + m2_expr.ExprInt(dst.size / 8, src.ptr.size),
                           size=16)
     e.append(m2_expr.ExprAssign(ES, ES_value))
     return e, []
@@ -3555,8 +3555,8 @@ def les(ir, instr, dst, src):
 
 def lss(ir, instr, dst, src):
     e = []
-    e.append(m2_expr.ExprAssign(dst, ir.ExprMem(src.arg, size=dst.size)))
-    SS_value = ir.ExprMem(src.arg + m2_expr.ExprInt(dst.size / 8, src.arg.size),
+    e.append(m2_expr.ExprAssign(dst, ir.ExprMem(src.ptr, size=dst.size)))
+    SS_value = ir.ExprMem(src.ptr + m2_expr.ExprInt(dst.size / 8, src.ptr.size),
                           size=16)
     e.append(m2_expr.ExprAssign(SS, SS_value))
     return e, []
@@ -3564,8 +3564,8 @@ def lss(ir, instr, dst, src):
 
 def lfs(ir, instr, dst, src):
     e = []
-    e.append(m2_expr.ExprAssign(dst, ir.ExprMem(src.arg, size=dst.size)))
-    FS_value = ir.ExprMem(src.arg + m2_expr.ExprInt(dst.size / 8, src.arg.size),
+    e.append(m2_expr.ExprAssign(dst, ir.ExprMem(src.ptr, size=dst.size)))
+    FS_value = ir.ExprMem(src.ptr + m2_expr.ExprInt(dst.size / 8, src.ptr.size),
                           size=16)
     e.append(m2_expr.ExprAssign(FS, FS_value))
     return e, []
@@ -3573,8 +3573,8 @@ def lfs(ir, instr, dst, src):
 
 def lgs(ir, instr, dst, src):
     e = []
-    e.append(m2_expr.ExprAssign(dst, ir.ExprMem(src.arg, size=dst.size)))
-    GS_value = ir.ExprMem(src.arg + m2_expr.ExprInt(dst.size / 8, src.arg.size),
+    e.append(m2_expr.ExprAssign(dst, ir.ExprMem(src.ptr, size=dst.size)))
+    GS_value = ir.ExprMem(src.ptr + m2_expr.ExprInt(dst.size / 8, src.ptr.size),
                           size=16)
     e.append(m2_expr.ExprAssign(GS, GS_value))
     return e, []
@@ -3732,7 +3732,7 @@ def __vec_vertical_instr_gen(op, elt_size, sem, apply_on_output):
     def vec_instr(ir, instr, dst, src):
         e = []
         if isinstance(src, m2_expr.ExprMem):
-            src = ir.ExprMem(src.arg, dst.size)
+            src = ir.ExprMem(src.ptr, dst.size)
         reg_size = dst.size
         e.append(m2_expr.ExprAssign(dst, sem(op, elt_size, reg_size, dst, src,
                                           apply_on_output)))
@@ -5642,7 +5642,7 @@ class ir_x86_16(IntermediateRepresentation):
             for i, a in enumerate(args):
                 if a.is_mem() and not a.is_mem_segm():
                     args[i] = self.ExprMem(m2_expr.ExprOp('segm', my_ss,
-                                                          a.arg), a.size)
+                                                          a.ptr), a.size)
 
         if not instr.name.lower() in mnemo_func:
             raise NotImplementedError(