diff options
Diffstat (limited to 'miasm2/arch')
| -rw-r--r-- | miasm2/arch/aarch64/arch.py | 2 | ||||
| -rw-r--r-- | miasm2/arch/arm/sem.py | 13 | ||||
| -rw-r--r-- | miasm2/arch/ppc/arch.py | 2 | ||||
| -rw-r--r-- | miasm2/arch/ppc/sem.py | 6 | ||||
| -rw-r--r-- | miasm2/arch/x86/arch.py | 7 | ||||
| -rw-r--r-- | miasm2/arch/x86/sem.py | 8 |
6 files changed, 9 insertions, 29 deletions
diff --git a/miasm2/arch/aarch64/arch.py b/miasm2/arch/aarch64/arch.py index 15a7bd77..598aca83 100644 --- a/miasm2/arch/aarch64/arch.py +++ b/miasm2/arch/aarch64/arch.py @@ -357,7 +357,7 @@ class instruction_aarch64(instruction): raise NotImplementedError("bad op") def dstflow(self): - return self.name in self.name in BRCOND + ["B", "BL", "BR", "BLR"] + return self.name in BRCOND + ["B", "BL", "BR", "BLR"] def mnemo_flow_to_dst_index(self, name): if self.name in ['CBZ', 'CBNZ']: diff --git a/miasm2/arch/arm/sem.py b/miasm2/arch/arm/sem.py index 2cfc2a17..600ad586 100644 --- a/miasm2/arch/arm/sem.py +++ b/miasm2/arch/arm/sem.py @@ -283,7 +283,8 @@ def rsb(ir, instr, a, b, c=None): e = [] if c is None: b, c = a, b - r = c - b + arg1, arg2 = c, b + r = arg1 - arg2 e.append(ExprAff(a, r)) dst = get_dst(a) if dst is not None: @@ -297,10 +298,8 @@ def rsbs(ir, instr, a, b, c=None): b, c = a, b arg1, arg2 = c, b r = arg1 - arg2 - e += update_flag_arith_sub_zn(arg1, arg2) e += update_flag_arith_sub_co(arg1, arg2) - e.append(ExprAff(a, r)) dst = get_dst(a) if dst is not None: @@ -398,11 +397,8 @@ def l_cmp(ir, instr, a, b, c=None): if c is None: b, c = a, b arg1, arg2 = b, c - r = b - c - e += update_flag_arith_sub_zn(arg1, arg2) e += update_flag_arith_sub_co(arg1, arg2) - return e, [] @@ -411,11 +407,8 @@ def cmn(ir, instr, a, b, c=None): if c is None: b, c = a, b arg1, arg2 = b, c - r = b + c - e += update_flag_arith_add_zn(arg1, arg2) e += update_flag_arith_add_co(arg1, arg2) - return e, [] @@ -448,7 +441,7 @@ def orrs(ir, instr, a, b, c=None): if c is None: b, c = a, b arg1, arg2 = b, c - r = b | c + r = arg1 | arg2 e += [ExprAff(zf, ExprOp('FLAG_EQ', r))] e += update_flag_nf(r) diff --git a/miasm2/arch/ppc/arch.py b/miasm2/arch/ppc/arch.py index c100cde3..f198312e 100644 --- a/miasm2/arch/ppc/arch.py +++ b/miasm2/arch/ppc/arch.py @@ -313,7 +313,7 @@ class ppc_gpreg_or_0(ppc_reg): parser = reg_info.parser def decode(self, v): - ret = super(ppc_reg, self).decode(v) + ret = super(ppc_gpreg_or_0, self).decode(v) if ret == False: return False reg = self.expr diff --git a/miasm2/arch/ppc/sem.py b/miasm2/arch/ppc/sem.py index 3c885d12..82a662c2 100644 --- a/miasm2/arch/ppc/sem.py +++ b/miasm2/arch/ppc/sem.py @@ -135,7 +135,7 @@ def mn_do_cr(ir, instr, crd, cra, crb): elif op == 'XOR': r = a ^ b else: - raise "Unknown operation on CR" + raise RuntimeError("Unknown operation on CR") return [ ExprAff(d, r) ], [] def mn_do_div(ir, instr, rd, ra, rb): @@ -294,10 +294,10 @@ def mn_do_lswi(ir, instr, rd, ra, nb): if nb == 0: nb = 32 i = 32 - raise "%r not implemented" % instr + raise RuntimeError("%r not implemented" % instr) def mn_do_lswx(ir, instr, rd, ra, nb): - raise "%r not implemented" % instr + raise RuntimeError("%r not implemented" % instr) def mn_do_mcrf(ir, instr, crfd, crfs): ret = [] diff --git a/miasm2/arch/x86/arch.py b/miasm2/arch/x86/arch.py index 3e41d46e..2abd5bbc 100644 --- a/miasm2/arch/x86/arch.py +++ b/miasm2/arch/x86/arch.py @@ -939,7 +939,6 @@ class bs_modname_size(bs_divert): osize = v_opmode_info(size, opmode, 1, 0) nfields[i] = f nfields = nfields[:-1] - args = dict(self.args) ndct = dict(dct) if osize in self.args['name']: ndct['name'] = self.args['name'][osize] @@ -951,7 +950,6 @@ class bs_modname_size(bs_divert): f = bs("0", l=0, cls=(bs_fbit,), fname="rex_w") osize = v_opmode_info(size, opmode, 0, 0) nfields[i] = f - args = dict(self.args) ndct = dict(dct) if osize in self.args['name']: ndct['name'] = self.args['name'][osize] @@ -960,7 +958,6 @@ class bs_modname_size(bs_divert): l = opmode_prefix((dct['mode'], dct['opmode'], dct['admode'])) osize = v_opmode_info(size, opmode, None, 0) nfields = fields[:-1] - args = dict(self.args) ndct = dict(dct) if osize in self.args['name']: ndct['name'] = self.args['name'][osize] @@ -2897,9 +2894,7 @@ class bs_rel_off(bs_cond_imm): if not isinstance(self.expr, ExprInt): raise StopIteration arg0_expr = self.parent.args[0].expr - if self.l != 0: - l = self.l - else: + if self.l == 0: l = self.parent.v_opmode() self.l = l l = offsize(self.parent) diff --git a/miasm2/arch/x86/sem.py b/miasm2/arch/x86/sem.py index f07e2285..816608cb 100644 --- a/miasm2/arch/x86/sem.py +++ b/miasm2/arch/x86/sem.py @@ -1441,7 +1441,6 @@ def ret(ir, instr, src=None): myesp = mRSP[instr.mode][:size] if src is None: - src = m2_expr.ExprInt(0, size) value = (myesp + (m2_expr.ExprInt((size / 8), size))) else: src = m2_expr.ExprInt(int(src), size) @@ -1490,7 +1489,6 @@ def retf(ir, instr, src=None): def leave(ir, instr): - opmode, admode = instr.v_opmode(), instr.v_admode() size = instr.mode myesp = mRSP[size] e = [] @@ -4427,7 +4425,6 @@ def pslldq(_, instr, dst, src): def psrldq(_, instr, dst, src): assert src.is_int() - e = [] count = int(src) if count > 15: return [m2_expr.ExprAff(dst, m2_expr.ExprInt(0, dst.size))], [] @@ -4924,7 +4921,6 @@ def maskmovq(ir, instr, src, mask): # Build write blocks dst_addr = mRDI[instr.mode] for i, start in enumerate(xrange(0, mask.size, 8)): - bit = mask[start + 7: start + 8] cur_label = write_labels[i] next_check_label = check_labels[i + 1] if (i + 1) < len(check_labels) else loc_next_expr write_addr = dst_addr + m2_expr.ExprInt(i, dst_addr.size) @@ -5664,13 +5660,9 @@ class ir_x86_16(IntermediateRepresentation): return instr_ir, extra_ir instr.additional_info.except_on_instr = True - # get instruction size - s = {"B": 8, "W": 16, "D": 32, 'Q': 64}[instr.name[-1]] - size = instr.v_opmode() admode = instr.v_admode() c_reg = mRCX[instr.mode][:admode] - out_ir = [] zf_val = None # set if zf is tested (cmps, scas) for e in instr_ir: # +[updt_c]: |