diff options
Diffstat (limited to 'miasm2/arch')
| -rw-r--r-- | miasm2/arch/aarch64/sem.py | 10 | ||||
| -rw-r--r-- | miasm2/arch/mips32/ira.py | 10 | ||||
| -rw-r--r-- | miasm2/arch/mips32/jit.py | 12 | ||||
| -rw-r--r-- | miasm2/arch/x86/ira.py | 4 | ||||
| -rw-r--r-- | miasm2/arch/x86/jit.py | 27 | ||||
| -rw-r--r-- | miasm2/arch/x86/sem.py | 12 |
6 files changed, 56 insertions, 19 deletions
diff --git a/miasm2/arch/aarch64/sem.py b/miasm2/arch/aarch64/sem.py index e9eaffc8..599cdc98 100644 --- a/miasm2/arch/aarch64/sem.py +++ b/miasm2/arch/aarch64/sem.py @@ -777,9 +777,10 @@ class ir_aarch64l(IntermediateRepresentation): return m2_expr.ExprAff(dst, src) def irbloc_fix_regs_for_mode(self, irbloc, mode=64): - for assignblk in irbloc.irs: - for dst, src in assignblk.items(): - del(assignblk[dst]) + for idx, assignblk in enumerate(irbloc.irs): + new_assignblk = dict(assignblk) + for dst, src in assignblk.iteritems(): + del(new_assignblk[dst]) # Special case for 64 bits: # If destination is a 32 bit reg, zero extend the 64 bit reg @@ -791,7 +792,8 @@ class ir_aarch64l(IntermediateRepresentation): dst = self.expr_fix_regs_for_mode(dst) src = self.expr_fix_regs_for_mode(src) - assignblk[dst] = src + new_assignblk[dst] = src + irbloc.irs[idx] = AssignBlock(new_assignblk, assignblk.instr) if irbloc.dst is not None: irbloc.dst = self.expr_fix_regs_for_mode(irbloc.dst) diff --git a/miasm2/arch/mips32/ira.py b/miasm2/arch/mips32/ira.py index 92af5cc5..a2eab4fb 100644 --- a/miasm2/arch/mips32/ira.py +++ b/miasm2/arch/mips32/ira.py @@ -31,18 +31,18 @@ class ir_a_mips32l(ir_mips32l, ira): if expr_is_label(lr_val): lr_val = ExprInt(lr_val.name.offset, 32) - line = block.lines[-2] - if lr_val.arg != line.offset + 8: + instr = block.irs[-2].instr + if lr_val.arg != instr.offset + 8: raise ValueError("Wrong arg") # CALL lbl = block.get_next() new_lbl = self.gen_label() - irs = self.call_effects(pc_val, line) + irs = self.call_effects(pc_val, instr) irs.append(AssignBlock([ExprAff(self.IRDst, - ExprId(lbl, size=self.pc.size))])) + ExprId(lbl, size=self.pc.size))], + instr)) nblock = IRBlock(new_lbl, irs) - nblock.lines = [line] * len(irs) self.blocks[new_lbl] = nblock irb.dst = ExprId(new_lbl, size=self.pc.size) diff --git a/miasm2/arch/mips32/jit.py b/miasm2/arch/mips32/jit.py index bfa9c5fd..9b46589f 100644 --- a/miasm2/arch/mips32/jit.py +++ b/miasm2/arch/mips32/jit.py @@ -5,6 +5,7 @@ from miasm2.core import asmblock from miasm2.core.utils import pck32, upck32 from miasm2.arch.mips32.sem import ir_mips32l, ir_mips32b from miasm2.jitter.codegen import CGen +from miasm2.ir.ir import AssignBlock import miasm2.expression.expression as m2_expr log = logging.getLogger('jit_mips32') @@ -43,18 +44,21 @@ class mipsCGen(CGen): if not instr.breakflow(): continue for irblock in irblocks: - for assignblock in irblock.irs: + for idx, assignblock in enumerate(irblock.irs): if self.ir_arch.pc not in assignblock: continue + new_assignblock = dict(assignblock) # Add internal branch destination - assignblock[self.delay_slot_dst] = assignblock[ + new_assignblock[self.delay_slot_dst] = assignblock[ self.ir_arch.pc] - assignblock[self.delay_slot_set] = m2_expr.ExprInt(1, 32) + new_assignblock[self.delay_slot_set] = m2_expr.ExprInt(1, 32) # Replace IRDst with next instruction - assignblock[self.ir_arch.IRDst] = m2_expr.ExprId( + new_assignblock[self.ir_arch.IRDst] = m2_expr.ExprId( self.ir_arch.get_next_instr(instr)) irblock.dst = m2_expr.ExprId( self.ir_arch.get_next_instr(instr)) + irblock.irs[idx] = AssignBlock(new_assignblock, assignblock.instr) + return irblocks_list def gen_finalize(self, block): diff --git a/miasm2/arch/x86/ira.py b/miasm2/arch/x86/ira.py index 1fcaaa52..d0bebfb6 100644 --- a/miasm2/arch/x86/ira.py +++ b/miasm2/arch/x86/ira.py @@ -53,7 +53,9 @@ class ir_a_x86_64(ir_x86_64, ir_a_x86_16): )), ExprAff(self.sp, ExprOp('call_func_stack', ad, self.sp)), - ])] + ], + instr + )] def sizeof_char(self): return 8 diff --git a/miasm2/arch/x86/jit.py b/miasm2/arch/x86/jit.py index ef1f162b..e64c610b 100644 --- a/miasm2/arch/x86/jit.py +++ b/miasm2/arch/x86/jit.py @@ -140,6 +140,33 @@ class jitter_x86_32(jitter): get_arg_n_systemv = get_stack_arg + # fastcall + @named_arguments + def func_args_fastcall(self, n_args): + args_regs = ['ECX', 'EDX'] + ret_ad = self.pop_uint32_t() + args = [] + for i in xrange(n_args): + args.append(self.get_arg_n_fastcall(i)) + return ret_ad, args + + def func_prepare_fastcall(self, ret_addr, *args): + args_regs = ['ECX', 'EDX'] + self.push_uint32_t(ret_addr) + for i in xrange(min(len(args), len(args_regs))): + setattr(self.cpu, args_regs[i], args[i]) + remaining_args = args[len(args_regs):] + for arg in reversed(remaining_args): + self.push_uint32_t(arg) + + def get_arg_n_fastcall(self, index): + args_regs = ['ECX', 'EDX'] + if index < len(args_regs): + return getattr(self.cpu, args_regs[index]) + return self.get_stack_arg(index - len(args_regs)) + + + class jitter_x86_64(jitter): C_Gen = x86_64_CGen diff --git a/miasm2/arch/x86/sem.py b/miasm2/arch/x86/sem.py index 98866e65..0312891b 100644 --- a/miasm2/arch/x86/sem.py +++ b/miasm2/arch/x86/sem.py @@ -21,7 +21,7 @@ from miasm2.expression.simplifications import expr_simp from miasm2.arch.x86.regs import * from miasm2.arch.x86.arch import mn_x86, repeat_mn, replace_regs from miasm2.expression.expression_helper import expr_cmps, expr_cmpu -from miasm2.ir.ir import IntermediateRepresentation, IRBlock +from miasm2.ir.ir import IntermediateRepresentation, IRBlock, AssignBlock from miasm2.core.sembuilder import SemBuilder import math import struct @@ -4602,9 +4602,10 @@ class ir_x86_16(IntermediateRepresentation): return m2_expr.ExprAff(dst, src) def irbloc_fix_regs_for_mode(self, irbloc, mode=64): - for assignblk in irbloc.irs: - for dst, src in assignblk.items(): - del assignblk[dst] + for idx, assignblk in enumerate(irbloc.irs): + new_assignblk = dict(assignblk) + for dst, src in assignblk.iteritems(): + del new_assignblk[dst] # Special case for 64 bits: # If destination is a 32 bit reg, zero extend the 64 bit reg if mode == 64: @@ -4615,7 +4616,8 @@ class ir_x86_16(IntermediateRepresentation): dst = replace_regs[64][dst].arg dst = self.expr_fix_regs_for_mode(dst, mode) src = self.expr_fix_regs_for_mode(src, mode) - assignblk[dst] = src + new_assignblk[dst] = src + irbloc.irs[idx] = AssignBlock(new_assignblk, assignblk.instr) if irbloc.dst is not None: irbloc.dst = self.expr_fix_regs_for_mode(irbloc.dst, mode) |