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-rw-r--r--miasm2/arch/aarch64/jit.py10
-rw-r--r--miasm2/arch/aarch64/sem.py30
-rw-r--r--miasm2/arch/arm/arch.py6
-rw-r--r--miasm2/arch/arm/disasm.py2
-rw-r--r--miasm2/arch/arm/jit.py12
-rw-r--r--miasm2/arch/arm/sem.py3
-rw-r--r--miasm2/arch/mips32/jit.py12
-rw-r--r--miasm2/arch/msp430/jit.py8
-rw-r--r--miasm2/arch/msp430/sem.py1
-rw-r--r--miasm2/arch/ppc/jit.py6
-rw-r--r--miasm2/arch/x86/jit.py20
-rw-r--r--miasm2/arch/x86/sem.py2
12 files changed, 66 insertions, 46 deletions
diff --git a/miasm2/arch/aarch64/jit.py b/miasm2/arch/aarch64/jit.py
index 31570f52..b557a179 100644
--- a/miasm2/arch/aarch64/jit.py
+++ b/miasm2/arch/aarch64/jit.py
@@ -1,6 +1,6 @@
 import logging
 
-from miasm2.jitter.jitload import jitter, named_arguments
+from miasm2.jitter.jitload import Jitter, named_arguments
 from miasm2.core import asmblock
 from miasm2.core.utils import pck64, upck64
 from miasm2.arch.aarch64.sem import ir_aarch64b, ir_aarch64l
@@ -11,12 +11,12 @@ hnd.setFormatter(logging.Formatter("[%(levelname)s]: %(message)s"))
 log.addHandler(hnd)
 log.setLevel(logging.CRITICAL)
 
-class jitter_aarch64l(jitter):
+class jitter_aarch64l(Jitter):
     max_reg_arg = 8
 
     def __init__(self, *args, **kwargs):
         sp = asmblock.AsmSymbolPool()
-        jitter.__init__(self, ir_aarch64l(sp), *args, **kwargs)
+        Jitter.__init__(self, ir_aarch64l(sp), *args, **kwargs)
         self.vm.set_little_endian()
 
     def push_uint64_t(self, value):
@@ -69,7 +69,7 @@ class jitter_aarch64l(jitter):
     func_prepare_systemv = func_prepare_stdcall
 
     def init_run(self, *args, **kwargs):
-        jitter.init_run(self, *args, **kwargs)
+        Jitter.init_run(self, *args, **kwargs)
         self.cpu.PC = self.pc
 
 
@@ -77,5 +77,5 @@ class jitter_aarch64b(jitter_aarch64l):
 
     def __init__(self, *args, **kwargs):
         sp = asmblock.AsmSymbolPool()
-        jitter.__init__(self, ir_aarch64b(sp), *args, **kwargs)
+        Jitter.__init__(self, ir_aarch64b(sp), *args, **kwargs)
         self.vm.set_big_endian()
diff --git a/miasm2/arch/aarch64/sem.py b/miasm2/arch/aarch64/sem.py
index ad582878..c232e8dc 100644
--- a/miasm2/arch/aarch64/sem.py
+++ b/miasm2/arch/aarch64/sem.py
@@ -350,7 +350,36 @@ def csel(arg1, arg2, arg3, arg4):
     cond_expr = cond2expr[arg4.name]
     arg1 = arg2 if cond_expr else arg3
 
+def ccmp(ir, instr, arg1, arg2, arg3, arg4):
+    e = []
+    if(arg2.is_int):
+        arg2=m2_expr.ExprInt(arg2.arg.arg,arg1.size)
+    default_nf = arg3[0:1]
+    default_zf = arg3[1:2]
+    default_cf = arg3[2:3]
+    default_of = arg3[3:4]
+    cond_expr = cond2expr[arg4.name]
+    res = arg1 - arg2
+    new_nf = nf
+    new_zf = update_flag_zf(res)[0].src
+    new_cf = update_flag_sub_cf(arg1, arg2, res).src
+    new_of = update_flag_sub_of(arg1, arg2, res).src
+
+    e.append(m2_expr.ExprAff(nf, m2_expr.ExprCond(cond_expr,
+                                                    new_nf,
+                                                    default_nf)))
+    e.append(m2_expr.ExprAff(zf, m2_expr.ExprCond(cond_expr,
+                                                    new_zf,
+                                                    default_zf)))
+    e.append(m2_expr.ExprAff(cf, m2_expr.ExprCond(cond_expr,
+                                                    new_cf,
+                                                    default_cf)))
+    e.append(m2_expr.ExprAff(of, m2_expr.ExprCond(cond_expr,
+                                                    new_of,
+                                                    default_of)))
+    return e, []
 
+    
 def csinc(ir, instr, arg1, arg2, arg3, arg4):
     e = []
     cond_expr = cond2expr[arg4.name]
@@ -761,6 +790,7 @@ mnemo_func.update({
     'cmp': cmp,
     'cmn': cmn,
     'movk': movk,
+    'ccmp': ccmp,
     'csinc': csinc,
     'csinv': csinv,
     'csneg': csneg,
diff --git a/miasm2/arch/arm/arch.py b/miasm2/arch/arm/arch.py
index 17b57ba4..624642cf 100644
--- a/miasm2/arch/arm/arch.py
+++ b/miasm2/arch/arm/arch.py
@@ -1038,16 +1038,12 @@ class arm_op2(arm_arg):
         shift_kind = shift & 1
         shift_type = (shift >> 1) & 3
         shift >>= 3
-        # print self.parent.immop.value, hex(shift), hex(shift_kind),
-        # hex(shift_type)
         if shift_kind:
             # shift kind is reg
             if shift & 1:
-                # log.debug('error in shift1')
                 return False
             rs = shift >> 1
             if rs == 0xf:
-                # log.debug('error in shift2')
                 return False
             shift_op = regs_expr[rs]
         else:
@@ -2155,12 +2151,10 @@ class armt_rlist_pclr(armt_rlist):
         reg_l = list(e.args)
         self.parent.pclr.value = 0
         if self.parent.pp.value == 0:
-            # print 'push'
             if regs_expr[14] in reg_l:
                 reg_l.remove(regs_expr[14])
                 self.parent.pclr.value = 1
         else:
-            # print 'pop',
             if regs_expr[15] in reg_l:
                 reg_l.remove(regs_expr[15])
                 self.parent.pclr.value = 1
diff --git a/miasm2/arch/arm/disasm.py b/miasm2/arch/arm/disasm.py
index 205e2a17..8997fa2b 100644
--- a/miasm2/arch/arm/disasm.py
+++ b/miasm2/arch/arm/disasm.py
@@ -24,7 +24,7 @@ def cb_arm_fix_call(mn, cur_bloc, symbol_pool, offsets_to_dis, *args, **kwargs):
         return
     if not l2.args[1] in values:
         return
-    loc_key_cst = self.symbol_pool.getby_offset_create(l1.offset + 4)
+    loc_key_cst = symbol_pool.getby_offset_create(l1.offset + 4)
     cur_bloc.add_cst(loc_key_cst, AsmConstraint.c_next)
     offsets_to_dis.add(l1.offset + 4)
 
diff --git a/miasm2/arch/arm/jit.py b/miasm2/arch/arm/jit.py
index b92e2c32..ef2e14ae 100644
--- a/miasm2/arch/arm/jit.py
+++ b/miasm2/arch/arm/jit.py
@@ -1,6 +1,6 @@
 import logging
 
-from miasm2.jitter.jitload import jitter, named_arguments
+from miasm2.jitter.jitload import Jitter, named_arguments
 from miasm2.core import asmblock
 from miasm2.core.utils import pck32, upck32
 from miasm2.arch.arm.sem import ir_armb, ir_arml, ir_armtl, ir_armtb, cond_dct_inv, tab_cond
@@ -51,12 +51,12 @@ class arm_CGen(CGen):
         return irblocks_list
 
 
-class jitter_arml(jitter):
+class jitter_arml(Jitter):
     C_Gen = arm_CGen
 
     def __init__(self, *args, **kwargs):
         sp = asmblock.AsmSymbolPool()
-        jitter.__init__(self, ir_arml(sp), *args, **kwargs)
+        Jitter.__init__(self, ir_arml(sp), *args, **kwargs)
         self.vm.set_little_endian()
 
     def push_uint32_t(self, value):
@@ -107,7 +107,7 @@ class jitter_arml(jitter):
     get_arg_n_systemv = get_arg_n_stdcall
 
     def init_run(self, *args, **kwargs):
-        jitter.init_run(self, *args, **kwargs)
+        Jitter.init_run(self, *args, **kwargs)
         self.cpu.PC = self.pc
 
 
@@ -116,7 +116,7 @@ class jitter_armb(jitter_arml):
 
     def __init__(self, *args, **kwargs):
         sp = asmblock.AsmSymbolPool()
-        jitter.__init__(self, ir_armb(sp), *args, **kwargs)
+        Jitter.__init__(self, ir_armb(sp), *args, **kwargs)
         self.vm.set_big_endian()
 
 
@@ -125,5 +125,5 @@ class jitter_armtl(jitter_arml):
 
     def __init__(self, *args, **kwargs):
         sp = asmblock.AsmSymbolPool()
-        jitter.__init__(self, ir_armtl(sp), *args, **kwargs)
+        Jitter.__init__(self, ir_armtl(sp), *args, **kwargs)
         self.vm.set_little_endian()
diff --git a/miasm2/arch/arm/sem.py b/miasm2/arch/arm/sem.py
index c80e9826..ccd56e8f 100644
--- a/miasm2/arch/arm/sem.py
+++ b/miasm2/arch/arm/sem.py
@@ -635,7 +635,6 @@ def st_ld_r(ir, instr, a, a2, b, store=False, size=32, s_ext=False, z_ext=False)
         base, off = b.args[0],  b.args[1]  # ExprInt(size/8, 32)
     else:
         base, off = b, ExprInt(0, 32)
-    # print a, wb, base, off, postinc
     if postinc:
         ad = base
     else:
@@ -734,13 +733,11 @@ def ldrsh(ir, instr, a, b):
 def st_ld_m(ir, instr, a, b, store=False, postinc=False, updown=False):
     e = []
     wb = False
-    # sb = False
     dst = None
     if isinstance(a, ExprOp) and a.op == 'wback':
         wb = True
         a = a.args[0]
     if isinstance(b, ExprOp) and b.op == 'sbit':
-        # sb = True
         b = b.args[0]
     regs = b.args
     base = a
diff --git a/miasm2/arch/mips32/jit.py b/miasm2/arch/mips32/jit.py
index 180f8b0a..c637fb13 100644
--- a/miasm2/arch/mips32/jit.py
+++ b/miasm2/arch/mips32/jit.py
@@ -1,6 +1,6 @@
 import logging
 
-from miasm2.jitter.jitload import jitter, named_arguments
+from miasm2.jitter.jitload import Jitter, named_arguments
 from miasm2.core import asmblock
 from miasm2.core.utils import pck32, upck32
 from miasm2.arch.mips32.sem import ir_mips32l, ir_mips32b
@@ -71,7 +71,7 @@ class mipsCGen(CGen):
 
         loc_key = self.get_block_post_label(block)
         offset = self.ir_arch.symbol_pool.loc_key_to_offset(loc_key)
-        out = (self.CODE_RETURN_NO_EXCEPTION % (self.loc_key_to_jitlabel(loc_key),
+        out = (self.CODE_RETURN_NO_EXCEPTION % (loc_key,
                                                 self.C_PC,
                                                 m2_expr.ExprId('branch_dst_irdst', 32),
                                                 m2_expr.ExprId('branch_dst_irdst', 32),
@@ -80,13 +80,13 @@ class mipsCGen(CGen):
         return out
 
 
-class jitter_mips32l(jitter):
+class jitter_mips32l(Jitter):
 
     C_Gen = mipsCGen
 
     def __init__(self, *args, **kwargs):
         sp = asmblock.AsmSymbolPool()
-        jitter.__init__(self, ir_mips32l(sp), *args, **kwargs)
+        Jitter.__init__(self, ir_mips32l(sp), *args, **kwargs)
         self.vm.set_little_endian()
 
     def push_uint32_t(self, value):
@@ -102,7 +102,7 @@ class jitter_mips32l(jitter):
         return upck32(self.vm.get_mem(self.cpu.SP + 4 * index, 4))
 
     def init_run(self, *args, **kwargs):
-        jitter.init_run(self, *args, **kwargs)
+        Jitter.init_run(self, *args, **kwargs)
         self.cpu.PC = self.pc
 
     # calling conventions
@@ -146,5 +146,5 @@ class jitter_mips32b(jitter_mips32l):
 
     def __init__(self, *args, **kwargs):
         sp = asmblock.AsmSymbolPool()
-        jitter.__init__(self, ir_mips32b(sp), *args, **kwargs)
+        Jitter.__init__(self, ir_mips32b(sp), *args, **kwargs)
         self.vm.set_big_endian()
diff --git a/miasm2/arch/msp430/jit.py b/miasm2/arch/msp430/jit.py
index dd5fe94e..dcd7e91a 100644
--- a/miasm2/arch/msp430/jit.py
+++ b/miasm2/arch/msp430/jit.py
@@ -1,4 +1,4 @@
-from miasm2.jitter.jitload import jitter
+from miasm2.jitter.jitload import Jitter
 from miasm2.core import asmblock
 from miasm2.core.utils import pck16, upck16
 from miasm2.arch.msp430.sem import ir_msp430
@@ -11,11 +11,11 @@ hnd.setFormatter(logging.Formatter("[%(levelname)s]: %(message)s"))
 log.addHandler(hnd)
 log.setLevel(logging.CRITICAL)
 
-class jitter_msp430(jitter):
+class jitter_msp430(Jitter):
 
     def __init__(self, *args, **kwargs):
         sp = asmblock.AsmSymbolPool()
-        jitter.__init__(self, ir_msp430(sp), *args, **kwargs)
+        Jitter.__init__(self, ir_msp430(sp), *args, **kwargs)
         self.vm.set_little_endian()
 
     def push_uint16_t(self, value):
@@ -37,6 +37,6 @@ class jitter_msp430(jitter):
         return value
 
     def init_run(self, *args, **kwargs):
-        jitter.init_run(self, *args, **kwargs)
+        Jitter.init_run(self, *args, **kwargs)
         self.cpu.PC = self.pc
 
diff --git a/miasm2/arch/msp430/sem.py b/miasm2/arch/msp430/sem.py
index 877c2a70..a3521fb5 100644
--- a/miasm2/arch/msp430/sem.py
+++ b/miasm2/arch/msp430/sem.py
@@ -434,7 +434,6 @@ class ir_msp430(IntermediateRepresentation):
         pass
 
     def get_ir(self, instr):
-        # print instr#, args
         args = instr.args
         instr_ir, extra_ir = mnemo_func[instr.name](self, instr, *args)
         self.mod_sr(instr, instr_ir, extra_ir)
diff --git a/miasm2/arch/ppc/jit.py b/miasm2/arch/ppc/jit.py
index 9134e032..e79faabd 100644
--- a/miasm2/arch/ppc/jit.py
+++ b/miasm2/arch/ppc/jit.py
@@ -1,4 +1,4 @@
-from miasm2.jitter.jitload import jitter, named_arguments
+from miasm2.jitter.jitload import Jitter, named_arguments
 from miasm2.core import asmblock
 from miasm2.arch.ppc.sem import ir_ppc32b
 import struct
@@ -11,7 +11,7 @@ hnd.setFormatter(logging.Formatter("[%(levelname)s]: %(message)s"))
 log.addHandler(hnd)
 log.setLevel(logging.CRITICAL)
 
-class jitter_ppc32b(jitter):
+class jitter_ppc32b(Jitter):
     max_reg_arg = 8
 
     def __init__(self, *args, **kwargs):
@@ -66,5 +66,5 @@ class jitter_ppc32b(jitter):
 
 
     def init_run(self, *args, **kwargs):
-        jitter.init_run(self, *args, **kwargs)
+        Jitter.init_run(self, *args, **kwargs)
         self.cpu.PC = self.pc
diff --git a/miasm2/arch/x86/jit.py b/miasm2/arch/x86/jit.py
index a12a66f5..5485ed85 100644
--- a/miasm2/arch/x86/jit.py
+++ b/miasm2/arch/x86/jit.py
@@ -1,6 +1,6 @@
 import logging
 
-from miasm2.jitter.jitload import jitter, named_arguments
+from miasm2.jitter.jitload import Jitter, named_arguments
 from miasm2.core import asmblock
 from miasm2.core.utils import pck16, pck32, pck64, upck16, upck32, upck64
 from miasm2.arch.x86.sem import ir_x86_16, ir_x86_32, ir_x86_64
@@ -34,13 +34,13 @@ class x86_64_CGen(x86_32_CGen):
             out.append('dump_gpregs_64(jitcpu->cpu);')
         return out
 
-class jitter_x86_16(jitter):
+class jitter_x86_16(Jitter):
 
     C_Gen = x86_32_CGen
 
     def __init__(self, *args, **kwargs):
         sp = asmblock.AsmSymbolPool()
-        jitter.__init__(self, ir_x86_16(sp), *args, **kwargs)
+        Jitter.__init__(self, ir_x86_16(sp), *args, **kwargs)
         self.vm.set_little_endian()
         self.ir_arch.do_stk_segm = False
         self.orig_irbloc_fix_regs_for_mode = self.ir_arch.irbloc_fix_regs_for_mode
@@ -62,17 +62,17 @@ class jitter_x86_16(jitter):
         return upck16(self.vm.get_mem(self.cpu.SP + 4 * index, 4))
 
     def init_run(self, *args, **kwargs):
-        jitter.init_run(self, *args, **kwargs)
+        Jitter.init_run(self, *args, **kwargs)
         self.cpu.IP = self.pc
 
 
-class jitter_x86_32(jitter):
+class jitter_x86_32(Jitter):
 
     C_Gen = x86_32_CGen
 
     def __init__(self, *args, **kwargs):
         sp = asmblock.AsmSymbolPool()
-        jitter.__init__(self, ir_x86_32(sp), *args, **kwargs)
+        Jitter.__init__(self, ir_x86_32(sp), *args, **kwargs)
         self.vm.set_little_endian()
         self.ir_arch.do_stk_segm = False
 
@@ -104,7 +104,7 @@ class jitter_x86_32(jitter):
         return upck32(self.vm.get_mem(self.cpu.ESP + 4 * index, 4))
 
     def init_run(self, *args, **kwargs):
-        jitter.init_run(self, *args, **kwargs)
+        Jitter.init_run(self, *args, **kwargs)
         self.cpu.EIP = self.pc
 
     # calling conventions
@@ -180,7 +180,7 @@ class jitter_x86_32(jitter):
 
 
 
-class jitter_x86_64(jitter):
+class jitter_x86_64(Jitter):
 
     C_Gen = x86_64_CGen
     args_regs_systemv = ['RDI', 'RSI', 'RDX', 'RCX', 'R8', 'R9']
@@ -188,7 +188,7 @@ class jitter_x86_64(jitter):
 
     def __init__(self, *args, **kwargs):
         sp = asmblock.AsmSymbolPool()
-        jitter.__init__(self, ir_x86_64(sp), *args, **kwargs)
+        Jitter.__init__(self, ir_x86_64(sp), *args, **kwargs)
         self.vm.set_little_endian()
         self.ir_arch.do_stk_segm = False
 
@@ -211,7 +211,7 @@ class jitter_x86_64(jitter):
         return upck64(self.vm.get_mem(self.cpu.RSP + 8 * index, 8))
 
     def init_run(self, *args, **kwargs):
-        jitter.init_run(self, *args, **kwargs)
+        Jitter.init_run(self, *args, **kwargs)
         self.cpu.RIP = self.pc
 
     # calling conventions
diff --git a/miasm2/arch/x86/sem.py b/miasm2/arch/x86/sem.py
index d53677be..5989a0b4 100644
--- a/miasm2/arch/x86/sem.py
+++ b/miasm2/arch/x86/sem.py
@@ -776,7 +776,7 @@ def pop_gen(ir, instr, src, size):
         e.append(m2_expr.ExprAff(sp, new_sp))
     # XXX FIX XXX for pop [esp]
     if isinstance(src, m2_expr.ExprMem):
-        src = src.replace_expr({sp: new_sp})
+        src = expr_simp(src.replace_expr({sp: new_sp}))
     result = sp
     if ir.do_stk_segm:
         result = ir.gen_segm_expr(SS, result)