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-rw-r--r--miasm2/arch/aarch64/arch.py4
-rw-r--r--miasm2/arch/aarch64/disasm.py2
-rw-r--r--miasm2/arch/aarch64/ira.py15
-rw-r--r--miasm2/arch/aarch64/jit.py29
-rw-r--r--miasm2/arch/aarch64/sem.py18
-rw-r--r--miasm2/arch/arm/arch.py1
-rw-r--r--miasm2/arch/arm/disasm.py4
-rw-r--r--miasm2/arch/arm/ira.py16
-rw-r--r--miasm2/arch/arm/jit.py29
-rw-r--r--miasm2/arch/arm/sem.py20
-rw-r--r--miasm2/arch/mips32/arch.py1
-rw-r--r--miasm2/arch/mips32/disasm.py2
-rw-r--r--miasm2/arch/mips32/ira.py38
-rw-r--r--miasm2/arch/mips32/jit.py25
-rw-r--r--miasm2/arch/mips32/sem.py55
-rw-r--r--miasm2/arch/msp430/arch.py1
-rw-r--r--miasm2/arch/msp430/disasm.py2
-rw-r--r--miasm2/arch/msp430/ira.py32
-rw-r--r--miasm2/arch/msp430/jit.py20
-rw-r--r--miasm2/arch/msp430/sem.py6
-rw-r--r--miasm2/arch/sh4/arch.py1
-rw-r--r--miasm2/arch/x86/arch.py4
-rw-r--r--miasm2/arch/x86/disasm.py2
-rw-r--r--miasm2/arch/x86/ira.py30
-rw-r--r--miasm2/arch/x86/jit.py61
-rw-r--r--miasm2/arch/x86/sem.py56
26 files changed, 203 insertions, 271 deletions
diff --git a/miasm2/arch/aarch64/arch.py b/miasm2/arch/aarch64/arch.py
index 460c134e..6f95df99 100644
--- a/miasm2/arch/aarch64/arch.py
+++ b/miasm2/arch/aarch64/arch.py
@@ -8,7 +8,7 @@ from collections import defaultdict
 from miasm2.core.bin_stream import bin_stream
 import regs as regs_module
 from regs import *
-from miasm2.core.asmbloc import asm_label
+from miasm2.core.asmblock import AsmLabel
 from miasm2.core.cpu import log as log_cpu
 from miasm2.expression.modint import uint32, uint64
 import math
@@ -207,7 +207,7 @@ simdregs_h_zero = (simd32_info.parser |
 
 def ast_id2expr(t):
     if not t in mn_aarch64.regs.all_regs_ids_byname:
-        r = m2_expr.ExprId(asm_label(t))
+        r = m2_expr.ExprId(AsmLabel(t))
     else:
         r = mn_aarch64.regs.all_regs_ids_byname[t]
     return r
diff --git a/miasm2/arch/aarch64/disasm.py b/miasm2/arch/aarch64/disasm.py
index d31ce3fd..a8604fe5 100644
--- a/miasm2/arch/aarch64/disasm.py
+++ b/miasm2/arch/aarch64/disasm.py
@@ -1,4 +1,4 @@
-from miasm2.core.asmbloc import asm_constraint, disasmEngine
+from miasm2.core.asmblock import disasmEngine
 from miasm2.arch.aarch64.arch import mn_aarch64
 
 cb_aarch64_funcs = []
diff --git a/miasm2/arch/aarch64/ira.py b/miasm2/arch/aarch64/ira.py
index 20a9a66c..ada2e028 100644
--- a/miasm2/arch/aarch64/ira.py
+++ b/miasm2/arch/aarch64/ira.py
@@ -1,10 +1,7 @@
 #-*- coding:utf-8 -*-
 
-from miasm2.expression.expression import *
-from miasm2.ir.ir import ir, irbloc, AssignBlock
 from miasm2.ir.analysis import ira
 from miasm2.arch.aarch64.sem import ir_aarch64l, ir_aarch64b
-from miasm2.arch.aarch64.regs import *
 
 
 class ir_a_aarch64l_base(ir_aarch64l, ira):
@@ -28,13 +25,13 @@ class ir_a_aarch64l(ir_a_aarch64l_base):
         self.ret_reg = self.arch.regs.X0
 
     # for test XXX TODO
-    def set_dead_regs(self, b):
-        b.rw[-1][1].add(self.arch.regs.zf)
-        b.rw[-1][1].add(self.arch.regs.nf)
-        b.rw[-1][1].add(self.arch.regs.of)
-        b.rw[-1][1].add(self.arch.regs.cf)
+    def set_dead_regs(self, irblock):
+        irblock.rw[-1][1].add(self.arch.regs.zf)
+        irblock.rw[-1][1].add(self.arch.regs.nf)
+        irblock.rw[-1][1].add(self.arch.regs.of)
+        irblock.rw[-1][1].add(self.arch.regs.cf)
 
-    def get_out_regs(self, b):
+    def get_out_regs(self, _):
         return set([self.ret_reg, self.sp])
 
     def sizeof_char(self):
diff --git a/miasm2/arch/aarch64/jit.py b/miasm2/arch/aarch64/jit.py
index ca8d7b39..255bb91d 100644
--- a/miasm2/arch/aarch64/jit.py
+++ b/miasm2/arch/aarch64/jit.py
@@ -1,8 +1,8 @@
 import logging
 
 from miasm2.jitter.jitload import jitter, named_arguments
-from miasm2.core import asmbloc
-from miasm2.core.utils import *
+from miasm2.core import asmblock
+from miasm2.core.utils import pck64, upck64
 from miasm2.arch.aarch64.sem import ir_aarch64b, ir_aarch64l
 
 log = logging.getLogger('jit_aarch64')
@@ -15,22 +15,21 @@ class jitter_aarch64l(jitter):
     max_reg_arg = 8
 
     def __init__(self, *args, **kwargs):
-        sp = asmbloc.asm_symbol_pool()
+        sp = asmblock.AsmSymbolPool()
         jitter.__init__(self, ir_aarch64l(sp), *args, **kwargs)
         self.vm.set_little_endian()
 
-    def push_uint64_t(self, v):
+    def push_uint64_t(self, value):
         self.cpu.SP -= 8
-        self.vm.set_mem(self.cpu.SP, pck64(v))
+        self.vm.set_mem(self.cpu.SP, pck64(value))
 
     def pop_uint64_t(self):
-        x = upck32(self.vm.get_mem(self.cpu.SP, 8))
+        value = upck64(self.vm.get_mem(self.cpu.SP, 8))
         self.cpu.SP += 8
-        return x
+        return value
 
-    def get_stack_arg(self, n):
-        x = upck64(self.vm.get_mem(self.cpu.SP + 8 * n, 8))
-        return x
+    def get_stack_arg(self, index):
+        return upck64(self.vm.get_mem(self.cpu.SP + 8 * index, 8))
 
     # calling conventions
 
@@ -50,11 +49,11 @@ class jitter_aarch64l(jitter):
             self.cpu.X0 = ret_value
         return True
 
-    def get_arg_n_stdcall(self, n):
-        if n < self.max_reg_arg:
-            arg = self.cpu.get_gpreg()['X%d' % n]
+    def get_arg_n_stdcall(self, index):
+        if index < self.max_reg_arg:
+            arg = self.cpu.get_gpreg()['X%d' % index]
         else:
-            arg = self.get_stack_arg(n - self.max_reg_arg)
+            arg = self.get_stack_arg(index - self.max_reg_arg)
         return arg
 
     def init_run(self, *args, **kwargs):
@@ -65,6 +64,6 @@ class jitter_aarch64l(jitter):
 class jitter_aarch64b(jitter_aarch64l):
 
     def __init__(self, *args, **kwargs):
-        sp = asmbloc.asm_symbol_pool()
+        sp = asmblock.AsmSymbolPool()
         jitter.__init__(self, ir_aarch64b(sp), *args, **kwargs)
         self.vm.set_big_endian()
diff --git a/miasm2/arch/aarch64/sem.py b/miasm2/arch/aarch64/sem.py
index c3ed56d5..792a4984 100644
--- a/miasm2/arch/aarch64/sem.py
+++ b/miasm2/arch/aarch64/sem.py
@@ -1,5 +1,5 @@
 from miasm2.expression import expression as m2_expr
-from miasm2.ir.ir import ir, irbloc, AssignBlock
+from miasm2.ir.ir import IntermediateRepresentation, IRBlock, AssignBlock
 from miasm2.arch.aarch64.arch import mn_aarch64, conds_expr, replace_regs
 from miasm2.arch.aarch64.regs import *
 from miasm2.core.sembuilder import SemBuilder
@@ -746,10 +746,10 @@ class aarch64info:
     # offset
 
 
-class ir_aarch64l(ir):
+class ir_aarch64l(IntermediateRepresentation):
 
     def __init__(self, symbol_pool=None):
-        ir.__init__(self, mn_aarch64, "l", symbol_pool)
+        IntermediateRepresentation.__init__(self, mn_aarch64, "l", symbol_pool)
         self.pc = PC
         self.sp = SP
         self.IRDst = m2_expr.ExprId('IRDst', 64)
@@ -804,8 +804,8 @@ class ir_aarch64l(ir):
                 dst = dst.replace_expr({self.pc: cur_offset})
             src = src.replace_expr({self.pc: cur_offset})
             instr_ir[i] = m2_expr.ExprAff(dst, src)
-        for b in extra_ir:
-            for irs in b.irs:
+        for irblock in extra_ir:
+            for irs in irblock.irs:
                 for i, expr in enumerate(irs):
                     dst, src = expr.dst, expr.src
                     if dst != self.pc:
@@ -819,9 +819,9 @@ class ir_aarch64l(ir):
         regs_to_fix = [WZR, XZR]
         instr_ir = [expr for expr in instr_ir if expr.dst not in regs_to_fix]
 
-        for b in extra_ir:
-            for i, irs in enumerate(b.irs):
-                b.irs[i] = [expr for expr in irs if expr.dst not in regs_to_fix]
+        for irblock in extra_ir:
+            for i, irs in enumerate(irblock.irs):
+                irblock.irs[i] = [expr for expr in irs if expr.dst not in regs_to_fix]
 
         return instr_ir, extra_ir
 
@@ -829,7 +829,7 @@ class ir_aarch64l(ir):
 class ir_aarch64b(ir_aarch64l):
 
     def __init__(self, symbol_pool=None):
-        ir.__init__(self, mn_aarch64, "b", symbol_pool)
+        IntermediateRepresentation.__init__(self, mn_aarch64, "b", symbol_pool)
         self.pc = PC
         self.sp = SP
         self.IRDst = m2_expr.ExprId('IRDst', 64)
diff --git a/miasm2/arch/arm/arch.py b/miasm2/arch/arm/arch.py
index d9bf42ba..54a168af 100644
--- a/miasm2/arch/arm/arch.py
+++ b/miasm2/arch/arm/arch.py
@@ -8,7 +8,6 @@ from collections import defaultdict
 from miasm2.core.bin_stream import bin_stream
 import miasm2.arch.arm.regs as regs_module
 from miasm2.arch.arm.regs import *
-from miasm2.core.asmbloc import asm_label
 
 # A1 encoding
 
diff --git a/miasm2/arch/arm/disasm.py b/miasm2/arch/arm/disasm.py
index 6209be5e..3f6ea4d5 100644
--- a/miasm2/arch/arm/disasm.py
+++ b/miasm2/arch/arm/disasm.py
@@ -1,4 +1,4 @@
-from miasm2.core.asmbloc import asm_constraint, disasmEngine
+from miasm2.core.asmblock import AsmConstraint, disasmEngine
 from miasm2.arch.arm.arch import mn_arm, mn_armt
 
 
@@ -24,7 +24,7 @@ def cb_arm_fix_call(mn, cur_bloc, symbol_pool, offsets_to_dis, *args, **kwargs):
         return
     if not l2.args[1] in values:
         return
-    cur_bloc.add_cst(l1.offset + 4, asm_constraint.c_next, symbol_pool)
+    cur_bloc.add_cst(l1.offset + 4, AsmConstraint.c_next, symbol_pool)
     offsets_to_dis.add(l1.offset + 4)
 
 cb_arm_funcs = [cb_arm_fix_call]
diff --git a/miasm2/arch/arm/ira.py b/miasm2/arch/arm/ira.py
index 8d659b58..760e6d90 100644
--- a/miasm2/arch/arm/ira.py
+++ b/miasm2/arch/arm/ira.py
@@ -1,11 +1,7 @@
 #-*- coding:utf-8 -*-
 
-from miasm2.expression.expression import *
-from miasm2.ir.ir import ir, irbloc, AssignBlock
 from miasm2.ir.analysis import ira
 from miasm2.arch.arm.sem import ir_arml, ir_armtl, ir_armb, ir_armtb
-from miasm2.arch.arm.regs import *
-# from miasm2.core.graph import DiGraph
 
 
 class ir_a_arml_base(ir_arml, ira):
@@ -26,13 +22,13 @@ class ir_a_arml(ir_a_arml_base):
         self.ret_reg = self.arch.regs.R0
 
     # for test XXX TODO
-    def set_dead_regs(self, b):
-        b.rw[-1][1].add(self.arch.regs.zf)
-        b.rw[-1][1].add(self.arch.regs.nf)
-        b.rw[-1][1].add(self.arch.regs.of)
-        b.rw[-1][1].add(self.arch.regs.cf)
+    def set_dead_regs(self, irblock):
+        irblock.rw[-1][1].add(self.arch.regs.zf)
+        irblock.rw[-1][1].add(self.arch.regs.nf)
+        irblock.rw[-1][1].add(self.arch.regs.of)
+        irblock.rw[-1][1].add(self.arch.regs.cf)
 
-    def get_out_regs(self, b):
+    def get_out_regs(self, _):
         return set([self.ret_reg, self.sp])
 
     def sizeof_char(self):
diff --git a/miasm2/arch/arm/jit.py b/miasm2/arch/arm/jit.py
index 70d16176..70c708e1 100644
--- a/miasm2/arch/arm/jit.py
+++ b/miasm2/arch/arm/jit.py
@@ -1,8 +1,8 @@
 import logging
 
 from miasm2.jitter.jitload import jitter, named_arguments
-from miasm2.core import asmbloc
-from miasm2.core.utils import *
+from miasm2.core import asmblock
+from miasm2.core.utils import pck32, upck32
 from miasm2.arch.arm.sem import ir_armb, ir_arml
 
 log = logging.getLogger('jit_arm')
@@ -14,22 +14,21 @@ log.setLevel(logging.CRITICAL)
 class jitter_arml(jitter):
 
     def __init__(self, *args, **kwargs):
-        sp = asmbloc.asm_symbol_pool()
+        sp = asmblock.AsmSymbolPool()
         jitter.__init__(self, ir_arml(sp), *args, **kwargs)
         self.vm.set_little_endian()
 
-    def push_uint32_t(self, v):
+    def push_uint32_t(self, value):
         self.cpu.SP -= 4
-        self.vm.set_mem(self.cpu.SP, pck32(v))
+        self.vm.set_mem(self.cpu.SP, pck32(value))
 
     def pop_uint32_t(self):
-        x = upck32(self.vm.get_mem(self.cpu.SP, 4))
+        value = upck32(self.vm.get_mem(self.cpu.SP, 4))
         self.cpu.SP += 4
-        return x
+        return value
 
-    def get_stack_arg(self, n):
-        x = upck32(self.vm.get_mem(self.cpu.SP + 4 * n, 4))
-        return x
+    def get_stack_arg(self, index):
+        return upck32(self.vm.get_mem(self.cpu.SP + 4 * index, 4))
 
     # calling conventions
 
@@ -49,11 +48,11 @@ class jitter_arml(jitter):
             self.cpu.R0 = ret_value
         return True
 
-    def get_arg_n_stdcall(self, n):
-        if n < 4:
-            arg = self.cpu.get_gpreg()['R%d' % n]
+    def get_arg_n_stdcall(self, index):
+        if index < 4:
+            arg = self.cpu.get_gpreg()['R%d' % index]
         else:
-            arg = self.get_stack_arg(n-4)
+            arg = self.get_stack_arg(index-4)
         return arg
 
     def init_run(self, *args, **kwargs):
@@ -63,6 +62,6 @@ class jitter_arml(jitter):
 class jitter_armb(jitter_arml):
 
     def __init__(self, *args, **kwargs):
-        sp = asmbloc.asm_symbol_pool()
+        sp = asmblock.AsmSymbolPool()
         jitter.__init__(self, ir_armb(sp), *args, **kwargs)
         self.vm.set_big_endian()
diff --git a/miasm2/arch/arm/sem.py b/miasm2/arch/arm/sem.py
index 225b393c..8c74aa76 100644
--- a/miasm2/arch/arm/sem.py
+++ b/miasm2/arch/arm/sem.py
@@ -1,5 +1,5 @@
 from miasm2.expression.expression import *
-from miasm2.ir.ir import ir, irbloc
+from miasm2.ir.ir import IntermediateRepresentation, IRBlock
 from miasm2.arch.arm.arch import mn_arm, mn_armt
 from miasm2.arch.arm.regs import *
 
@@ -1055,7 +1055,7 @@ def add_condition_expr(ir, instr, cond, instr_ir):
             break
     if not has_irdst:
         instr_ir.append(ExprAff(ir.IRDst, lbl_next))
-    e_do = irbloc(lbl_do.name, [instr_ir])
+    e_do = IRBlock(lbl_do.name, [instr_ir])
     e = [ExprAff(ir.IRDst, dst_cond)]
     return e, [e_do]
 
@@ -1227,9 +1227,9 @@ class arminfo:
     # offset
 
 
-class ir_arml(ir):
+class ir_arml(IntermediateRepresentation):
     def __init__(self, symbol_pool=None):
-        ir.__init__(self, mn_arm, "l", symbol_pool)
+        IntermediateRepresentation.__init__(self, mn_arm, "l", symbol_pool)
         self.pc = PC
         self.sp = SP
         self.IRDst = ExprId('IRDst', 32)
@@ -1252,8 +1252,8 @@ class ir_arml(ir):
             x = ExprAff(x.dst, x.src.replace_expr(
                 {self.pc: ExprInt32(instr.offset + 8)}))
             instr_ir[i] = x
-        for b in extra_ir:
-            for irs in b.irs:
+        for irblock in extra_ir:
+            for irs in irblock.irs:
                 for i, x in enumerate(irs):
                     x = ExprAff(x.dst, x.src.replace_expr(
                         {self.pc: ExprInt32(instr.offset + 8)}))
@@ -1264,14 +1264,14 @@ class ir_arml(ir):
 
 class ir_armb(ir_arml):
     def __init__(self, symbol_pool=None):
-        ir.__init__(self, mn_arm, "b", symbol_pool)
+        IntermediateRepresentation.__init__(self, mn_arm, "b", symbol_pool)
         self.pc = PC
         self.sp = SP
         self.IRDst = ExprId('IRDst', 32)
 
-class ir_armtl(ir):
+class ir_armtl(IntermediateRepresentation):
     def __init__(self, symbol_pool=None):
-        ir.__init__(self, mn_armt, "l", symbol_pool)
+        IntermediateRepresentation.__init__(self, mn_armt, "l", symbol_pool)
         self.pc = PC
         self.sp = SP
         self.IRDst = ExprId('IRDst', 32)
@@ -1281,7 +1281,7 @@ class ir_armtl(ir):
 
 class ir_armtb(ir_armtl):
     def __init__(self, symbol_pool=None):
-        ir.__init__(self, mn_armt, "b", symbol_pool)
+        IntermediateRepresentation.__init__(self, mn_armt, "b", symbol_pool)
         self.pc = PC
         self.sp = SP
         self.IRDst = ExprId('IRDst', 32)
diff --git a/miasm2/arch/mips32/arch.py b/miasm2/arch/mips32/arch.py
index 79176205..f11c6e3a 100644
--- a/miasm2/arch/mips32/arch.py
+++ b/miasm2/arch/mips32/arch.py
@@ -9,7 +9,6 @@ from miasm2.expression.expression import ExprMem, ExprInt, ExprInt32, ExprId
 from miasm2.core.bin_stream import bin_stream
 import miasm2.arch.mips32.regs as regs
 import miasm2.core.cpu as cpu
-from miasm2.core.asmbloc import asm_label
 
 log = logging.getLogger("mips32dis")
 console_handler = logging.StreamHandler()
diff --git a/miasm2/arch/mips32/disasm.py b/miasm2/arch/mips32/disasm.py
index e5a70349..bdd800d5 100644
--- a/miasm2/arch/mips32/disasm.py
+++ b/miasm2/arch/mips32/disasm.py
@@ -1,4 +1,4 @@
-from miasm2.core.asmbloc import disasmEngine
+from miasm2.core.asmblock import disasmEngine
 from miasm2.arch.mips32.arch import mn_mips32
 
 
diff --git a/miasm2/arch/mips32/ira.py b/miasm2/arch/mips32/ira.py
index 8f7b2df3..dd02ff50 100644
--- a/miasm2/arch/mips32/ira.py
+++ b/miasm2/arch/mips32/ira.py
@@ -1,34 +1,28 @@
 #-*- coding:utf-8 -*-
 
-from miasm2.expression.expression import *
-from miasm2.ir.ir import ir, irbloc, AssignBlock
+from miasm2.expression.expression import ExprAff, ExprInt32, ExprId
+from miasm2.ir.ir import IntermediateRepresentation, IRBlock, AssignBlock
 from miasm2.ir.analysis import ira
 from miasm2.arch.mips32.sem import ir_mips32l, ir_mips32b
-from miasm2.arch.mips32.regs import *
-from miasm2.core.asmbloc import expr_is_int_or_label, expr_is_label
+from miasm2.core.asmblock import expr_is_int_or_label, expr_is_label
 
 class ir_a_mips32l(ir_mips32l, ira):
     def __init__(self, symbol_pool=None):
         ir_mips32l.__init__(self, symbol_pool)
         self.ret_reg = self.arch.regs.V0
 
-
-    # for test XXX TODO
-    def set_dead_regs(self, b):
-        pass
-
     def pre_add_instr(self, block, instr, irb_cur, ir_blocks_all, gen_pc_updt):
         # Avoid adding side effects, already done in post_add_bloc
         return irb_cur
 
-    def post_add_bloc(self, bloc, ir_blocs):
-        ir.post_add_bloc(self, bloc, ir_blocs)
-        for irb in ir_blocs:
+    def post_add_bloc(self, block, ir_blocks):
+        IntermediateRepresentation.post_add_bloc(self, block, ir_blocks)
+        for irb in ir_blocks:
             pc_val = None
             lr_val = None
             for assignblk in irb.irs:
-                pc_val = assignblk.get(PC, pc_val)
-                lr_val = assignblk.get(RA, lr_val)
+                pc_val = assignblk.get(self.arch.regs.PC, pc_val)
+                lr_val = assignblk.get(self.arch.regs.RA, lr_val)
 
             if pc_val is None or lr_val is None:
                 continue
@@ -37,22 +31,22 @@ class ir_a_mips32l(ir_mips32l, ira):
             if expr_is_label(lr_val):
                 lr_val = ExprInt32(lr_val.name.offset)
 
-            l = bloc.lines[-2]
-            if lr_val.arg != l.offset + 8:
+            line = block.lines[-2]
+            if lr_val.arg != line.offset + 8:
                 raise ValueError("Wrong arg")
 
             # CALL
-            lbl = bloc.get_next()
+            lbl = block.get_next()
             new_lbl = self.gen_label()
-            irs = self.call_effects(pc_val, l)
+            irs = self.call_effects(pc_val, line)
             irs.append(AssignBlock([ExprAff(self.IRDst,
                                             ExprId(lbl, size=self.pc.size))]))
-            nbloc = irbloc(new_lbl, irs)
-            nbloc.lines = [l] * len(irs)
-            self.blocs[new_lbl] = nbloc
+            nblock = IRBlock(new_lbl, irs)
+            nblock.lines = [line] * len(irs)
+            self.blocks[new_lbl] = nblock
             irb.dst = ExprId(new_lbl, size=self.pc.size)
 
-    def get_out_regs(self, b):
+    def get_out_regs(self, _):
         return set([self.ret_reg, self.sp])
 
     def sizeof_char(self):
diff --git a/miasm2/arch/mips32/jit.py b/miasm2/arch/mips32/jit.py
index 332e8d13..0ba531f1 100644
--- a/miasm2/arch/mips32/jit.py
+++ b/miasm2/arch/mips32/jit.py
@@ -1,8 +1,8 @@
 import logging
 
 from miasm2.jitter.jitload import jitter
-from miasm2.core import asmbloc
-from miasm2.core.utils import *
+from miasm2.core import asmblock
+from miasm2.core.utils import pck32, upck32
 from miasm2.arch.mips32.sem import ir_mips32l, ir_mips32b
 from miasm2.jitter.codegen import CGen
 import miasm2.expression.expression as m2_expr
@@ -43,7 +43,7 @@ class mipsCGen(CGen):
             if not instr.breakflow():
                 continue
             for irblock in irblocks:
-                for i, assignblock in enumerate(irblock.irs):
+                for assignblock in irblock.irs:
                     if self.ir_arch.pc not in assignblock:
                         continue
                     # Add internal branch destination
@@ -68,7 +68,7 @@ class mipsCGen(CGen):
                                                 m2_expr.ExprId('branch_dst_irdst'),
                                                 m2_expr.ExprId('branch_dst_irdst'),
                                                 self.id_to_c(m2_expr.ExprInt(lbl.offset, 32)))
-               ).split('\n')
+              ).split('\n')
         return out
 
 
@@ -77,22 +77,21 @@ class jitter_mips32l(jitter):
     C_Gen = mipsCGen
 
     def __init__(self, *args, **kwargs):
-        sp = asmbloc.asm_symbol_pool()
+        sp = asmblock.AsmSymbolPool()
         jitter.__init__(self, ir_mips32l(sp), *args, **kwargs)
         self.vm.set_little_endian()
 
-    def push_uint32_t(self, v):
+    def push_uint32_t(self, value):
         self.cpu.SP -= 4
-        self.vm.set_mem(self.cpu.SP, pck32(v))
+        self.vm.set_mem(self.cpu.SP, pck32(value))
 
     def pop_uint32_t(self):
-        x = upck32(self.vm.get_mem(self.cpu.SP, 4))
+        value = upck32(self.vm.get_mem(self.cpu.SP, 4))
         self.cpu.SP += 4
-        return x
+        return value
 
-    def get_stack_arg(self, n):
-        x = upck32(self.vm.get_mem(self.cpu.SP + 4 * n, 4))
-        return x
+    def get_stack_arg(self, index):
+        return upck32(self.vm.get_mem(self.cpu.SP + 4 * index, 4))
 
     def init_run(self, *args, **kwargs):
         jitter.init_run(self, *args, **kwargs)
@@ -102,6 +101,6 @@ class jitter_mips32l(jitter):
 class jitter_mips32b(jitter_mips32l):
 
     def __init__(self, *args, **kwargs):
-        sp = asmbloc.asm_symbol_pool()
+        sp = asmblock.AsmSymbolPool()
         jitter.__init__(self, ir_mips32b(sp), *args, **kwargs)
         self.vm.set_big_endian()
diff --git a/miasm2/arch/mips32/sem.py b/miasm2/arch/mips32/sem.py
index b52b8401..d982f033 100644
--- a/miasm2/arch/mips32/sem.py
+++ b/miasm2/arch/mips32/sem.py
@@ -1,5 +1,5 @@
 import miasm2.expression.expression as m2_expr
-from miasm2.ir.ir import ir, irbloc
+from miasm2.ir.ir import IntermediateRepresentation, IRBlock
 from miasm2.arch.mips32.arch import mn_mips32
 from miasm2.arch.mips32.regs import R_LO, R_HI, PC, RA
 from miasm2.core.sembuilder import SemBuilder
@@ -429,10 +429,10 @@ def get_mnemo_expr(ir, instr, *args):
     instr, extra_ir = mnemo_func[instr.name.lower()](ir, instr, *args)
     return instr, extra_ir
 
-class ir_mips32l(ir):
+class ir_mips32l(IntermediateRepresentation):
 
     def __init__(self, symbol_pool=None):
-        ir.__init__(self, mn_mips32, 'l', symbol_pool)
+        IntermediateRepresentation.__init__(self, mn_mips32, 'l', symbol_pool)
         self.pc = mn_mips32.getpc()
         self.sp = mn_mips32.getsp()
         self.IRDst = m2_expr.ExprId('IRDst', 32)
@@ -445,8 +445,8 @@ class ir_mips32l(ir):
             x = m2_expr.ExprAff(x.dst, x.src.replace_expr(
                 {self.pc: m2_expr.ExprInt32(instr.offset + 4)}))
             instr_ir[i] = x
-        for b in extra_ir:
-            for irs in b.irs:
+        for irblock in extra_ir:
+            for irs in irblock.irs:
                 for i, x in enumerate(irs):
                     x = m2_expr.ExprAff(x.dst, x.src.replace_expr(
                         {self.pc: m2_expr.ExprInt32(instr.offset + 4)}))
@@ -454,53 +454,14 @@ class ir_mips32l(ir):
         return instr_ir, extra_ir
 
     def get_next_instr(self, instr):
-        l = self.symbol_pool.getby_offset_create(instr.offset  + 4)
-        return l
+        return self.symbol_pool.getby_offset_create(instr.offset  + 4)
 
     def get_next_break_label(self, instr):
-        l = self.symbol_pool.getby_offset_create(instr.offset  + 8)
-        return l
-    """
-    def add_bloc(self, bloc, gen_pc_updt = False):
-        c = None
-        ir_blocs_all = []
-        for l in bloc.lines:
-            if c is None:
-                # print 'new c'
-                label = self.get_label(l)
-                c = irbloc(label, [], [])
-                ir_blocs_all.append(c)
-                bloc_dst = None
-            # print 'Translate', l
-            dst, ir_bloc_cur, ir_blocs_extra = self.instr2ir(l)
-            # print ir_bloc_cur
-            # for xxx in ir_bloc_cur:
-            #    print "\t", xxx
-            assert((dst is None) or (bloc_dst is None))
-            bloc_dst = dst
-            #if bloc_dst is not None:
-            #    c.dst = bloc_dst
-            if dst is not None:
-                ir_bloc_cur.append(m2_expr.ExprAff(PC_FETCH, dst))
-                c.dst = PC_FETCH
-            if gen_pc_updt is not False:
-                self.gen_pc_update(c, l)
-
-            c.irs.append(ir_bloc_cur)
-            c.lines.append(l)
-            if ir_blocs_extra:
-                # print 'split'
-                for b in ir_blocs_extra:
-                    b.lines = [l] * len(b.irs)
-                ir_blocs_all += ir_blocs_extra
-                c = None
-        self.post_add_bloc(bloc, ir_blocs_all)
-        return ir_blocs_all
-    """
+        return self.symbol_pool.getby_offset_create(instr.offset  + 8)
 
 class ir_mips32b(ir_mips32l):
     def __init__(self, symbol_pool=None):
-        ir.__init__(self, mn_mips32, 'b', symbol_pool)
+        IntermediateRepresentation.__init__(self, mn_mips32, 'b', symbol_pool)
         self.pc = mn_mips32.getpc()
         self.sp = mn_mips32.getsp()
         self.IRDst = m2_expr.ExprId('IRDst', 32)
diff --git a/miasm2/arch/msp430/arch.py b/miasm2/arch/msp430/arch.py
index d7463f3d..07ba3019 100644
--- a/miasm2/arch/msp430/arch.py
+++ b/miasm2/arch/msp430/arch.py
@@ -8,7 +8,6 @@ from collections import defaultdict
 from miasm2.core.bin_stream import bin_stream
 import miasm2.arch.msp430.regs as regs_module
 from miasm2.arch.msp430.regs import *
-from miasm2.core.asmbloc import asm_label
 
 log = logging.getLogger("msp430dis")
 console_handler = logging.StreamHandler()
diff --git a/miasm2/arch/msp430/disasm.py b/miasm2/arch/msp430/disasm.py
index ac5d9cce..849cd675 100644
--- a/miasm2/arch/msp430/disasm.py
+++ b/miasm2/arch/msp430/disasm.py
@@ -1,4 +1,4 @@
-from miasm2.core.asmbloc import disasmEngine
+from miasm2.core.asmblock import disasmEngine
 from miasm2.arch.msp430.arch import mn_msp430
 
 
diff --git a/miasm2/arch/msp430/ira.py b/miasm2/arch/msp430/ira.py
index 071bfae8..0dc63c61 100644
--- a/miasm2/arch/msp430/ira.py
+++ b/miasm2/arch/msp430/ira.py
@@ -1,11 +1,7 @@
 #-*- coding:utf-8 -*-
 
-from miasm2.expression.expression import *
-from miasm2.ir.ir import ir, irbloc, AssignBlock
 from miasm2.ir.analysis import ira
 from miasm2.arch.msp430.sem import ir_msp430
-from miasm2.arch.msp430.regs import *
-# from miasm2.core.graph import DiGraph
 
 
 class ir_a_msp430_base(ir_msp430, ira):
@@ -21,19 +17,19 @@ class ir_a_msp430(ir_a_msp430_base):
         ir_a_msp430_base.__init__(self, symbol_pool)
 
     # for test XXX TODO
-    def set_dead_regs(self, b):
-        b.rw[-1][1].add(self.arch.regs.zf)
-        b.rw[-1][1].add(self.arch.regs.nf)
-        b.rw[-1][1].add(self.arch.regs.of)
-        b.rw[-1][1].add(self.arch.regs.cf)
-
-        b.rw[-1][1].add(self.arch.regs.res)
-        b.rw[-1][1].add(self.arch.regs.scg1)
-        b.rw[-1][1].add(self.arch.regs.scg0)
-        b.rw[-1][1].add(self.arch.regs.osc)
-        b.rw[-1][1].add(self.arch.regs.cpuoff)
-        b.rw[-1][1].add(self.arch.regs.gie)
-
-    def get_out_regs(self, b):
+    def set_dead_regs(self, irblock):
+        irblock.rw[-1][1].add(self.arch.regs.zf)
+        irblock.rw[-1][1].add(self.arch.regs.nf)
+        irblock.rw[-1][1].add(self.arch.regs.of)
+        irblock.rw[-1][1].add(self.arch.regs.cf)
+
+        irblock.rw[-1][1].add(self.arch.regs.res)
+        irblock.rw[-1][1].add(self.arch.regs.scg1)
+        irblock.rw[-1][1].add(self.arch.regs.scg0)
+        irblock.rw[-1][1].add(self.arch.regs.osc)
+        irblock.rw[-1][1].add(self.arch.regs.cpuoff)
+        irblock.rw[-1][1].add(self.arch.regs.gie)
+
+    def get_out_regs(self, _):
         return set([self.ret_reg, self.sp])
 
diff --git a/miasm2/arch/msp430/jit.py b/miasm2/arch/msp430/jit.py
index 95d34f96..dd5fe94e 100644
--- a/miasm2/arch/msp430/jit.py
+++ b/miasm2/arch/msp430/jit.py
@@ -1,6 +1,6 @@
 from miasm2.jitter.jitload import jitter
-from miasm2.core import asmbloc
-from miasm2.core.utils import *
+from miasm2.core import asmblock
+from miasm2.core.utils import pck16, upck16
 from miasm2.arch.msp430.sem import ir_msp430
 
 import logging
@@ -14,27 +14,27 @@ log.setLevel(logging.CRITICAL)
 class jitter_msp430(jitter):
 
     def __init__(self, *args, **kwargs):
-        sp = asmbloc.asm_symbol_pool()
+        sp = asmblock.AsmSymbolPool()
         jitter.__init__(self, ir_msp430(sp), *args, **kwargs)
         self.vm.set_little_endian()
 
-    def push_uint16_t(self, v):
+    def push_uint16_t(self, value):
         regs = self.cpu.get_gpreg()
         regs['SP'] -= 2
         self.cpu.set_gpreg(regs)
-        self.vm.set_mem(regs['SP'], pck16(v))
+        self.vm.set_mem(regs['SP'], pck16(value))
 
     def pop_uint16_t(self):
         regs = self.cpu.get_gpreg()
-        x = upck16(self.vm.get_mem(regs['SP'], 2))
+        value = upck16(self.vm.get_mem(regs['SP'], 2))
         regs['SP'] += 2
         self.cpu.set_gpreg(regs)
-        return x
+        return value
 
-    def get_stack_arg(self, n):
+    def get_stack_arg(self, index):
         regs = self.cpu.get_gpreg()
-        x = upck16(self.vm.get_mem(regs['SP'] + 2 * n, 2))
-        return x
+        value = upck16(self.vm.get_mem(regs['SP'] + 2 * index, 2))
+        return value
 
     def init_run(self, *args, **kwargs):
         jitter.init_run(self, *args, **kwargs)
diff --git a/miasm2/arch/msp430/sem.py b/miasm2/arch/msp430/sem.py
index 4b52361d..e8eb91cc 100644
--- a/miasm2/arch/msp430/sem.py
+++ b/miasm2/arch/msp430/sem.py
@@ -3,7 +3,7 @@
 from miasm2.expression.expression import *
 from miasm2.arch.msp430.regs import *
 from miasm2.arch.msp430.arch import mn_msp430
-from miasm2.ir.ir import ir
+from miasm2.ir.ir import IntermediateRepresentation
 
 
 # Utils
@@ -412,10 +412,10 @@ def ComposeExprAff(dst, src):
     return e
 
 
-class ir_msp430(ir):
+class ir_msp430(IntermediateRepresentation):
 
     def __init__(self, symbol_pool=None):
-        ir.__init__(self, mn_msp430, None, symbol_pool)
+        IntermediateRepresentation.__init__(self, mn_msp430, None, symbol_pool)
         self.pc = PC
         self.sp = SP
         self.IRDst = ExprId('IRDst', 16)
diff --git a/miasm2/arch/sh4/arch.py b/miasm2/arch/sh4/arch.py
index ae96fef1..634cbf43 100644
--- a/miasm2/arch/sh4/arch.py
+++ b/miasm2/arch/sh4/arch.py
@@ -6,7 +6,6 @@ from miasm2.expression.expression import *
 from collections import defaultdict
 import miasm2.arch.sh4.regs as regs_module
 from miasm2.arch.sh4.regs import *
-from miasm2.core.asmbloc import asm_label
 
 jra = ExprId('jra')
 jrb = ExprId('jrb')
diff --git a/miasm2/arch/x86/arch.py b/miasm2/arch/x86/arch.py
index 8ae6cd31..d686cd55 100644
--- a/miasm2/arch/x86/arch.py
+++ b/miasm2/arch/x86/arch.py
@@ -7,7 +7,7 @@ from miasm2.core.cpu import *
 from collections import defaultdict
 import miasm2.arch.x86.regs as regs_module
 from miasm2.arch.x86.regs import *
-from miasm2.core.asmbloc import asm_label
+from miasm2.core.asmblock import AsmLabel
 
 log = logging.getLogger("x86_arch")
 console_handler = logging.StreamHandler()
@@ -489,7 +489,7 @@ class instruction_x86(instruction):
             return
         expr = self.args[0]
         if isinstance(expr, ExprId):
-            if not isinstance(expr.name, asm_label) and expr not in all_regs_ids:
+            if not isinstance(expr.name, AsmLabel) and expr not in all_regs_ids:
                 raise ValueError("ExprId must be a label or a register")
         elif isinstance(expr, ExprInt):
             ad = expr.arg + int(self.offset)
diff --git a/miasm2/arch/x86/disasm.py b/miasm2/arch/x86/disasm.py
index 0ff55097..fc981c09 100644
--- a/miasm2/arch/x86/disasm.py
+++ b/miasm2/arch/x86/disasm.py
@@ -1,4 +1,4 @@
-from miasm2.core.asmbloc import disasmEngine
+from miasm2.core.asmblock import disasmEngine
 from miasm2.arch.x86.arch import mn_x86
 
 
diff --git a/miasm2/arch/x86/ira.py b/miasm2/arch/x86/ira.py
index 31d38b37..74aa0203 100644
--- a/miasm2/arch/x86/ira.py
+++ b/miasm2/arch/x86/ira.py
@@ -1,9 +1,7 @@
 #-*- coding:utf-8 -*-
 
-from miasm2.expression.expression import ExprAff, ExprOp, ExprId
-from miasm2.core.graph import DiGraph
-from miasm2.core.asmbloc import expr_is_label
-from miasm2.ir.ir import ir, irbloc, AssignBlock
+from miasm2.expression.expression import ExprAff, ExprOp
+from miasm2.ir.ir import AssignBlock
 from miasm2.ir.analysis import ira
 from miasm2.arch.x86.sem import ir_x86_16, ir_x86_32, ir_x86_64
 
@@ -15,21 +13,21 @@ class ir_a_x86_16(ir_x86_16, ira):
         self.ret_reg = self.arch.regs.AX
 
     # for test XXX TODO
-    def set_dead_regs(self, b):
-        b.rw[-1][1].add(self.arch.regs.zf)
-        b.rw[-1][1].add(self.arch.regs.of)
-        b.rw[-1][1].add(self.arch.regs.pf)
-        b.rw[-1][1].add(self.arch.regs.cf)
-        b.rw[-1][1].add(self.arch.regs.nf)
-        b.rw[-1][1].add(self.arch.regs.af)
-
-    def get_out_regs(self, b):
+    def set_dead_regs(self, irblock):
+        irblock.rw[-1][1].add(self.arch.regs.zf)
+        irblock.rw[-1][1].add(self.arch.regs.of)
+        irblock.rw[-1][1].add(self.arch.regs.pf)
+        irblock.rw[-1][1].add(self.arch.regs.cf)
+        irblock.rw[-1][1].add(self.arch.regs.nf)
+        irblock.rw[-1][1].add(self.arch.regs.af)
+
+    def get_out_regs(self, _):
         return set([self.ret_reg, self.sp])
 
     def add_unused_regs(self):
-        leaves = [self.blocs[n] for n in self.g.leafs()]
-        for b in leaves:
-            self.set_dead_regs(b)
+        leaves = [self.blocks[label] for label in self.g.leafs()]
+        for irblock in leaves:
+            self.set_dead_regs(irblock)
 
 class ir_a_x86_32(ir_x86_32, ir_a_x86_16):
 
diff --git a/miasm2/arch/x86/jit.py b/miasm2/arch/x86/jit.py
index 2e483f2a..cfdabf8c 100644
--- a/miasm2/arch/x86/jit.py
+++ b/miasm2/arch/x86/jit.py
@@ -1,8 +1,8 @@
 import logging
 
 from miasm2.jitter.jitload import jitter, named_arguments
-from miasm2.core import asmbloc
-from miasm2.core.utils import *
+from miasm2.core import asmblock
+from miasm2.core.utils import pck16, pck32, pck64, upck16, upck32, upck64
 from miasm2.arch.x86.sem import ir_x86_16, ir_x86_32, ir_x86_64
 from miasm2.jitter.codegen import CGen
 
@@ -37,28 +37,27 @@ class jitter_x86_16(jitter):
     C_Gen = x86_32_CGen
 
     def __init__(self, *args, **kwargs):
-        sp = asmbloc.asm_symbol_pool()
+        sp = asmblock.AsmSymbolPool()
         jitter.__init__(self, ir_x86_16(sp), *args, **kwargs)
         self.vm.set_little_endian()
         self.ir_arch.do_stk_segm = False
         self.orig_irbloc_fix_regs_for_mode = self.ir_arch.irbloc_fix_regs_for_mode
         self.ir_arch.irbloc_fix_regs_for_mode = self.ir_archbloc_fix_regs_for_mode
 
-    def ir_archbloc_fix_regs_for_mode(self, irbloc, attrib=64):
-        self.orig_irbloc_fix_regs_for_mode(irbloc, 64)
+    def ir_archbloc_fix_regs_for_mode(self, irblock, attrib=64):
+        self.orig_irbloc_fix_regs_for_mode(irblock, 64)
 
-    def push_uint16_t(self, v):
+    def push_uint16_t(self, value):
         self.cpu.SP -= self.ir_arch.sp.size / 8
-        self.vm.set_mem(self.cpu.SP, pck16(v))
+        self.vm.set_mem(self.cpu.SP, pck16(value))
 
     def pop_uint16_t(self):
-        x = upck16(self.vm.get_mem(self.cpu.SP, self.ir_arch.sp.size / 8))
+        value = upck16(self.vm.get_mem(self.cpu.SP, self.ir_arch.sp.size / 8))
         self.cpu.SP += self.ir_arch.sp.size / 8
-        return x
+        return value
 
-    def get_stack_arg(self, n):
-        x = upck16(self.vm.get_mem(self.cpu.SP + 4 * n, 4))
-        return x
+    def get_stack_arg(self, index):
+        return upck16(self.vm.get_mem(self.cpu.SP + 4 * index, 4))
 
     def init_run(self, *args, **kwargs):
         jitter.init_run(self, *args, **kwargs)
@@ -70,7 +69,7 @@ class jitter_x86_32(jitter):
     C_Gen = x86_32_CGen
 
     def __init__(self, *args, **kwargs):
-        sp = asmbloc.asm_symbol_pool()
+        sp = asmblock.AsmSymbolPool()
         jitter.__init__(self, ir_x86_32(sp), *args, **kwargs)
         self.vm.set_little_endian()
         self.ir_arch.do_stk_segm = False
@@ -78,21 +77,20 @@ class jitter_x86_32(jitter):
         self.orig_irbloc_fix_regs_for_mode = self.ir_arch.irbloc_fix_regs_for_mode
         self.ir_arch.irbloc_fix_regs_for_mode = self.ir_archbloc_fix_regs_for_mode
 
-    def ir_archbloc_fix_regs_for_mode(self, irbloc, attrib=64):
-        self.orig_irbloc_fix_regs_for_mode(irbloc, 64)
+    def ir_archbloc_fix_regs_for_mode(self, irblock, attrib=64):
+        self.orig_irbloc_fix_regs_for_mode(irblock, 64)
 
-    def push_uint32_t(self, v):
+    def push_uint32_t(self, value):
         self.cpu.ESP -= self.ir_arch.sp.size / 8
-        self.vm.set_mem(self.cpu.ESP, pck32(v))
+        self.vm.set_mem(self.cpu.ESP, pck32(value))
 
     def pop_uint32_t(self):
-        x = upck32(self.vm.get_mem(self.cpu.ESP, self.ir_arch.sp.size / 8))
+        value = upck32(self.vm.get_mem(self.cpu.ESP, self.ir_arch.sp.size / 8))
         self.cpu.ESP += self.ir_arch.sp.size / 8
-        return x
+        return value
 
-    def get_stack_arg(self, n):
-        x = upck32(self.vm.get_mem(self.cpu.ESP + 4 * n, 4))
-        return x
+    def get_stack_arg(self, index):
+        return upck32(self.vm.get_mem(self.cpu.ESP + 4 * index, 4))
 
     # calling conventions
 
@@ -131,7 +129,7 @@ class jitter_x86_64(jitter):
     C_Gen = x86_64_CGen
 
     def __init__(self, *args, **kwargs):
-        sp = asmbloc.asm_symbol_pool()
+        sp = asmblock.AsmSymbolPool()
         jitter.__init__(self, ir_x86_64(sp), *args, **kwargs)
         self.vm.set_little_endian()
         self.ir_arch.do_stk_segm = False
@@ -139,21 +137,20 @@ class jitter_x86_64(jitter):
         self.orig_irbloc_fix_regs_for_mode = self.ir_arch.irbloc_fix_regs_for_mode
         self.ir_arch.irbloc_fix_regs_for_mode = self.ir_archbloc_fix_regs_for_mode
 
-    def ir_archbloc_fix_regs_for_mode(self, irbloc, attrib=64):
-        self.orig_irbloc_fix_regs_for_mode(irbloc, 64)
+    def ir_archbloc_fix_regs_for_mode(self, irblock, attrib=64):
+        self.orig_irbloc_fix_regs_for_mode(irblock, 64)
 
-    def push_uint64_t(self, v):
+    def push_uint64_t(self, value):
         self.cpu.RSP -= self.ir_arch.sp.size / 8
-        self.vm.set_mem(self.cpu.RSP, pck64(v))
+        self.vm.set_mem(self.cpu.RSP, pck64(value))
 
     def pop_uint64_t(self):
-        x = upck64(self.vm.get_mem(self.cpu.RSP, self.ir_arch.sp.size / 8))
+        value = upck64(self.vm.get_mem(self.cpu.RSP, self.ir_arch.sp.size / 8))
         self.cpu.RSP += self.ir_arch.sp.size / 8
-        return x
+        return value
 
-    def get_stack_arg(self, n):
-        x = upck64(self.vm.get_mem(self.cpu.RSP + 8 * n, 8))
-        return x
+    def get_stack_arg(self, index):
+        return upck64(self.vm.get_mem(self.cpu.RSP + 8 * index, 8))
 
     @named_arguments
     def func_args_stdcall(self, n_args):
diff --git a/miasm2/arch/x86/sem.py b/miasm2/arch/x86/sem.py
index 18a1421e..729806b5 100644
--- a/miasm2/arch/x86/sem.py
+++ b/miasm2/arch/x86/sem.py
@@ -21,7 +21,7 @@ from miasm2.expression.simplifications import expr_simp
 from miasm2.arch.x86.regs import *
 from miasm2.arch.x86.arch import mn_x86, repeat_mn, replace_regs
 from miasm2.expression.expression_helper import expr_cmps, expr_cmpu
-from miasm2.ir.ir import ir, irbloc
+from miasm2.ir.ir import IntermediateRepresentation, IRBlock
 from miasm2.core.sembuilder import SemBuilder
 import math
 import struct
@@ -277,7 +277,7 @@ def gen_fcmov(ir, instr, cond, arg1, arg2, mov_if):
     e_do, extra_irs = [m2_expr.ExprAff(arg1, arg2)], []
     e_do.append(m2_expr.ExprAff(ir.IRDst, lbl_skip))
     e.append(m2_expr.ExprAff(ir.IRDst, m2_expr.ExprCond(cond, dstA, dstB)))
-    return e, [irbloc(lbl_do.name, [e_do])]
+    return e, [IRBlock(lbl_do.name, [e_do])]
 
 
 def gen_cmov(ir, instr, cond, dst, src, mov_if):
@@ -297,7 +297,7 @@ def gen_cmov(ir, instr, cond, dst, src, mov_if):
     e_do, extra_irs = mov(ir, instr, dst, src)
     e_do.append(m2_expr.ExprAff(ir.IRDst, lbl_skip))
     e.append(m2_expr.ExprAff(ir.IRDst, m2_expr.ExprCond(cond, dstA, dstB)))
-    return e, [irbloc(lbl_do.name, [e_do])]
+    return e, [IRBlock(lbl_do.name, [e_do])]
 
 
 def mov(_, instr, dst, src):
@@ -518,7 +518,7 @@ def _rotate_tpl(ir, instr, dst, src, op, left=False, include_cf=False):
     e_do.append(m2_expr.ExprAff(ir.IRDst, lbl_skip))
     e.append(m2_expr.ExprAff(
         ir.IRDst, m2_expr.ExprCond(shifter, lbl_do, lbl_skip)))
-    return (e, [irbloc(lbl_do.name, [e_do])])
+    return (e, [IRBlock(lbl_do.name, [e_do])])
 
 
 def l_rol(ir, instr, dst, src):
@@ -615,7 +615,7 @@ def _shift_tpl(op, ir, instr, a, b, c=None, op_inv=None, left=False,
     e_do.append(m2_expr.ExprAff(ir.IRDst, lbl_skip))
     e.append(m2_expr.ExprAff(ir.IRDst, m2_expr.ExprCond(shifter, lbl_do,
                                                         lbl_skip)))
-    return e, [irbloc(lbl_do.name, [e_do])]
+    return e, [IRBlock(lbl_do.name, [e_do])]
 
 
 def sar(ir, instr, dst, src):
@@ -963,7 +963,7 @@ def cmps(ir, instr, size):
     e0.append(m2_expr.ExprAff(b.arg,
                               b.arg + m2_expr.ExprInt(size / 8, b.arg.size)))
     e0.append(m2_expr.ExprAff(ir.IRDst, lbl_next))
-    e0 = irbloc(lbl_df_0.name, [e0])
+    e0 = IRBlock(lbl_df_0.name, [e0])
 
     e1 = []
     e1.append(m2_expr.ExprAff(a.arg,
@@ -971,7 +971,7 @@ def cmps(ir, instr, size):
     e1.append(m2_expr.ExprAff(b.arg,
                               b.arg - m2_expr.ExprInt(size / 8, b.arg.size)))
     e1.append(m2_expr.ExprAff(ir.IRDst, lbl_next))
-    e1 = irbloc(lbl_df_1.name, [e1])
+    e1 = IRBlock(lbl_df_1.name, [e1])
 
     e.append(m2_expr.ExprAff(ir.IRDst,
                              m2_expr.ExprCond(df, lbl_df_1, lbl_df_0)))
@@ -992,13 +992,13 @@ def scas(ir, instr, size):
     e0.append(m2_expr.ExprAff(a.arg,
                               a.arg + m2_expr.ExprInt(size / 8, a.arg.size)))
     e0.append(m2_expr.ExprAff(ir.IRDst, lbl_next))
-    e0 = irbloc(lbl_df_0.name, [e0])
+    e0 = IRBlock(lbl_df_0.name, [e0])
 
     e1 = []
     e1.append(m2_expr.ExprAff(a.arg,
                               a.arg - m2_expr.ExprInt(size / 8, a.arg.size)))
     e1.append(m2_expr.ExprAff(ir.IRDst, lbl_next))
-    e1 = irbloc(lbl_df_1.name, [e1])
+    e1 = IRBlock(lbl_df_1.name, [e1])
 
     e.append(m2_expr.ExprAff(ir.IRDst,
                              m2_expr.ExprCond(df, lbl_df_1, lbl_df_0)))
@@ -1641,12 +1641,12 @@ def stos(ir, instr, size):
     e0 = []
     e0.append(m2_expr.ExprAff(addr_o, addr_p))
     e0.append(m2_expr.ExprAff(ir.IRDst, lbl_next))
-    e0 = irbloc(lbl_df_0.name, [e0])
+    e0 = IRBlock(lbl_df_0.name, [e0])
 
     e1 = []
     e1.append(m2_expr.ExprAff(addr_o, addr_m))
     e1.append(m2_expr.ExprAff(ir.IRDst, lbl_next))
-    e1 = irbloc(lbl_df_1.name, [e1])
+    e1 = IRBlock(lbl_df_1.name, [e1])
 
     e = []
     e.append(m2_expr.ExprAff(ir.ExprMem(addr, size), b))
@@ -1676,12 +1676,12 @@ def lods(ir, instr, size):
     e0 = []
     e0.append(m2_expr.ExprAff(addr_o, addr_p))
     e0.append(m2_expr.ExprAff(ir.IRDst, lbl_next))
-    e0 = irbloc(lbl_df_0.name, [e0])
+    e0 = IRBlock(lbl_df_0.name, [e0])
 
     e1 = []
     e1.append(m2_expr.ExprAff(addr_o, addr_m))
     e1.append(m2_expr.ExprAff(ir.IRDst, lbl_next))
-    e1 = irbloc(lbl_df_1.name, [e1])
+    e1 = IRBlock(lbl_df_1.name, [e1])
 
     e = []
     if instr.mode == 64 and b.size == 32:
@@ -1718,13 +1718,13 @@ def movs(ir, instr, size):
     e0.append(m2_expr.ExprAff(a, a + m2_expr.ExprInt(size / 8, a.size)))
     e0.append(m2_expr.ExprAff(b, b + m2_expr.ExprInt(size / 8, b.size)))
     e0.append(m2_expr.ExprAff(ir.IRDst, lbl_next))
-    e0 = irbloc(lbl_df_0.name, [e0])
+    e0 = IRBlock(lbl_df_0.name, [e0])
 
     e1 = []
     e1.append(m2_expr.ExprAff(a, a - m2_expr.ExprInt(size / 8, a.size)))
     e1.append(m2_expr.ExprAff(b, b - m2_expr.ExprInt(size / 8, b.size)))
     e1.append(m2_expr.ExprAff(ir.IRDst, lbl_next))
-    e1 = irbloc(lbl_df_1.name, [e1])
+    e1 = IRBlock(lbl_df_1.name, [e1])
 
     e.append(m2_expr.ExprAff(ir.IRDst,
                              m2_expr.ExprCond(df, lbl_df_1, lbl_df_0)))
@@ -2758,8 +2758,8 @@ def bsr_bsf(ir, instr, dst, src, op_name):
     e_src_not_null.append(m2_expr.ExprAff(dst, m2_expr.ExprOp(op_name, src)))
     e_src_not_null.append(aff_dst)
 
-    return e, [irbloc(lbl_src_null.name, [e_src_null]),
-               irbloc(lbl_src_not_null.name, [e_src_not_null])]
+    return e, [IRBlock(lbl_src_null.name, [e_src_null]),
+               IRBlock(lbl_src_not_null.name, [e_src_not_null])]
 
 
 def bsf(ir, instr, dst, src):
@@ -3655,7 +3655,7 @@ def ps_rl_ll(ir, instr, dst, src, op, size):
     e_do = []
     e.append(m2_expr.ExprAff(dst[0:dst.size], m2_expr.ExprCompose(*slices)))
     e_do.append(m2_expr.ExprAff(ir.IRDst, lbl_next))
-    return e, [irbloc(lbl_do.name, [e_do]), irbloc(lbl_zero.name, [e_zero])]
+    return e, [IRBlock(lbl_do.name, [e_do]), IRBlock(lbl_zero.name, [e_zero])]
 
 
 def psrlw(ir, instr, dst, src):
@@ -4484,10 +4484,10 @@ mnemo_func = {'mov': mov,
               }
 
 
-class ir_x86_16(ir):
+class ir_x86_16(IntermediateRepresentation):
 
     def __init__(self, symbol_pool=None):
-        ir.__init__(self, mn_x86, 16, symbol_pool)
+        IntermediateRepresentation.__init__(self, mn_x86, 16, symbol_pool)
         self.do_stk_segm = False
         self.do_ds_segm = False
         self.do_str_segm = False
@@ -4571,8 +4571,8 @@ class ir_x86_16(ir):
         lbl_skip = m2_expr.ExprId(self.get_next_label(instr), self.IRDst.size)
         lbl_next = m2_expr.ExprId(self.get_next_label(instr), self.IRDst.size)
 
-        for b in extra_ir:
-            for ir in b.irs:
+        for irblock in extra_ir:
+            for ir in irblock.irs:
                 for i, e in enumerate(ir):
                     src = e.src.replace_expr({lbl_next: lbl_end})
                     ir[i] = m2_expr.ExprAff(e.dst, src)
@@ -4583,10 +4583,10 @@ class ir_x86_16(ir):
         cond_bloc.append(m2_expr.ExprAff(self.IRDst, m2_expr.ExprCond(c_cond,
                                                                       lbl_skip,
                                                                       lbl_do)))
-        cond_bloc = irbloc(lbl_end.name, [cond_bloc])
+        cond_bloc = IRBlock(lbl_end.name, [cond_bloc])
         e_do = instr_ir
 
-        c = irbloc(lbl_do.name, [e_do])
+        c = IRBlock(lbl_do.name, [e_do])
         c.except_automod = False
         e_n = [m2_expr.ExprAff(self.IRDst, m2_expr.ExprCond(c_reg, lbl_do,
                                                             lbl_skip))]
@@ -4622,7 +4622,7 @@ class ir_x86_16(ir):
 class ir_x86_32(ir_x86_16):
 
     def __init__(self, symbol_pool=None):
-        ir.__init__(self, mn_x86, 32, symbol_pool)
+        IntermediateRepresentation.__init__(self, mn_x86, 32, symbol_pool)
         self.do_stk_segm = False
         self.do_ds_segm = False
         self.do_str_segm = False
@@ -4636,7 +4636,7 @@ class ir_x86_32(ir_x86_16):
 class ir_x86_64(ir_x86_16):
 
     def __init__(self, symbol_pool=None):
-        ir.__init__(self, mn_x86, 64, symbol_pool)
+        IntermediateRepresentation.__init__(self, mn_x86, 64, symbol_pool)
         self.do_stk_segm = False
         self.do_ds_segm = False
         self.do_str_segm = False
@@ -4656,8 +4656,8 @@ class ir_x86_64(ir_x86_16):
             src = src.replace_expr(
                 {self.pc: m2_expr.ExprInt64(instr.offset + instr.l)})
             instr_ir[i] = m2_expr.ExprAff(dst, src)
-        for b in extra_ir:
-            for irs in b.irs:
+        for irblock in extra_ir:
+            for irs in irblock.irs:
                 for i, expr in enumerate(irs):
                     dst, src = expr.dst, expr.src
                     if dst != self.pc: