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-rw-r--r--miasm2/arch/aarch64/arch.py2
-rw-r--r--miasm2/arch/aarch64/sem.py4
-rw-r--r--miasm2/arch/arm/arch.py2
-rw-r--r--miasm2/arch/arm/sem.py17
-rw-r--r--miasm2/arch/ppc/arch.py2
-rw-r--r--miasm2/arch/ppc/sem.py6
-rw-r--r--miasm2/arch/x86/arch.py7
-rw-r--r--miasm2/arch/x86/sem.py8
8 files changed, 14 insertions, 34 deletions
diff --git a/miasm2/arch/aarch64/arch.py b/miasm2/arch/aarch64/arch.py
index 15a7bd77..598aca83 100644
--- a/miasm2/arch/aarch64/arch.py
+++ b/miasm2/arch/aarch64/arch.py
@@ -357,7 +357,7 @@ class instruction_aarch64(instruction):
             raise NotImplementedError("bad op")
 
     def dstflow(self):
-        return self.name in self.name in BRCOND + ["B", "BL", "BR", "BLR"]
+        return self.name in BRCOND + ["B", "BL", "BR", "BLR"]
 
     def mnemo_flow_to_dst_index(self, name):
         if self.name in ['CBZ', 'CBNZ']:
diff --git a/miasm2/arch/aarch64/sem.py b/miasm2/arch/aarch64/sem.py
index 4247a47f..3f70d7a7 100644
--- a/miasm2/arch/aarch64/sem.py
+++ b/miasm2/arch/aarch64/sem.py
@@ -723,7 +723,7 @@ def mrs(ir, insr, arg1, arg2, arg3, arg4, arg5):
         out.append(nf)
         e.append(ExprAff(arg1, ExprCompose(*out).zeroExtend(arg1.size)))
     else:
-        raise NotImplementedError("MSR not implemented")
+        raise NotImplementedError("MRS not implemented")
     return e, []
 
 def msr(ir, instr, arg1, arg2, arg3, arg4, arg5):
@@ -735,7 +735,7 @@ def msr(ir, instr, arg1, arg2, arg3, arg4, arg5):
         e.append(ExprAff(cf, arg5[29:30]))
         e.append(ExprAff(of, arg5[28:29]))
     else:
-        raise NotImplementedError("MRS not implemented")
+        raise NotImplementedError("MSR not implemented")
     return e, []
 
 
diff --git a/miasm2/arch/arm/arch.py b/miasm2/arch/arm/arch.py
index 74d4a89f..e1b015a5 100644
--- a/miasm2/arch/arm/arch.py
+++ b/miasm2/arch/arm/arch.py
@@ -2373,7 +2373,7 @@ armtop("addsp", [bs('10110000'), bs_addsubsp_name, sp, off7], [sp, off7])
 armtop("pushpop", [bs('1011'), bs_pushpop_name, bs('10'), pclr, trlistpclr], [trlistpclr])
 armtop("btransfersp", [bs('1100'),  bs_tbtransfer_name, rbl_wb, trlist])
 armtop("br", [bs('1101'),  bs_br_name, offs8])
-armtop("blx", [bs("01000111"),  bs('10'), rnl, bs('000')])
+armtop("blx", [bs("01000111"),  bs('1'), rm, bs('000')])
 armtop("svc", [bs('11011111'),  imm8])
 armtop("b", [bs('11100'),  offs11])
 armtop("und", [bs('1101'), bs('1110'), imm8_d1])
diff --git a/miasm2/arch/arm/sem.py b/miasm2/arch/arm/sem.py
index 7dca6242..600ad586 100644
--- a/miasm2/arch/arm/sem.py
+++ b/miasm2/arch/arm/sem.py
@@ -283,7 +283,8 @@ def rsb(ir, instr, a, b, c=None):
     e = []
     if c is None:
         b, c = a, b
-    r = c - b
+    arg1, arg2 = c, b
+    r = arg1 - arg2
     e.append(ExprAff(a, r))
     dst = get_dst(a)
     if dst is not None:
@@ -297,10 +298,8 @@ def rsbs(ir, instr, a, b, c=None):
         b, c = a, b
     arg1, arg2 = c, b
     r = arg1 - arg2
-
     e += update_flag_arith_sub_zn(arg1, arg2)
     e += update_flag_arith_sub_co(arg1, arg2)
-
     e.append(ExprAff(a, r))
     dst = get_dst(a)
     if dst is not None:
@@ -398,11 +397,8 @@ def l_cmp(ir, instr, a, b, c=None):
     if c is None:
         b, c = a, b
     arg1, arg2 = b, c
-    r = b - c
-
     e += update_flag_arith_sub_zn(arg1, arg2)
     e += update_flag_arith_sub_co(arg1, arg2)
-
     return e, []
 
 
@@ -411,11 +407,8 @@ def cmn(ir, instr, a, b, c=None):
     if c is None:
         b, c = a, b
     arg1, arg2 = b, c
-    r = b + c
-
     e += update_flag_arith_add_zn(arg1, arg2)
     e += update_flag_arith_add_co(arg1, arg2)
-
     return e, []
 
 
@@ -448,7 +441,7 @@ def orrs(ir, instr, a, b, c=None):
     if c is None:
         b, c = a, b
     arg1, arg2 = b, c
-    r = b | c
+    r = arg1 | arg2
 
     e += [ExprAff(zf, ExprOp('FLAG_EQ', r))]
     e += update_flag_nf(r)
@@ -525,7 +518,7 @@ def mrs(ir, instr, a, b):
         out.append(nf)
         e.append(ExprAff(a, ExprCompose(*out)))
     else:
-        raise NotImplementedError("MSR not implemented")
+        raise NotImplementedError("MRS not implemented")
     return e, []
 
 def msr(ir, instr, a, b):
@@ -536,7 +529,7 @@ def msr(ir, instr, a, b):
         e.append(ExprAff(cf, b[29:30]))
         e.append(ExprAff(of, b[28:29]))
     else:
-        raise NotImplementedError("MRS not implemented")
+        raise NotImplementedError("MSR not implemented")
     return e, []
 
 
diff --git a/miasm2/arch/ppc/arch.py b/miasm2/arch/ppc/arch.py
index c100cde3..f198312e 100644
--- a/miasm2/arch/ppc/arch.py
+++ b/miasm2/arch/ppc/arch.py
@@ -313,7 +313,7 @@ class ppc_gpreg_or_0(ppc_reg):
     parser = reg_info.parser
 
     def decode(self, v):
-        ret = super(ppc_reg, self).decode(v)
+        ret = super(ppc_gpreg_or_0, self).decode(v)
         if ret == False:
             return False
         reg = self.expr
diff --git a/miasm2/arch/ppc/sem.py b/miasm2/arch/ppc/sem.py
index 3c885d12..82a662c2 100644
--- a/miasm2/arch/ppc/sem.py
+++ b/miasm2/arch/ppc/sem.py
@@ -135,7 +135,7 @@ def mn_do_cr(ir, instr, crd, cra, crb):
     elif op == 'XOR':
         r = a ^ b
     else:
-        raise "Unknown operation on CR"
+        raise RuntimeError("Unknown operation on CR")
     return [ ExprAff(d, r) ], []
 
 def mn_do_div(ir, instr, rd, ra, rb):
@@ -294,10 +294,10 @@ def mn_do_lswi(ir, instr, rd, ra, nb):
     if nb == 0:
         nb = 32
     i = 32
-    raise "%r not implemented" % instr
+    raise RuntimeError("%r not implemented" % instr)
 
 def mn_do_lswx(ir, instr, rd, ra, nb):
-    raise "%r not implemented" % instr
+    raise RuntimeError("%r not implemented" % instr)
 
 def mn_do_mcrf(ir, instr, crfd, crfs):
     ret = []
diff --git a/miasm2/arch/x86/arch.py b/miasm2/arch/x86/arch.py
index 3e41d46e..2abd5bbc 100644
--- a/miasm2/arch/x86/arch.py
+++ b/miasm2/arch/x86/arch.py
@@ -939,7 +939,6 @@ class bs_modname_size(bs_divert):
                     osize = v_opmode_info(size, opmode, 1, 0)
                     nfields[i] = f
                     nfields = nfields[:-1]
-                    args = dict(self.args)
                     ndct = dict(dct)
                     if osize in self.args['name']:
                         ndct['name'] = self.args['name'][osize]
@@ -951,7 +950,6 @@ class bs_modname_size(bs_divert):
                     f = bs("0", l=0, cls=(bs_fbit,), fname="rex_w")
                     osize = v_opmode_info(size, opmode, 0, 0)
                     nfields[i] = f
-                    args = dict(self.args)
                     ndct = dict(dct)
                     if osize in self.args['name']:
                         ndct['name'] = self.args['name'][osize]
@@ -960,7 +958,6 @@ class bs_modname_size(bs_divert):
                 l = opmode_prefix((dct['mode'], dct['opmode'], dct['admode']))
                 osize = v_opmode_info(size, opmode, None, 0)
                 nfields = fields[:-1]
-                args = dict(self.args)
                 ndct = dict(dct)
                 if osize in self.args['name']:
                     ndct['name'] = self.args['name'][osize]
@@ -2897,9 +2894,7 @@ class bs_rel_off(bs_cond_imm):
         if not isinstance(self.expr, ExprInt):
             raise StopIteration
         arg0_expr = self.parent.args[0].expr
-        if self.l != 0:
-            l = self.l
-        else:
+        if self.l == 0:
             l = self.parent.v_opmode()
             self.l = l
         l = offsize(self.parent)
diff --git a/miasm2/arch/x86/sem.py b/miasm2/arch/x86/sem.py
index f07e2285..816608cb 100644
--- a/miasm2/arch/x86/sem.py
+++ b/miasm2/arch/x86/sem.py
@@ -1441,7 +1441,6 @@ def ret(ir, instr, src=None):
     myesp = mRSP[instr.mode][:size]
 
     if src is None:
-        src = m2_expr.ExprInt(0, size)
         value = (myesp + (m2_expr.ExprInt((size / 8), size)))
     else:
         src = m2_expr.ExprInt(int(src), size)
@@ -1490,7 +1489,6 @@ def retf(ir, instr, src=None):
 
 
 def leave(ir, instr):
-    opmode, admode = instr.v_opmode(), instr.v_admode()
     size = instr.mode
     myesp = mRSP[size]
     e = []
@@ -4427,7 +4425,6 @@ def pslldq(_, instr, dst, src):
 
 def psrldq(_, instr, dst, src):
     assert src.is_int()
-    e = []
     count = int(src)
     if count > 15:
         return [m2_expr.ExprAff(dst, m2_expr.ExprInt(0, dst.size))], []
@@ -4924,7 +4921,6 @@ def maskmovq(ir, instr, src, mask):
     # Build write blocks
     dst_addr = mRDI[instr.mode]
     for i, start in enumerate(xrange(0, mask.size, 8)):
-        bit = mask[start + 7: start + 8]
         cur_label = write_labels[i]
         next_check_label = check_labels[i + 1] if (i + 1) < len(check_labels) else loc_next_expr
         write_addr = dst_addr + m2_expr.ExprInt(i, dst_addr.size)
@@ -5664,13 +5660,9 @@ class ir_x86_16(IntermediateRepresentation):
             return instr_ir, extra_ir
 
         instr.additional_info.except_on_instr = True
-        # get instruction size
-        s = {"B": 8, "W": 16, "D": 32, 'Q': 64}[instr.name[-1]]
-        size = instr.v_opmode()
         admode = instr.v_admode()
         c_reg = mRCX[instr.mode][:admode]
 
-        out_ir = []
         zf_val = None
         # set if zf is tested (cmps, scas)
         for e in instr_ir:  # +[updt_c]: