3 files changed, 0 insertions, 10 deletions
diff --git a/miasm2/arch/arm/arch.py b/miasm2/arch/arm/arch.py
index 17b57ba4..624642cf 100644
--- a/miasm2/arch/arm/arch.py
+++ b/miasm2/arch/arm/arch.py
@@ -1038,16 +1038,12 @@ class arm_op2(arm_arg):
         shift_kind = shift & 1
         shift_type = (shift >> 1) & 3
         shift >>= 3
-        # print self.parent.immop.value, hex(shift), hex(shift_kind),
-        # hex(shift_type)
         if shift_kind:
             # shift kind is reg
             if shift & 1:
-                # log.debug('error in shift1')
                 return False
             rs = shift >> 1
             if rs == 0xf:
-                # log.debug('error in shift2')
                 return False
             shift_op = regs_expr[rs]
         else:
@@ -2155,12 +2151,10 @@ class armt_rlist_pclr(armt_rlist):
         reg_l = list(e.args)
         self.parent.pclr.value = 0
         if self.parent.pp.value == 0:
-            # print 'push'
             if regs_expr[14] in reg_l:
                 reg_l.remove(regs_expr[14])
                 self.parent.pclr.value = 1
         else:
-            # print 'pop',
             if regs_expr[15] in reg_l:
                 reg_l.remove(regs_expr[15])
                 self.parent.pclr.value = 1
diff --git a/miasm2/arch/arm/sem.py b/miasm2/arch/arm/sem.py
index c80e9826..ccd56e8f 100644
--- a/miasm2/arch/arm/sem.py
+++ b/miasm2/arch/arm/sem.py
@@ -635,7 +635,6 @@ def st_ld_r(ir, instr, a, a2, b, store=False, size=32, s_ext=False, z_ext=False)
         base, off = b.args[0],  b.args[1]  # ExprInt(size/8, 32)
     else:
         base, off = b, ExprInt(0, 32)
-    # print a, wb, base, off, postinc
     if postinc:
         ad = base
     else:
@@ -734,13 +733,11 @@ def ldrsh(ir, instr, a, b):
 def st_ld_m(ir, instr, a, b, store=False, postinc=False, updown=False):
     e = []
     wb = False
-    # sb = False
     dst = None
     if isinstance(a, ExprOp) and a.op == 'wback':
         wb = True
         a = a.args[0]
     if isinstance(b, ExprOp) and b.op == 'sbit':
-        # sb = True
         b = b.args[0]
     regs = b.args
     base = a
diff --git a/miasm2/arch/msp430/sem.py b/miasm2/arch/msp430/sem.py
index 877c2a70..a3521fb5 100644
--- a/miasm2/arch/msp430/sem.py
+++ b/miasm2/arch/msp430/sem.py
@@ -434,7 +434,6 @@ class ir_msp430(IntermediateRepresentation):
         pass
 
     def get_ir(self, instr):
-        # print instr#, args
         args = instr.args
         instr_ir, extra_ir = mnemo_func[instr.name](self, instr, *args)
         self.mod_sr(instr, instr_ir, extra_ir)