4 files changed, 10 insertions, 14 deletions
diff --git a/miasm2/arch/arm/arch.py b/miasm2/arch/arm/arch.py
index e7054b51..c50748e4 100644
--- a/miasm2/arch/arm/arch.py
+++ b/miasm2/arch/arm/arch.py
@@ -1694,10 +1694,12 @@ armop("sxtb", [bs('01101010'), bs('1111'), rd, rot_rm, bs('00'), bs('0111'), rm_
 armop("sxth", [bs('01101011'), bs('1111'), rd, rot_rm, bs('00'), bs('0111'), rm_noarg])
 
 armop("rev", [bs('01101011'), bs('1111'), rd, bs('1111'), bs('0011'), rm])
+armop("rev16", [bs('01101011'), bs('1111'), rd, bs('1111'), bs('1011'), rm])
 
 armop("pld", [bs8(0xF5), bs_addi, bs_rw, bs('01'), mem_rn_imm, bs('1111'), imm12_off])
 
 armop("isb", [bs8(0xF5), bs8(0x7F), bs8(0xF0), bs8(0x6F)])
+armop("nop", [bs8(0xE3), bs8(0x20), bs8(0xF0), bs8(0)])
 
 class arm_widthm1(arm_imm, m_arg):
     def decode(self, v):
diff --git a/miasm2/arch/arm/sem.py b/miasm2/arch/arm/sem.py
index 3e017d1f..782a99fb 100644
--- a/miasm2/arch/arm/sem.py
+++ b/miasm2/arch/arm/sem.py
@@ -1493,6 +1493,7 @@ mnemo_condm0 = {'add': add,
                 'mla': mla,
                 'ldr': ldr,
                 'ldrd': ldrd,
+                'ldrsb': ldrsb,
                 'str': l_str,
                 'strd': l_strd,
                 'b': b,
@@ -1549,7 +1550,6 @@ mnemo_condm1 = {'adds': add,
                 'blx': blx,
 
                 'ldrb': ldrb,
-                'ldrsb': ldrsb,
                 'ldsb': ldrsb,
                 'strb': strb,
                 }
diff --git a/miasm2/arch/x86/regs.py b/miasm2/arch/x86/regs.py
index 84590c75..ef1095e2 100644
--- a/miasm2/arch/x86/regs.py
+++ b/miasm2/arch/x86/regs.py
@@ -235,9 +235,7 @@ reg_mm5 = 'MM5'
 reg_mm6 = 'MM6'
 reg_mm7 = 'MM7'
 
-
-reg_tsc1 = "tsc1"
-reg_tsc2 = "tsc2"
+reg_tsc = "tsc"
 
 reg_float_c0 = 'float_c0'
 reg_float_c1 = 'float_c1'
@@ -321,8 +319,7 @@ DS = ExprId(reg_ds, size=16)
 FS = ExprId(reg_fs, size=16)
 GS = ExprId(reg_gs, size=16)
 
-tsc1 = ExprId(reg_tsc1, size=32)
-tsc2 = ExprId(reg_tsc2, size=32)
+tsc = ExprId(reg_tsc, size=64)
 
 float_c0 = ExprId(reg_float_c0, size=1)
 float_c1 = ExprId(reg_float_c1, size=1)
@@ -388,7 +385,7 @@ all_regs_ids = [
     zf, nf, pf, of, cf, af, df,
     tf, i_f, iopl, nt, rf, vm, ac, vif, vip, i_d,
     float_control, float_eip, float_cs, float_address, float_ds,
-    tsc1, tsc2,
+    tsc,
     ES, CS, SS, DS, FS, GS,
     float_st0, float_st1, float_st2, float_st3,
     float_st4, float_st5, float_st6, float_st7,
@@ -411,7 +408,7 @@ all_regs_ids_no_alias = [
     zf, nf, pf, of, cf, af, df,
     tf, i_f, iopl, nt, rf, vm, ac, vif, vip, i_d,
     float_control, float_eip, float_cs, float_address, float_ds,
-    tsc1, tsc2,
+    tsc,
     ES, CS, SS, DS, FS, GS,
     float_st0, float_st1, float_st2, float_st3,
     float_st4, float_st5, float_st6, float_st7,
diff --git a/miasm2/arch/x86/sem.py b/miasm2/arch/x86/sem.py
index b2ef5a43..d03a7cd4 100644
--- a/miasm2/arch/x86/sem.py
+++ b/miasm2/arch/x86/sem.py
@@ -3040,12 +3040,9 @@ def hlt(_, instr):
 
 def rdtsc(_, instr):
     e = []
-    e.append(m2_expr.ExprAssign(tsc1, tsc1 + m2_expr.ExprInt(1, 32)))
-    e.append(m2_expr.ExprAssign(tsc2, tsc2 + m2_expr.ExprCond(tsc1 - tsc1.mask,
-                                                           m2_expr.ExprInt(0, 32),
-                                                           m2_expr.ExprInt(1, 32))))
-    e.append(m2_expr.ExprAssign(mRAX[32], tsc1))
-    e.append(m2_expr.ExprAssign(mRDX[32], tsc2))
+    e.append(m2_expr.ExprAssign(tsc, tsc + m2_expr.ExprInt(1, 64)))
+    e.append(m2_expr.ExprAssign(mRAX[32], tsc[:32]))
+    e.append(m2_expr.ExprAssign(mRDX[32], tsc[32:]))
     return e, []