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-rw-r--r--miasm2/ir/ir.py26
-rw-r--r--miasm2/ir/symbexec.py3
-rw-r--r--miasm2/ir/symbexec_top.py3
-rw-r--r--miasm2/ir/translators/C.py12
4 files changed, 34 insertions, 10 deletions
diff --git a/miasm2/ir/ir.py b/miasm2/ir/ir.py
index 64eb3463..1c6895e0 100644
--- a/miasm2/ir/ir.py
+++ b/miasm2/ir/ir.py
@@ -177,6 +177,9 @@ class AssignBlock(object):
             return False
         return all(other[dst] == src for dst, src in self.iteritems())
 
+    def __ne__(self, other):
+        return not self.__eq__(other)
+
     def __len__(self):
         return len(self._assigns)
 
@@ -240,15 +243,18 @@ class AssignBlock(object):
         return m2_expr.ExprAff(dst, self[dst])
 
     def simplify(self, simplifier):
-        """Return a new AssignBlock with expression simplified
-        @simplifier: ExpressionSimplifier instance"""
+        """
+        Return a new AssignBlock with expression simplified
+
+        @simplifier: ExpressionSimplifier instance
+        """
         new_assignblk = {}
         for dst, src in self.iteritems():
             if dst == src:
                 continue
-            src = simplifier(src)
-            dst = simplifier(dst)
-            new_assignblk[dst] = src
+            new_src = simplifier(src)
+            new_dst = simplifier(dst)
+            new_assignblk[new_dst] = new_src
         return AssignBlock(irs=new_assignblk, instr=self.instr)
 
 
@@ -687,12 +693,16 @@ class IntermediateRepresentation(object):
         Simplify expressions in each irblocks
         @simplifier: ExpressionSimplifier instance
         """
+        modified = False
         for label, block in self.blocks.iteritems():
             assignblks = []
             for assignblk in block:
                 new_assignblk = assignblk.simplify(simplifier)
+                if assignblk != new_assignblk:
+                    modified = True
                 assignblks.append(new_assignblk)
             self.blocks[label] = IRBlock(label, assignblks)
+        return modified
 
     def replace_expr_in_ir(self, bloc, rep):
         for assignblk in bloc:
@@ -808,6 +818,10 @@ class IntermediateRepresentation(object):
                 continue
             if not expr_is_label(assignblk[self.IRDst]):
                 continue
+            dst = assignblk[self.IRDst].name
+            if dst == block.label:
+                # Infinite loop block
+                continue
             jmp_blocks.add(block.label)
 
         # Remove them, relink graph
@@ -844,7 +858,7 @@ class IntermediateRepresentation(object):
                         self.graph.add_uniq_edge(lbl, dst_label)
                         modified = True
                     if dst.src1 == dst.src2:
-                        dst = src1
+                        dst = dst.src1
                 else:
                     continue
                 new_parent = parent.set_dst(dst)
diff --git a/miasm2/ir/symbexec.py b/miasm2/ir/symbexec.py
index 3cde2af7..4070f261 100644
--- a/miasm2/ir/symbexec.py
+++ b/miasm2/ir/symbexec.py
@@ -53,6 +53,9 @@ class SymbolicState(StateEngine):
             return False
         return self.symbols == other.symbols
 
+    def __ne__(self, other):
+        return not self.__eq__(other)
+
     def __iter__(self):
         for dst, src in self._symbols:
             yield dst, src
diff --git a/miasm2/ir/symbexec_top.py b/miasm2/ir/symbexec_top.py
index 71837ed0..1e1e76e9 100644
--- a/miasm2/ir/symbexec_top.py
+++ b/miasm2/ir/symbexec_top.py
@@ -39,6 +39,9 @@ class SymbolicStateTop(StateEngine):
         return (self.symbols == other.symbols and
                 self.regstop == other.regstop)
 
+    def __ne__(self, other):
+        return not self.__eq__(other)
+
     def __iter__(self):
         for dst, src in self._symbols:
             yield dst, src
diff --git a/miasm2/ir/translators/C.py b/miasm2/ir/translators/C.py
index 95502a15..0e285669 100644
--- a/miasm2/ir/translators/C.py
+++ b/miasm2/ir/translators/C.py
@@ -94,12 +94,16 @@ class TranslatorC(Translator):
                                                    self.from_expr(expr.args[0]),
                                                    self.from_expr(expr.args[1]),
                                                    size2mask(expr.args[0].size))
-            elif (expr.op.startswith('cpuid') or
-                  expr.op.startswith("fcom")  or
+            elif expr.op == 'cpuid':
+                return "%s(%s, %s)" % (expr.op,
+                                       self.from_expr(expr.args[0]),
+                                       self.from_expr(expr.args[1]))
+            elif (expr.op.startswith("fcom")  or
                   expr.op in ["fadd", "fsub", "fdiv", 'fmul', "fscale",
                               "fprem", "fprem_lsb", "fyl2x", "fpatan"]):
-                return "%s(%s, %s)" % (expr.op, self.from_expr(expr.args[0]),
-                                       self.from_expr(expr.args[1]))
+                return "fpu_%s(%s, %s)" % (expr.op,
+                                           self.from_expr(expr.args[0]),
+                                           self.from_expr(expr.args[1]))
             elif expr.op == "segm":
                 return "segm2addr(jitcpu, %s, %s)" % (
                     self.from_expr(expr.args[0]), self.from_expr(expr.args[1]))