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-rw-r--r--miasm2/jitter/Jittcc.c26
-rw-r--r--miasm2/jitter/arch/JitCore.c10
-rw-r--r--miasm2/jitter/arch/JitCore.h7
-rw-r--r--miasm2/jitter/arch/JitCore_arm.h3
-rw-r--r--miasm2/jitter/arch/JitCore_mips32.h4
-rw-r--r--miasm2/jitter/arch/JitCore_msp430.h3
-rw-r--r--miasm2/jitter/arch/JitCore_x86.h3
-rw-r--r--miasm2/jitter/jitcore.py18
-rw-r--r--miasm2/jitter/jitcore_llvm.py15
-rw-r--r--miasm2/jitter/jitcore_python.py15
-rw-r--r--miasm2/jitter/jitcore_tcc.py27
-rw-r--r--miasm2/jitter/jitload.py20
-rw-r--r--miasm2/jitter/vm_mngr.h1
13 files changed, 97 insertions, 55 deletions
diff --git a/miasm2/jitter/Jittcc.c b/miasm2/jitter/Jittcc.c
index 710a6175..8c5b2046 100644
--- a/miasm2/jitter/Jittcc.c
+++ b/miasm2/jitter/Jittcc.c
@@ -121,17 +121,37 @@ PyObject* tcc_set_emul_lib_path(PyObject* self, PyObject* args)
 }
 
 
+typedef struct {
+	uint8_t is_local;
+	uint64_t address;
+} block_id;
+
+
 PyObject* tcc_exec_bloc(PyObject* self, PyObject* args)
 {
-	PyObject* (*func)(void*, void*);
+	//PyObject* (*func)(void*, void*);
+	block_id (*func)(void*, void*);
 	uint64_t vm;
 	uint64_t cpu;
 	PyObject* ret;
+	block_id BlockDst;
 
 	if (!PyArg_ParseTuple(args, "KKK", &func, &cpu, &vm))
 		return NULL;
-	ret = func((void*)cpu, (void*)vm);
-	return ret;
+	BlockDst = func((void*)cpu, (void*)vm);
+
+	ret = PyTuple_New(2);
+	if (ret == NULL) {
+		fprintf(stderr, "Erreur alloc!\n");
+		exit(1);
+	}
+
+	if (BlockDst.is_local == 1) {
+		fprintf(stderr, "return on local label!\n");
+		exit(1);
+	}
+
+	return PyLong_FromUnsignedLongLong(BlockDst.address);
 }
 
 PyObject* tcc_compil(PyObject* self, PyObject* args)
diff --git a/miasm2/jitter/arch/JitCore.c b/miasm2/jitter/arch/JitCore.c
new file mode 100644
index 00000000..739beb74
--- /dev/null
+++ b/miasm2/jitter/arch/JitCore.c
@@ -0,0 +1,10 @@
+#include <Python.h>
+#include "JitCore.h"
+
+block_id Resolve_dst(uint64_t addr, uint64_t is_local)
+{
+	block_id b;
+	b.address = addr;
+	b.is_local = is_local;
+	return b;
+}
diff --git a/miasm2/jitter/arch/JitCore.h b/miasm2/jitter/arch/JitCore.h
index 2686cb46..723a10cc 100644
--- a/miasm2/jitter/arch/JitCore.h
+++ b/miasm2/jitter/arch/JitCore.h
@@ -64,3 +64,10 @@
 		return 0;						\
 	}
 
+
+typedef struct {
+	uint8_t is_local;
+	uint64_t address;
+} block_id;
+
+block_id Resolve_dst(uint64_t addr, uint64_t is_local);
diff --git a/miasm2/jitter/arch/JitCore_arm.h b/miasm2/jitter/arch/JitCore_arm.h
index e92db860..cf985ea7 100644
--- a/miasm2/jitter/arch/JitCore_arm.h
+++ b/miasm2/jitter/arch/JitCore_arm.h
@@ -144,4 +144,5 @@ typedef struct {
 
 
 
-#define RETURN_PC return PyLong_FromUnsignedLongLong(vmcpu->PC);
+//#define RETURN_PC return PyLong_FromUnsignedLongLong(vmcpu->PC);
+#define RETURN_PC return BlockDst;
diff --git a/miasm2/jitter/arch/JitCore_mips32.h b/miasm2/jitter/arch/JitCore_mips32.h
index 65666d88..ac128250 100644
--- a/miasm2/jitter/arch/JitCore_mips32.h
+++ b/miasm2/jitter/arch/JitCore_mips32.h
@@ -239,5 +239,5 @@ typedef struct {
 }vm_cpu_t;
 
 
-
-#define RETURN_PC return PyLong_FromUnsignedLongLong(vmcpu->PC);
+//#define RETURN_PC return PyLong_FromUnsignedLongLong(vmcpu->PC);
+#define RETURN_PC return BlockDst;
diff --git a/miasm2/jitter/arch/JitCore_msp430.h b/miasm2/jitter/arch/JitCore_msp430.h
index c65989b0..e1c001b7 100644
--- a/miasm2/jitter/arch/JitCore_msp430.h
+++ b/miasm2/jitter/arch/JitCore_msp430.h
@@ -156,7 +156,8 @@ typedef struct {
 
 }vm_cpu_t;
 
-#define RETURN_PC return PyLong_FromUnsignedLongLong(vmcpu->PC);
+//#define RETURN_PC return PyLong_FromUnsignedLongLong(vmcpu->PC);
+#define RETURN_PC return BlockDst;
 
 uint16_t bcdadd_16(uint16_t a, uint16_t b);
 
diff --git a/miasm2/jitter/arch/JitCore_x86.h b/miasm2/jitter/arch/JitCore_x86.h
index 5ed0feff..844c13c0 100644
--- a/miasm2/jitter/arch/JitCore_x86.h
+++ b/miasm2/jitter/arch/JitCore_x86.h
@@ -290,4 +290,5 @@ uint16_t umod16(vm_cpu_t* vmcpu, uint16_t a, uint16_t b);
 int16_t idiv16(vm_cpu_t* vmcpu, int16_t a, int16_t b);
 int16_t imod16(vm_cpu_t* vmcpu, int16_t a, int16_t b);
 
-#define RETURN_PC return PyLong_FromUnsignedLongLong(vmcpu->RIP);
+//#define RETURN_PC return PyLong_FromUnsignedLongLong(vmcpu->RIP);
+#define RETURN_PC return BlockDst;
diff --git a/miasm2/jitter/jitcore.py b/miasm2/jitter/jitcore.py
index 81193406..1af7333f 100644
--- a/miasm2/jitter/jitcore.py
+++ b/miasm2/jitter/jitcore.py
@@ -24,13 +24,13 @@ class JitCore(object):
 
     "JiT management. This is an abstract class"
 
-    def __init__(self, my_ir, bs=None):
+    def __init__(self, ir_arch, bs=None):
         """Initialise a JitCore instance.
-        @my_ir: ir instance for current architecture
+        @ir_arch: ir instance for current architecture
         @bs: bitstream
         """
 
-        self.my_ir = my_ir
+        self.ir_arch = ir_arch
         self.bs = bs
         self.known_blocs = {}
         self.lbl2jitbloc = {}
@@ -98,7 +98,7 @@ class JitCore(object):
         @b: the bloc to add
         """
 
-        irblocs = self.my_ir.add_bloc(b, gen_pc_updt = True)
+        irblocs = self.ir_arch.add_bloc(b, gen_pc_updt = True)
         b.irblocs = irblocs
         self.jitirblocs(b.label, irblocs)
 
@@ -109,18 +109,18 @@ class JitCore(object):
         if isinstance(addr, asmbloc.asm_label):
             addr = addr.offset
 
-        l = self.my_ir.symbol_pool.getby_offset_create(addr)
+        l = self.ir_arch.symbol_pool.getby_offset_create(addr)
         cur_bloc = asmbloc.asm_bloc(l)
 
         # Disassemble it
         try:
-            asmbloc.dis_bloc(self.my_ir.arch, self.bs, cur_bloc, addr,
-                             set(), self.my_ir.symbol_pool, [],
+            asmbloc.dis_bloc(self.ir_arch.arch, self.bs, cur_bloc, addr,
+                             set(), self.ir_arch.symbol_pool, [],
                              follow_call=False, patch_instr_symb=True,
                              dontdis_retcall=False,
                              lines_wd=self.options["jit_maxline"],
                              # max 10 asm lines
-                             attrib=self.my_ir.attrib,
+                             attrib=self.ir_arch.attrib,
                              split_dis=self.split_dis)
         except IOError:
             # vm_exception_flag is set
@@ -161,7 +161,7 @@ class JitCore(object):
         """
 
         if lbl is None:
-            lbl = cpu.vm_get_gpreg()[self.my_ir.pc.name]
+            lbl = cpu.vm_get_gpreg()[self.ir_arch.pc.name]
 
         if not lbl in self.lbl2jitbloc:
             # Need to JiT the bloc
diff --git a/miasm2/jitter/jitcore_llvm.py b/miasm2/jitter/jitcore_llvm.py
index 03bfb90b..9d139550 100644
--- a/miasm2/jitter/jitcore_llvm.py
+++ b/miasm2/jitter/jitcore_llvm.py
@@ -19,8 +19,8 @@ class JitCore_LLVM(jitcore.JitCore):
                            "msp430": "JitCore_msp430.so",
                            "mips32": "JitCore_mips32.so"}
 
-    def __init__(self, my_ir, bs=None):
-        super(JitCore_LLVM, self).__init__(my_ir, bs)
+    def __init__(self, ir_arch, bs=None):
+        super(JitCore_LLVM, self).__init__(ir_arch, bs)
 
         self.options.update({"safe_mode": False,   # Verify each function
                              "optimise": False,     # Optimise functions
@@ -31,8 +31,9 @@ class JitCore_LLVM(jitcore.JitCore):
 
         self.exec_wrapper = Jitllvm.llvm_exec_bloc
         self.exec_engines = []
+        self.ir_arch = ir_arch
 
-    def load(self, arch):
+    def load(self):
 
         # Library to load within Jit context
         libs_to_load = []
@@ -42,7 +43,7 @@ class JitCore_LLVM(jitcore.JitCore):
         lib_dir = os.path.join(lib_dir, 'arch')
         try:
             jit_lib = os.path.join(
-                lib_dir, self.arch_dependent_libs[arch.name])
+                lib_dir, self.arch_dependent_libs[self.ir_arch.arch.name])
             libs_to_load.append(jit_lib)
         except KeyError:
             pass
@@ -54,10 +55,10 @@ class JitCore_LLVM(jitcore.JitCore):
         self.context.optimise_level()
 
         # Save the current architecture parameters
-        self.arch = arch
+        self.arch = self.ir_arch.arch
 
         # Get the correspondance between registers and vmcpu struct
-        mod_name = "miasm2.jitter.arch.JitCore_%s" % (arch.name)
+        mod_name = "miasm2.jitter.arch.JitCore_%s" % (self.ir_arch.arch.name)
         mod = importlib.import_module(mod_name)
         self.context.set_vmcpu(mod.get_gpreg_offset_all())
 
@@ -65,7 +66,7 @@ class JitCore_LLVM(jitcore.JitCore):
         self.mod_base_str = str(self.context.mod)
 
         # Set IRs transformation to apply
-        self.context.set_IR_transformation(self.my_ir.expr_fix_regs_for_mode)
+        self.context.set_IR_transformation(self.ir_arch.expr_fix_regs_for_mode)
 
     def add_bloc(self, bloc):
 
diff --git a/miasm2/jitter/jitcore_python.py b/miasm2/jitter/jitcore_python.py
index 90c8bace..c2fb4be1 100644
--- a/miasm2/jitter/jitcore_python.py
+++ b/miasm2/jitter/jitcore_python.py
@@ -49,18 +49,19 @@ def update_engine_from_cpu(cpu, exec_engine):
 class JitCore_Python(jitcore.JitCore):
     "JiT management, using Miasm2 Symbol Execution engine as backend"
 
-    def __init__(self, my_ir, bs=None):
-        super(JitCore_Python, self).__init__(my_ir, bs)
+    def __init__(self, ir_arch, bs=None):
+        super(JitCore_Python, self).__init__(ir_arch, bs)
         self.symbexec = None
+        self.ir_arch = ir_arch
 
-    def load(self, arch):
+    def load(self):
         "Preload symbols according to current architecture"
 
         symbols_init =  {}
-        for i, r in enumerate(arch.regs.all_regs_ids_no_alias):
-            symbols_init[r] = arch.regs.all_regs_ids_init[i]
+        for i, r in enumerate(self.ir_arch.arch.regs.all_regs_ids_no_alias):
+            symbols_init[r] = self.ir_arch.arch.regs.all_regs_ids_init[i]
 
-        self.symbexec = symbexec(arch, symbols_init,
+        self.symbexec = symbexec(self.ir_arch, symbols_init,
                                  func_read = self.func_read,
                                  func_write = self.func_write)
 
@@ -157,7 +158,7 @@ class JitCore_Python(jitcore.JitCore):
                         return line.offset
 
                 # Get next bloc address
-                ad = expr_simp(exec_engine.eval_expr(irb.dst))
+                ad = expr_simp(exec_engine.eval_expr(self.ir_arch.IRDst))
 
                 # Updates @cpu instance according to new CPU values
                 update_cpu_from_engine(cpu, exec_engine)
diff --git a/miasm2/jitter/jitcore_tcc.py b/miasm2/jitter/jitcore_tcc.py
index cb92361f..ce1397a8 100644
--- a/miasm2/jitter/jitcore_tcc.py
+++ b/miasm2/jitter/jitcore_tcc.py
@@ -30,6 +30,7 @@ def gen_core(arch, attrib):
     txt = ""
     txt += '#include "%s/queue.h"\n' % lib_dir
     txt += '#include "%s/vm_mngr.h"\n' % lib_dir
+    txt += '#include "%s/arch/JitCore.h"\n' % lib_dir
     txt += '#include "%s/arch/JitCore_%s.h"\n' % (lib_dir, arch.name)
 
     txt += r'''
@@ -38,11 +39,11 @@ def gen_core(arch, attrib):
     return txt
 
 
-def gen_C_source(my_ir, func_code):
+def gen_C_source(ir_arch, func_code):
     c_source = ""
     c_source += "\n".join(func_code)
 
-    c_source = gen_core(my_ir.arch, my_ir.attrib) + c_source
+    c_source = gen_core(ir_arch.arch, ir_arch.attrib) + c_source
 
     c_source = """
  #ifdef __x86_64__
@@ -90,17 +91,18 @@ class JitCore_Tcc(jitcore.JitCore):
 
     "JiT management, using LibTCC as backend"
 
-    def __init__(self, my_ir, bs=None):
-        super(JitCore_Tcc, self).__init__(my_ir, bs)
+    def __init__(self, ir_arch, bs=None):
+        super(JitCore_Tcc, self).__init__(ir_arch, bs)
         self.resolver = resolver()
         self.exec_wrapper = Jittcc.tcc_exec_bloc
         self.tcc_states =[]
+        self.ir_arch = ir_arch
 
-    def load(self, arch):
+    def load(self):
         # os.path.join(os.path.dirname(os.path.realpath(__file__)), "jitter")
         lib_dir = os.path.dirname(os.path.realpath(__file__))
         libs = []
-        libs.append(os.path.join(lib_dir, 'arch/JitCore_%s.so' % (arch.name)))
+        libs.append(os.path.join(lib_dir, 'arch/JitCore_%s.so' % (self.ir_arch.arch.name)))
         libs = ';'.join(libs)
         jittcc_path = Jittcc.__file__
         include_dir = os.path.dirname(jittcc_path)
@@ -127,20 +129,18 @@ class JitCore_Tcc(jitcore.JitCore):
             Jittcc.tcc_end(tcc_state)
 
     def jitirblocs(self, label, irblocs):
-        # irbloc = self.lbl2irbloc[lbl]
         f_name = "bloc_%s" % label.name
-        f_declaration = \
-            'PyObject* %s(vm_cpu_t* vmcpu, vm_mngr_t* vm_mngr)' % f_name
-        out = irblocs2C(self.my_ir, self.resolver, label, irblocs,
+        f_declaration = 'block_id %s(vm_cpu_t* vmcpu, vm_mngr_t* vm_mngr)' % f_name
+        out = irblocs2C(self.ir_arch, self.resolver, label, irblocs,
                         gen_exception_code=True,
                         log_mn=self.log_mn,
                         log_regs=self.log_regs)
         out = [f_declaration + '{'] + out + ['}\n']
         c_code = out
 
-        func_code = gen_C_source(self.my_ir, c_code)
-        # print func_code
-        # open('tmp_%.4d.c'%self.jitcount, "w").write(func_code)
+        func_code = gen_C_source(self.ir_arch, c_code)
+
+        open('tmp_%.4d.c'%self.jitcount, "w").write(func_code)
         self.jitcount += 1
         tcc_state, mcode = jit_tcc_compil(f_name, func_code)
         self.tcc_states.append(tcc_state)
@@ -148,4 +148,3 @@ class JitCore_Tcc(jitcore.JitCore):
         self.lbl2jitbloc[label.offset] = mcode
         self.addr2obj[label.offset] = jcode
         self.addr2objref[label.offset] = objref(jcode)
-        # print "ADDR2CODE", hex(b.label.offset), hex(id(jcode))
diff --git a/miasm2/jitter/jitload.py b/miasm2/jitter/jitload.py
index dc1a2a94..285c41dd 100644
--- a/miasm2/jitter/jitload.py
+++ b/miasm2/jitter/jitload.py
@@ -560,18 +560,18 @@ class jitter:
 
     "Main class for JIT handling"
 
-    def __init__(self, my_ir, jit_type="tcc"):
+    def __init__(self, ir_arch, jit_type="tcc"):
         """Init an instance of jitter.
-        @my_ir: ir instance for this architecture
+        @ir_arch: ir instance for this architecture
         @jit_type: JiT backend to use. Available options are:
             - "tcc"
             - "llvm"
             - "python"
         """
 
-        self.arch = my_ir.arch
-        self.attrib = my_ir.attrib
-        arch_name = my_ir.arch.name  # (my_ir.arch.name, my_ir.attrib)
+        self.arch = ir_arch.arch
+        self.attrib = ir_arch.attrib
+        arch_name = ir_arch.arch.name  # (ir_arch.arch.name, ir_arch.attrib)
         if arch_name == "x86":
             from arch import JitCore_x86 as jcore
         elif arch_name == "arm":
@@ -586,15 +586,15 @@ class jitter:
         self.cpu = jcore.JitCpu()
         self.vm = jcore.VmMngr()
         self.bs = bin_stream_vm(self.vm)
-        self.my_ir = my_ir
+        self.ir_arch = ir_arch
         init_arch_C(self.arch)
 
         if jit_type == "tcc":
-            self.jit = JitCore_Tcc(self.my_ir, self.bs)
+            self.jit = JitCore_Tcc(self.ir_arch, self.bs)
         elif jit_type == "llvm":
-            self.jit = JitCore_LLVM(self.my_ir, self.bs)
+            self.jit = JitCore_LLVM(self.ir_arch, self.bs)
         elif jit_type == "python":
-            self.jit = JitCore_Python(self.my_ir, self.bs)
+            self.jit = JitCore_Python(self.ir_arch, self.bs)
         else:
             raise Exception("Unkown JiT Backend")
 
@@ -605,7 +605,7 @@ class jitter:
 
         self.vm.vm_set_addr2obj(self.jit.addr2obj)
 
-        self.jit.load(self.arch)
+        self.jit.load()
         self.stack_size = 0x10000
         self.stack_base = 0x1230000
 
diff --git a/miasm2/jitter/vm_mngr.h b/miasm2/jitter/vm_mngr.h
index 0cacb708..2bf23f37 100644
--- a/miasm2/jitter/vm_mngr.h
+++ b/miasm2/jitter/vm_mngr.h
@@ -124,6 +124,7 @@ struct memory_breakpoint_info {
 };
 
 
+
 #define PAGE_READ 1
 #define PAGE_WRITE 2
 #define PAGE_EXEC 4