diff options
Diffstat (limited to 'miasm2/jitter')
| -rw-r--r-- | miasm2/jitter/arch/JitCore_aarch64.c | 10 | ||||
| -rw-r--r-- | miasm2/jitter/arch/JitCore_aarch64.h | 1 | ||||
| -rw-r--r-- | miasm2/jitter/arch/JitCore_x86.c | 23 | ||||
| -rw-r--r-- | miasm2/jitter/codegen.py | 4 | ||||
| -rw-r--r-- | miasm2/jitter/jitcore.py | 4 | ||||
| -rw-r--r-- | miasm2/jitter/jitcore_python.py | 2 | ||||
| -rw-r--r-- | miasm2/jitter/jitload.py | 2 | ||||
| -rw-r--r-- | miasm2/jitter/llvmconvert.py | 22 |
8 files changed, 51 insertions, 17 deletions
diff --git a/miasm2/jitter/arch/JitCore_aarch64.c b/miasm2/jitter/arch/JitCore_aarch64.c index 03113d30..e10d847e 100644 --- a/miasm2/jitter/arch/JitCore_aarch64.c +++ b/miasm2/jitter/arch/JitCore_aarch64.c @@ -50,6 +50,10 @@ reg_dict gpreg_dict[] = { {.name = "nf", .offset = offsetof(vm_cpu_t, nf)}, {.name = "of", .offset = offsetof(vm_cpu_t, of)}, {.name = "cf", .offset = offsetof(vm_cpu_t, cf)}, + + {.name = "exception_flags", .offset = offsetof(vm_cpu_t, exception_flags)}, + {.name = "interrupt_num", .offset = offsetof(vm_cpu_t, interrupt_num)}, + }; /************************** JitCpu object **************************/ @@ -375,6 +379,9 @@ getset_reg_u32(of); getset_reg_u32(cf); +getset_reg_u32(exception_flags); +getset_reg_u32(interrupt_num); + PyObject* get_gpreg_offset_all(void) { @@ -485,6 +492,9 @@ static PyGetSetDef JitCpu_getseters[] = { {"of", (getter)JitCpu_get_of, (setter)JitCpu_set_of, "of", NULL}, {"cf", (getter)JitCpu_get_cf, (setter)JitCpu_set_cf, "cf", NULL}, + {"exception_flags", (getter)JitCpu_get_exception_flags, (setter)JitCpu_set_exception_flags, "exception_flags", NULL}, + {"interrupt_num", (getter)JitCpu_get_interrupt_num, (setter)JitCpu_set_interrupt_num, "interrupt_num", NULL}, + {NULL} /* Sentinel */ }; diff --git a/miasm2/jitter/arch/JitCore_aarch64.h b/miasm2/jitter/arch/JitCore_aarch64.h index 4635b395..c7fc3cea 100644 --- a/miasm2/jitter/arch/JitCore_aarch64.h +++ b/miasm2/jitter/arch/JitCore_aarch64.h @@ -1,6 +1,7 @@ typedef struct { uint32_t exception_flags; + uint32_t interrupt_num; /* gpregs */ diff --git a/miasm2/jitter/arch/JitCore_x86.c b/miasm2/jitter/arch/JitCore_x86.c index 3198eff3..407a01c7 100644 --- a/miasm2/jitter/arch/JitCore_x86.c +++ b/miasm2/jitter/arch/JitCore_x86.c @@ -178,6 +178,29 @@ PyObject * cpu_init_regs(JitCpu* self) } +void dump_gpregs_16(vm_cpu_t* vmcpu) +{ + + printf("EAX %.8"PRIX32" EBX %.8"PRIX32" ECX %.8"PRIX32" EDX %.8"PRIX32" ", + (uint32_t)(vmcpu->RAX & 0xFFFFFFFF), + (uint32_t)(vmcpu->RBX & 0xFFFFFFFF), + (uint32_t)(vmcpu->RCX & 0xFFFFFFFF), + (uint32_t)(vmcpu->RDX & 0xFFFFFFFF)); + printf("ESI %.8"PRIX32" EDI %.8"PRIX32" ESP %.8"PRIX32" EBP %.8"PRIX32" ", + (uint32_t)(vmcpu->RSI & 0xFFFFFFFF), + (uint32_t)(vmcpu->RDI & 0xFFFFFFFF), + (uint32_t)(vmcpu->RSP & 0xFFFFFFFF), + (uint32_t)(vmcpu->RBP & 0xFFFFFFFF)); + printf("EIP %.8"PRIX32" ", + (uint32_t)(vmcpu->RIP & 0xFFFFFFFF)); + printf("zf %.1"PRIX32" nf %.1"PRIX32" of %.1"PRIX32" cf %.1"PRIX32"\n", + (uint32_t)(vmcpu->zf & 0x1), + (uint32_t)(vmcpu->nf & 0x1), + (uint32_t)(vmcpu->of & 0x1), + (uint32_t)(vmcpu->cf & 0x1)); + +} + void dump_gpregs_32(vm_cpu_t* vmcpu) { diff --git a/miasm2/jitter/codegen.py b/miasm2/jitter/codegen.py index 61a9a784..9ed55f37 100644 --- a/miasm2/jitter/codegen.py +++ b/miasm2/jitter/codegen.py @@ -489,7 +489,7 @@ class CGen(object): for irblock in irblocks: attributes = [] irblocks_attributes.append(attributes) - for assignblk in irblock.irs: + for assignblk in irblock: attrib = Attributes(log_mn, log_regs) attributes.append(attrib) self.get_caracteristics(assignblk, attrib) @@ -534,7 +534,7 @@ class CGen(object): out = [] dst2index = None - for index, assignblk in enumerate(irblock.irs): + for index, assignblk in enumerate(irblock): if index == irblock.dst_linenb: c_dst, dst2index = self.gen_assignblk_dst(irblock.dst) else: diff --git a/miasm2/jitter/jitcore.py b/miasm2/jitter/jitcore.py index 9c35f829..f2b1375d 100644 --- a/miasm2/jitter/jitcore.py +++ b/miasm2/jitter/jitcore.py @@ -63,7 +63,7 @@ class JitCore(object): follow_call=False, dontdis_retcall=False, split_dis=self.split_dis, - dis_bloc_callback=self.disasm_cb) + dis_block_callback=self.disasm_cb) def set_options(self, **kwargs): @@ -140,7 +140,7 @@ class JitCore(object): # Prepare disassembler self.mdis.lines_wd = self.options["jit_maxline"] - self.mdis.dis_bloc_callback = self.disasm_cb + self.mdis.dis_block_callback = self.disasm_cb # Disassemble it try: diff --git a/miasm2/jitter/jitcore_python.py b/miasm2/jitter/jitcore_python.py index 6d954aae..a74ef7e6 100644 --- a/miasm2/jitter/jitcore_python.py +++ b/miasm2/jitter/jitcore_python.py @@ -72,7 +72,7 @@ class JitCore_Python(jitcore.JitCore): exec_engine.update_engine_from_cpu() # Execute current ir bloc - for assignblk in irb.irs: + for assignblk in irb: instr = assignblk.instr # For each new instruction (in assembly) if instr.offset not in offsets_jitted: diff --git a/miasm2/jitter/jitload.py b/miasm2/jitter/jitload.py index 4760c8dd..ff7ba215 100644 --- a/miasm2/jitter/jitload.py +++ b/miasm2/jitter/jitload.py @@ -448,7 +448,7 @@ class jitter: return ret def handle_function(self, f_addr): - """Add a brakpoint which will trigger the function handler""" + """Add a breakpoint which will trigger the function handler""" self.add_breakpoint(f_addr, self.handle_lib) def add_lib_handler(self, libs, user_globals=None): diff --git a/miasm2/jitter/llvmconvert.py b/miasm2/jitter/llvmconvert.py index 83349781..65c6aa07 100644 --- a/miasm2/jitter/llvmconvert.py +++ b/miasm2/jitter/llvmconvert.py @@ -966,7 +966,7 @@ class LLVMFunction(): if isinstance(offset, (int, long)): offset = self.add_ir(m2_expr.ExprInt(offset, PC.size)) self.affect(offset, PC) - self.affect(self.add_ir(m2_expr.ExprInt(1, 8)), m2_expr.ExprId("status")) + self.affect(self.add_ir(m2_expr.ExprInt(1, 8)), m2_expr.ExprId("status", 32)) self.set_ret(offset) builder.position_at_end(merge_block) @@ -1013,7 +1013,7 @@ class LLVMFunction(): if isinstance(offset, (int, long)): offset = self.add_ir(m2_expr.ExprInt(offset, PC.size)) self.affect(offset, PC) - self.affect(self.add_ir(m2_expr.ExprInt(1, 8)), m2_expr.ExprId("status")) + self.affect(self.add_ir(m2_expr.ExprInt(1, 8)), m2_expr.ExprId("status", 32)) self.set_ret(offset) builder.position_at_end(merge_block) @@ -1121,7 +1121,7 @@ class LLVMFunction(): self.gen_post_code(attrib) self.affect(dst, PC) self.gen_post_instr_checks(attrib, dst) - self.affect(self.add_ir(m2_expr.ExprInt(0, 8)), m2_expr.ExprId("status")) + self.affect(self.add_ir(m2_expr.ExprInt(0, 8)), m2_expr.ExprId("status", 32)) self.set_ret(dst) @@ -1138,7 +1138,7 @@ class LLVMFunction(): case_value = None instr = instr_attrib.instr - for index, assignblk in enumerate(irblock.irs): + for index, assignblk in enumerate(irblock): # Enable cache self.main_stream = True self.expr_cache = {} @@ -1215,7 +1215,7 @@ class LLVMFunction(): m2_exception_flag = self.llvm_context.ir_arch.arch.regs.exception_flags t_size = LLVMType.IntType(m2_exception_flag.size) self.affect(self.add_ir(m2_expr.ExprInt(1, 8)), - m2_expr.ExprId("status")) + m2_expr.ExprId("status", 32)) self.affect(t_size(m2_csts.EXCEPT_UNK_MNEMO), m2_exception_flag) self.set_ret(LLVMType.IntType(64)(asmblock.label.offset)) @@ -1233,7 +1233,7 @@ class LLVMFunction(): # Common code self.affect(self.add_ir(m2_expr.ExprInt(0, 8)), - m2_expr.ExprId("status")) + m2_expr.ExprId("status", 32)) # Check if IRDst has been set zero_casted = LLVMType.IntType(codegen.delay_slot_set.size)(0) @@ -1257,7 +1257,7 @@ class LLVMFunction(): to_ret = self.add_ir(codegen.delay_slot_dst) self.affect(to_ret, PC) self.affect(self.add_ir(m2_expr.ExprInt(0, 8)), - m2_expr.ExprId("status")) + m2_expr.ExprId("status", 32)) self.set_ret(to_ret) # Else Block @@ -1272,16 +1272,16 @@ class LLVMFunction(): Prototype : f(i8* jitcpu, i8* vmcpu, i8* vmmngr, i8* status)""" # Build function signature - self.my_args.append((m2_expr.ExprId("jitcpu"), + self.my_args.append((m2_expr.ExprId("jitcpu", 32), llvm_ir.PointerType(LLVMType.IntType(8)), "jitcpu")) - self.my_args.append((m2_expr.ExprId("vmcpu"), + self.my_args.append((m2_expr.ExprId("vmcpu", 32), llvm_ir.PointerType(LLVMType.IntType(8)), "vmcpu")) - self.my_args.append((m2_expr.ExprId("vmmngr"), + self.my_args.append((m2_expr.ExprId("vmmngr", 32), llvm_ir.PointerType(LLVMType.IntType(8)), "vmmngr")) - self.my_args.append((m2_expr.ExprId("status"), + self.my_args.append((m2_expr.ExprId("status", 32), llvm_ir.PointerType(LLVMType.IntType(8)), "status")) ret_size = 64 |