diff options
Diffstat (limited to 'miasm2/jitter')
| -rw-r--r-- | miasm2/jitter/arch/JitCore_arm.c | 35 | ||||
| -rw-r--r-- | miasm2/jitter/arch/JitCore_arm.h | 13 | ||||
| -rw-r--r-- | miasm2/jitter/codegen.py | 2 | ||||
| -rw-r--r-- | miasm2/jitter/jitload.py | 3 | ||||
| -rw-r--r-- | miasm2/jitter/llvmconvert.py | 4 |
5 files changed, 56 insertions, 1 deletions
diff --git a/miasm2/jitter/arch/JitCore_arm.c b/miasm2/jitter/arch/JitCore_arm.c index 6b167da5..cce0997d 100644 --- a/miasm2/jitter/arch/JitCore_arm.c +++ b/miasm2/jitter/arch/JitCore_arm.c @@ -31,6 +31,11 @@ reg_dict gpreg_dict[] = { {.name = "R0", .offset = offsetof(vm_cpu_t, R0)}, {.name = "nf", .offset = offsetof(vm_cpu_t, nf)}, {.name = "of", .offset = offsetof(vm_cpu_t, of)}, {.name = "cf", .offset = offsetof(vm_cpu_t, cf)}, + + {.name = "ge0", .offset = offsetof(vm_cpu_t, ge0)}, + {.name = "ge1", .offset = offsetof(vm_cpu_t, ge1)}, + {.name = "ge2", .offset = offsetof(vm_cpu_t, ge2)}, + {.name = "ge3", .offset = offsetof(vm_cpu_t, ge3)}, }; /************************** JitCpu object **************************/ @@ -65,6 +70,11 @@ PyObject* cpu_get_gpreg(JitCpu* self) get_reg(of); get_reg(cf); + get_reg(ge0); + get_reg(ge1); + get_reg(ge2); + get_reg(ge3); + return dict; } @@ -176,6 +186,16 @@ void check_automod(JitCpu* jitcpu, uint64_t addr, uint64_t size) } + +UDIV(32) + +UMOD(32) + +IDIV(32) + +IMOD(32) + + void MEM_WRITE_08(JitCpu* jitcpu, uint64_t addr, uint8_t src) { vm_MEM_WRITE_08(&((VmMngr*)jitcpu->pyvm)->vm_mngr, addr, src); @@ -304,6 +324,11 @@ getset_reg_u32(nf); getset_reg_u32(of); getset_reg_u32(cf); +getset_reg_u32(ge0); +getset_reg_u32(ge1); +getset_reg_u32(ge2); +getset_reg_u32(ge3); + PyObject* get_gpreg_offset_all(void) { @@ -335,6 +360,11 @@ PyObject* get_gpreg_offset_all(void) get_reg_off(of); get_reg_off(cf); + get_reg_off(ge0); + get_reg_off(ge1); + get_reg_off(ge2); + get_reg_off(ge3); + return dict; } @@ -374,6 +404,11 @@ static PyGetSetDef JitCpu_getseters[] = { {"of", (getter)JitCpu_get_of, (setter)JitCpu_set_of, "of", NULL}, {"cf", (getter)JitCpu_get_cf, (setter)JitCpu_set_cf, "cf", NULL}, + {"ge0", (getter)JitCpu_get_ge0, (setter)JitCpu_set_ge0, "ge0", NULL}, + {"ge1", (getter)JitCpu_get_ge1, (setter)JitCpu_set_ge0, "ge1", NULL}, + {"ge2", (getter)JitCpu_get_ge2, (setter)JitCpu_set_ge0, "ge2", NULL}, + {"ge3", (getter)JitCpu_get_ge3, (setter)JitCpu_set_ge0, "ge3", NULL}, + {NULL} /* Sentinel */ }; diff --git a/miasm2/jitter/arch/JitCore_arm.h b/miasm2/jitter/arch/JitCore_arm.h index 66d17604..445ac44a 100644 --- a/miasm2/jitter/arch/JitCore_arm.h +++ b/miasm2/jitter/arch/JitCore_arm.h @@ -26,12 +26,25 @@ typedef struct { uint32_t of; uint32_t cf; + /* ge */ + uint32_t ge0; + uint32_t ge1; + uint32_t ge2; + uint32_t ge3; + uint32_t bp_num; }vm_cpu_t; void dump_gpregs(vm_cpu_t* vmcpu); + +uint32_t udiv32(vm_cpu_t* vmcpu, uint32_t a, uint32_t b); +uint32_t umod32(vm_cpu_t* vmcpu, uint32_t a, uint32_t b); +int32_t idiv32(vm_cpu_t* vmcpu, int32_t a, int32_t b); +int32_t imod32(vm_cpu_t* vmcpu, int32_t a, int32_t b); + + #define RETURN_PC return BlockDst; uint32_t clz(uint32_t arg); diff --git a/miasm2/jitter/codegen.py b/miasm2/jitter/codegen.py index 9ed55f37..2c546be8 100644 --- a/miasm2/jitter/codegen.py +++ b/miasm2/jitter/codegen.py @@ -572,7 +572,7 @@ class CGen(object): irblocks_list = self.block2assignblks(block) out, instr_offsets = self.gen_init(block) - + assert len(block.lines) == len(irblocks_list) for instr, irblocks in zip(block.lines, irblocks_list): instr_attrib, irblocks_attributes = self.get_attributes(instr, irblocks, log_mn, log_regs) diff --git a/miasm2/jitter/jitload.py b/miasm2/jitter/jitload.py index 499d6c47..8eb7659e 100644 --- a/miasm2/jitter/jitload.py +++ b/miasm2/jitter/jitload.py @@ -182,6 +182,9 @@ class jitter(object): from miasm2.jitter.arch import JitCore_x86 as jcore elif arch_name == "arm": from miasm2.jitter.arch import JitCore_arm as jcore + elif arch_name == "armt": + from miasm2.jitter.arch import JitCore_arm as jcore + ir_arch.arch.name = 'arm' elif arch_name == "aarch64": from miasm2.jitter.arch import JitCore_aarch64 as jcore elif arch_name == "msp430": diff --git a/miasm2/jitter/llvmconvert.py b/miasm2/jitter/llvmconvert.py index 0e4368a8..35db1538 100644 --- a/miasm2/jitter/llvmconvert.py +++ b/miasm2/jitter/llvmconvert.py @@ -180,6 +180,10 @@ class LLVMContext_JIT(LLVMContext): from miasm2.arch.mips32.jit import mipsCGen self.cgen_class = mipsCGen self.has_delayslot = True + elif arch.name == "arm": + from miasm2.arch.arm.jit import arm_CGen + self.cgen_class = arm_CGen + self.has_delayslot = False else: self.cgen_class = CGen self.has_delayslot = False |