diff options
Diffstat (limited to 'miasm2')
| -rw-r--r-- | miasm2/arch/arm/arch.py | 26 | ||||
| -rw-r--r-- | miasm2/arch/arm/sem.py | 12 | ||||
| -rw-r--r-- | miasm2/arch/mips32/arch.py | 6 | ||||
| -rw-r--r-- | miasm2/arch/sh4/arch.py | 12 | ||||
| -rw-r--r-- | miasm2/arch/x86/sem.py | 6 | ||||
| -rw-r--r-- | miasm2/expression/expression.py | 9 |
6 files changed, 37 insertions, 34 deletions
diff --git a/miasm2/arch/arm/arch.py b/miasm2/arch/arm/arch.py index 5e4b02f9..39b4cb14 100644 --- a/miasm2/arch/arm/arch.py +++ b/miasm2/arch/arm/arch.py @@ -224,9 +224,9 @@ def deref2expr_pre(s, l, t): def deref2expr_pre_mem(s, l, t): t = t[0] if len(t) == 1: - return ExprMem(ExprOp("preinc", t[0], ExprInt(0, 32))) + return ExprMem(ExprOp("preinc", t[0], ExprInt(0, 32)), 32) elif len(t) == 2: - return ExprMem(ExprOp("preinc", t[0], t[1])) + return ExprMem(ExprOp("preinc", t[0], t[1]), 32) else: raise NotImplementedError('len(t) > 2') @@ -239,8 +239,8 @@ def deref2expr_post(s, l, t): def deref_wb(s, l, t): t = t[0] if t[-1] == '!': - return ExprMem(ExprOp('wback', *t[:-1])) - return ExprMem(t[0]) + return ExprMem(ExprOp('wback', *t[:-1]), 32) + return ExprMem(t[0], 32) # shift_off.setParseAction(deref_off) deref_nooff = Group( @@ -855,7 +855,7 @@ class arm_imm8_12(m_arg): e = ExprOp('postinc', self.parent.rn.expr, e) if self.parent.wback.value == 1: e = ExprOp('wback', e) - self.expr = ExprMem(e) + self.expr = ExprMem(e, 32) return True def encode(self): @@ -1056,7 +1056,7 @@ class arm_op2imm(arm_imm8_12): e = ExprOp('postinc', self.parent.rn.expr, ExprInt(imm, 32)) if self.parent.wback.value == 1: e = ExprOp('wback', e) - self.expr = ExprMem(e) + self.expr = ExprMem(e, 32) return True rm = val & 0xf shift = val >> 4 @@ -1083,7 +1083,7 @@ class arm_op2imm(arm_imm8_12): e = ExprOp('postinc', self.parent.rn.expr, a) if self.parent.wback.value == 1: e = ExprOp('wback', e) - self.expr = ExprMem(e) + self.expr = ExprMem(e, 32) return True def encode(self): @@ -1372,7 +1372,7 @@ class arm_immed(m_arg): e = ExprOp('postinc', self.parent.rn.expr, imm) if self.parent.wback.value == 1: e = ExprOp('wback', e) - self.expr = ExprMem(e) + self.expr = ExprMem(e, 32) return True @@ -1459,9 +1459,9 @@ class arm_mem_rn_imm(m_arg): imm = ExprInt(value, 32) reg = gpregs.expr[v] if value: - expr = ExprMem(reg + imm) + expr = ExprMem(reg + imm, 32) else: - expr = ExprMem(reg) + expr = ExprMem(reg, 32) self.expr = expr return True @@ -1748,9 +1748,9 @@ class arm_offpc(arm_offreg): v = v & self.lmask v <<= 2 if v: - self.expr = ExprMem(self.off_reg + ExprInt(v, 32)) + self.expr = ExprMem(self.off_reg + ExprInt(v, 32), 32) else: - self.expr = ExprMem(self.off_reg) + self.expr = ExprMem(self.off_reg, 32) e = self.expr.arg if isinstance(e, ExprOp) and e.op == 'wback': @@ -1823,7 +1823,7 @@ class arm_deref(m_arg): v = v & self.lmask rbase = regs_expr[v] e = ExprOp('preinc', rbase, self.parent.off.expr) - self.expr = ExprMem(e) + self.expr = ExprMem(e, 32) return True def encode(self): diff --git a/miasm2/arch/arm/sem.py b/miasm2/arch/arm/sem.py index 29b25538..c2afeef5 100644 --- a/miasm2/arch/arm/sem.py +++ b/miasm2/arch/arm/sem.py @@ -672,11 +672,11 @@ def st_ld_m(ir, instr, a, b, store=False, postinc=False, updown=False): for i, r in enumerate(regs): ad = base + ExprInt(i * step, 32) if store: - e.append(ExprAff(ExprMem(ad), r)) + e.append(ExprAff(ExprMem(ad, 32), r)) else: - e.append(ExprAff(r, ExprMem(ad))) + e.append(ExprAff(r, ExprMem(ad, 32))) if r == PC: - e.append(ExprAff(ir.IRDst, ExprMem(ad))) + e.append(ExprAff(ir.IRDst, ExprMem(ad, 32))) # XXX TODO check multiple write cause by wb if wb: if postinc: @@ -813,7 +813,7 @@ def push(ir, instr, a): regs = list(a.args) for i in xrange(len(regs)): r = SP + ExprInt(-4 * (i + 1), 32) - e.append(ExprAff(ExprMem(r), regs[i])) + e.append(ExprAff(ExprMem(r, 32), regs[i])) r = SP + ExprInt(-4 * len(regs), 32) e.append(ExprAff(SP, r)) return e @@ -825,9 +825,9 @@ def pop(ir, instr, a): dst = None for i in xrange(len(regs)): r = SP + ExprInt(4 * i, 32) - e.append(ExprAff(regs[i], ExprMem(r))) + e.append(ExprAff(regs[i], ExprMem(r, 32))) if regs[i] == ir.pc: - dst = ExprMem(r) + dst = ExprMem(r, 32) r = SP + ExprInt(4 * len(regs), 32) e.append(ExprAff(SP, r)) if dst is not None: diff --git a/miasm2/arch/mips32/arch.py b/miasm2/arch/mips32/arch.py index d64e27df..3abdc053 100644 --- a/miasm2/arch/mips32/arch.py +++ b/miasm2/arch/mips32/arch.py @@ -29,13 +29,13 @@ def deref2expr(s, l, t): if len(t) != 4: raise NotImplementedError("TODO") - return ExprMem(t[2] + t[0]) + return ExprMem(t[2] + t[0], 32) def deref2expr_nooff(s, l, t): t = t[0] if len(t) != 3: raise NotImplementedError("TODO") - return ExprMem(t[1]) + return ExprMem(t[1], 32) base_expr = cpu.base_expr @@ -380,7 +380,7 @@ class mips32_dreg_imm(cpu.m_arg): def decode(self, v): imm = self.parent.imm.expr r = gpregs.expr[v] - self.expr = ExprMem(r+imm) + self.expr = ExprMem(r+imm, 32) return True def encode(self): diff --git a/miasm2/arch/sh4/arch.py b/miasm2/arch/sh4/arch.py index d7ae4f12..ecfc9502 100644 --- a/miasm2/arch/sh4/arch.py +++ b/miasm2/arch/sh4/arch.py @@ -67,25 +67,25 @@ def parse_deref_mem(s, l, t): def parse_predec(s, l, t): t = t[0] - e = ExprMem(ExprOp('predec', t[0])) + e = ExprMem(ExprOp('predec', t[0]), 32) return e def parse_postinc(s, l, t): t = t[0] - e = ExprMem(ExprOp('postinc', t[0])) + e = ExprMem(ExprOp('postinc', t[0]), 32) return e def parse_regdisp(t): t = t[0] - e = ExprMem(t[0] + t[1]) + e = ExprMem(t[0] + t[1], 32) return e def parse_regreg(t): t = t[0] - e = ExprMem(t[0] + t[1]) + e = ExprMem(t[0] + t[1], 32) return e @@ -314,7 +314,7 @@ class sh4_dgbrimm8(sh4_dgpreg): def encode(self): e = self.expr s = self.sz - if e == ExprMem(GBR): + if e == ExprMem(GBR, 32): self.value = 0 return True res = match_expr(self.expr, ExprMem(GBR + jra, s), [jra]) @@ -331,7 +331,7 @@ class sh4_dpc32imm(sh4_dpc16imm): def decode(self, v): self.expr = ExprMem( - (PC & ExprInt(0xfffffffc, 32)) + ExprInt(v * 4 + 4, 32)) + (PC & ExprInt(0xfffffffc, 32)) + ExprInt(v * 4 + 4, 32), 32) return True def calcdisp(self, v): diff --git a/miasm2/arch/x86/sem.py b/miasm2/arch/x86/sem.py index 9f438b71..d81cbe5e 100644 --- a/miasm2/arch/x86/sem.py +++ b/miasm2/arch/x86/sem.py @@ -1078,7 +1078,7 @@ def pushfw(ir, instr): def popfd(ir, instr): - tmp = ir.ExprMem(mRSP[instr.mode]) + tmp = ir.ExprMem(mRSP[instr.mode], 32) e = [] e.append(m2_expr.ExprAff(cf, m2_expr.ExprSlice(tmp, 0, 1))) e.append(m2_expr.ExprAff(pf, m2_expr.ExprSlice(tmp, 2, 3))) @@ -1121,7 +1121,7 @@ def _tpl_eflags(tmp): def popfw(ir, instr): - tmp = ir.ExprMem(mRSP[instr.mode]) + tmp = ir.ExprMem(mRSP[instr.mode], 32) e = _tpl_eflags(tmp) e.append( m2_expr.ExprAff(mRSP[instr.mode], mRSP[instr.mode] + m2_expr.ExprInt(2, mRSP[instr.mode].size))) @@ -5046,7 +5046,7 @@ class ir_x86_16(IntermediateRepresentation): def mod_pc(self, instr, instr_ir, extra_ir): pass - def ExprMem(self, ptr, size=32): + def ExprMem(self, ptr, size): """Generate a memory access to @ptr The ptr is resized to a fixed size self.addrsize diff --git a/miasm2/expression/expression.py b/miasm2/expression/expression.py index a72c1ec4..f0491f1a 100644 --- a/miasm2/expression/expression.py +++ b/miasm2/expression/expression.py @@ -542,7 +542,7 @@ class ExprId(Expr): state = self._name, self._size return self.__class__, state - def __new__(cls, name, size=32): + def __new__(cls, name, size=None): return Expr.get_object(cls, (name, size)) def __str__(self): @@ -787,11 +787,14 @@ class ExprMem(Expr): __slots__ = Expr.__slots__ + ["_arg"] - def __init__(self, arg, size=32): + def __init__(self, arg, size=None): """Create an ExprMem @arg: Expr, memory access address @size: int, memory access size """ + if size is None: + warnings.warn('DEPRECATION WARNING: size is a mandatory argument: use ExprMem(arg, SIZE)') + size = 32 # arg must be Expr assert isinstance(arg, Expr) @@ -810,7 +813,7 @@ class ExprMem(Expr): state = self._arg, self._size return self.__class__, state - def __new__(cls, arg, size=32): + def __new__(cls, arg, size=None): return Expr.get_object(cls, (arg, size)) def __str__(self): |