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-rw-r--r--test/arch/mep/ir/launch.py22
-rw-r--r--test/arch/mep/ir/test_arithmetic.py185
-rw-r--r--test/arch/mep/ir/test_bitmanipulation.py55
-rw-r--r--test/arch/mep/ir/test_branchjump.py191
-rw-r--r--test/arch/mep/ir/test_control.py105
-rw-r--r--test/arch/mep/ir/test_coprocessor.py109
-rw-r--r--test/arch/mep/ir/test_datacache.py13
-rw-r--r--test/arch/mep/ir/test_debug.py33
-rw-r--r--test/arch/mep/ir/test_divide.py99
-rw-r--r--test/arch/mep/ir/test_extension.py57
-rw-r--r--test/arch/mep/ir/test_ir.py56
-rw-r--r--test/arch/mep/ir/test_ldz.py41
-rw-r--r--test/arch/mep/ir/test_loadstore.py209
-rw-r--r--test/arch/mep/ir/test_logical.py65
-rw-r--r--test/arch/mep/ir/test_move.py58
-rw-r--r--test/arch/mep/ir/test_multiply.py138
-rw-r--r--test/arch/mep/ir/test_repeat.py29
-rw-r--r--test/arch/mep/ir/test_shift.py108
-rw-r--r--test/arch/mep/ir/ut_helpers_ir.py87
19 files changed, 1660 insertions, 0 deletions
diff --git a/test/arch/mep/ir/launch.py b/test/arch/mep/ir/launch.py
new file mode 100644
index 00000000..44a8db52
--- /dev/null
+++ b/test/arch/mep/ir/launch.py
@@ -0,0 +1,22 @@
+# Toshiba MeP-c4 - pytest unit tests wrapper
+# Guillaume Valadon <guillaume@valadon.net>
+
+from ut_helpers_ir import launch_tests
+
+from test_arithmetic import TestArithmetic; launch_tests(TestArithmetic())
+from test_bitmanipulation import TestBitManipulation; launch_tests(TestBitManipulation())
+from test_branchjump import TestBranchJump; launch_tests(TestBranchJump())
+from test_control import TestControl; launch_tests(TestControl())
+from test_coprocessor import TestCoprocessor; launch_tests(TestCoprocessor())
+from test_datacache import TestDataCache; launch_tests(TestDataCache())
+from test_debug import TestDebug; launch_tests(TestDebug())
+from test_divide import TestDivide; launch_tests(TestDivide())
+from test_extension import TestExtension; launch_tests(TestExtension())
+from test_ldz import TestLdz; launch_tests(TestLdz())
+from test_loadstore import TestLoadStore; launch_tests(TestLoadStore())
+from test_logical import TestLogical; launch_tests(TestLogical())
+from test_move import TestMove; launch_tests(TestMove())
+from test_multiply import TestMultiply; launch_tests(TestMultiply())
+from test_repeat import TestRepeat; launch_tests(TestRepeat())
+from test_shift import TestShift; launch_tests(TestShift())
+from test_ir import TestMisc; launch_tests(TestMisc())
diff --git a/test/arch/mep/ir/test_arithmetic.py b/test/arch/mep/ir/test_arithmetic.py
new file mode 100644
index 00000000..6da938e9
--- /dev/null
+++ b/test/arch/mep/ir/test_arithmetic.py
@@ -0,0 +1,185 @@
+# Toshiba MeP-c4 - Arithmetic instructions unit tests
+# Guillaume Valadon <guillaume@valadon.net>
+
+from ut_helpers_ir import exec_instruction
+
+from miasm2.expression.expression import ExprId, ExprInt, ExprCond, ExprOp
+
+
+class TestArithmetic:
+
+    def test_add3(self):
+        """Test ADD3 execution"""
+
+        # ADD3 Rl,Rn,Rm
+        exec_instruction("ADD3 R1, R2, R3",
+                         [(ExprId("R2", 32), ExprInt(0x40, 32)), (ExprId("R3", 32), ExprInt(0x2, 32))],
+                         [(ExprId("R1", 32), ExprInt(0x42, 32))])
+
+        # ADD3 Rn,SP,imm7.align4
+        exec_instruction("ADD3 R1, SP, 0x8",
+                         [(ExprId("SP", 32), ExprInt(0x20, 32))],
+                         [(ExprId("R1", 32), ExprInt(0x28, 32))])
+
+        # ADD3 Rn,Rm,imm16
+        exec_instruction("ADD3 R7, R5, -31912",
+                         [(ExprId("R5", 32), ExprInt(0x20, 32))],
+                         [(ExprId("R7", 32), ExprInt(-31880, 32))])
+
+    def test_add(self):
+        """Test ADD execution"""
+
+        # ADD Rn,imm6
+        exec_instruction("ADD R1, 0x10",
+                         [(ExprId("R1", 32), ExprInt(0x32, 32))],
+                         [(ExprId("R1", 32), ExprInt(0x42, 32))])
+
+        exec_instruction("ADD R1, -5",
+                         [(ExprId("R1", 32), ExprInt(0x32, 32))],
+                         [(ExprId("R1", 32), ExprInt(45, 32))])
+
+        exec_instruction("ADD R1, -16",
+                         [(ExprId("R1", 32), ExprInt(0xFFFF, 32))],
+                         [(ExprId("R1", 32), ExprInt(0xFFEF, 32))])
+
+        exec_instruction("ADD R1, -28",
+                         [(ExprId("R1", 32), ExprInt(0, 32))],
+                         [(ExprId("R1", 32), ExprInt(0xFFFFFFE4, 32))])
+
+    def test_advck3(self):
+        """Test ADVCK3 execution"""
+
+        # ADVCK3 R0,Rn,Rm
+        exec_instruction("ADVCK3 R0, R1, R2",
+                         [(ExprId("R1", 32), ExprInt(1, 32)),
+                          (ExprId("R2", 32), ExprInt(2, 32))],
+                         [(ExprId("R0", 32), ExprInt(0, 32))])
+
+        exec_instruction("ADVCK3 R0, R1, R2",
+                         [(ExprId("R1", 32), ExprInt(1, 32)),
+                          (ExprId("R2", 32), ExprInt(0xFFFFFFFF, 32))],
+                         [(ExprId("R0", 32), ExprInt(1, 32))])
+
+    def test_sub(self):
+        """Test SUB execution"""
+
+        # SUB Rn,Rm
+        exec_instruction("SUB R1, R2",
+                         [(ExprId("R1", 32), ExprInt(0x28, 32)),
+                          (ExprId("R2", 32), ExprInt(0x7, 32))],
+                         [(ExprId("R1", 32), ExprInt(0x21, 32))])
+
+    def test_sbvck3(self):
+        """Test SBVCK3 execution"""
+
+        # SBVCK3 R0,Rn,Rm
+        exec_instruction("SBVCK3 R0, R1, R2",
+                         [(ExprId("R1", 32), ExprInt(2, 32)),
+                          (ExprId("R2", 32), ExprInt(1, 32))],
+                         [(ExprId("R0", 32), ExprCond(ExprOp(">",
+                                                             ExprInt(3, 32),
+                                                             ExprCond(ExprOp(">", ExprInt(0x2, 32), ExprInt(0x1, 32)),
+                                                                      ExprInt(0x2, 32),
+                                                                      ExprInt(0x1, 32))),
+                                                      ExprInt(1, 32),
+                                                      ExprInt(0, 32)))])
+
+        exec_instruction("SBVCK3 R0, R1, R2",
+                         [(ExprId("R1", 32), ExprInt(0, 32)),
+                          (ExprId("R2", 32), ExprInt(1, 32))],
+                         [(ExprId("R0", 32), ExprCond(ExprOp(">",
+                                                             ExprInt(1, 32),
+                                                             ExprCond(ExprOp(">", ExprInt(0, 32), ExprInt(1, 32)),
+                                                                      ExprInt(0, 32),
+                                                                      ExprInt(1, 32))),
+                                                      ExprInt(1, 32),
+                                                      ExprInt(0, 32)))])
+
+    def test_neg(self):
+        """Test NEG execution"""
+
+        # NEG Rn,Rm
+        exec_instruction("NEG R1, R2",
+                         [(ExprId("R2", 32), ExprInt(1, 32))],
+                         [(ExprId("R1", 32), ExprInt(0xFFFFFFFF, 32))])
+
+        exec_instruction("NEG R1, R2",
+                         [(ExprId("R2", 32), ExprInt(0x42, 32))],
+                         [(ExprId("R1", 32), ExprInt(0xFFFFFFBE, 32))])
+
+    def test_slt3(self):
+        """Test SLT3 execution"""
+
+        # SLT3 R0,Rn,Rm
+        exec_instruction("SLT3 R0, R1, R2",
+                         [(ExprId("R1", 32), ExprInt(0x2, 32)),
+                          (ExprId("R2", 32), ExprInt(0x1, 32))],
+                         [(ExprId("R0", 32), ExprInt(0, 32))])
+
+        r1 = 0x80000000
+        r2 = 0x80000001
+        exec_instruction("SLT3 R0, R1, R2",
+                         [(ExprId("R1", 32), ExprInt(r1, 32)),
+                          (ExprId("R2", 32), ExprInt(r2, 32))],
+                         [(ExprId("R0", 32), ExprInt(1, 32))])
+
+        r1 = 0x80000000
+        r2 = 0x00000001
+        exec_instruction("SLT3 R0, R1, R2",
+                         [(ExprId("R1", 32), ExprInt(r1, 32)),
+                          (ExprId("R2", 32), ExprInt(r2, 32))],
+                         [(ExprId("R0", 32), ExprInt(1, 32))])
+
+        r1 = 0x00000001
+        r2 = 0x80000000
+        exec_instruction("SLT3 R0, R1, R2",
+                         [(ExprId("R1", 32), ExprInt(r1, 32)),
+                          (ExprId("R2", 32), ExprInt(r2, 32))],
+                         [(ExprId("R0", 32), ExprInt(0, 32))])
+
+        # SLT3 R0,Rn,imm5
+        exec_instruction("SLT3 R0, R1, 12",
+                         [(ExprId("R1", 32), ExprInt(0x1, 32))],
+                         [(ExprId("R0", 32), ExprInt(1, 32))])
+
+        r1 = 0x80000000
+        exec_instruction("SLT3 R0, R1, 12",
+                         [(ExprId("R1", 32), ExprInt(0x80000000, 32))],
+                         [(ExprId("R0", 32), ExprInt(1, 32))])
+
+    def test_sltu3(self):
+        """Test SLTU3 execution"""
+
+        # SLTU3 R0,Rn,Rm
+        exec_instruction("SLTU3 R0, R1, R2",
+                         [(ExprId("R1", 32), ExprInt(0x1, 32)),
+                          (ExprId("R2", 32), ExprInt(0x2, 32))],
+                         [(ExprId("R0", 32), ExprInt(1, 32))])
+
+        exec_instruction("SLTU3 R0, R1, R2",
+                         [(ExprId("R1", 32), ExprInt(0x2, 32)),
+                          (ExprId("R2", 32), ExprInt(0x1, 32))],
+                         [(ExprId("R0", 32), ExprInt(0, 32))])
+
+        # SLTU3 R0,Rn,imm5
+        exec_instruction("SLTU3 R0, R1, 12",
+                         [(ExprId("R1", 32), ExprInt(0x1, 32))],
+                         [(ExprId("R0", 32), ExprInt(1, 32))])
+
+    def test_sl1ad3(self):
+        """Test SL2AD3 execution"""
+
+        # SL1AD3 R0,Rn,Rm
+        exec_instruction("SL1AD3 R0, R1, R2",
+                         [(ExprId("R1", 32), ExprInt(0x2, 32)),
+                          (ExprId("R2", 32), ExprInt(0x20, 32))],
+                         [(ExprId("R0", 32), ExprInt(0x24, 32))])
+
+    def test_sl2ad3(self):
+        """Test SL2AD3 execution"""
+
+        # SL2AD3 R0,Rn,Rm
+        exec_instruction("SL2AD3 R0, R1, R2",
+                         [(ExprId("R1", 32), ExprInt(0x2, 32)),
+                          (ExprId("R2", 32), ExprInt(0x20, 32))],
+                         [(ExprId("R0", 32), ExprInt(0x28, 32))])
diff --git a/test/arch/mep/ir/test_bitmanipulation.py b/test/arch/mep/ir/test_bitmanipulation.py
new file mode 100644
index 00000000..06466f9d
--- /dev/null
+++ b/test/arch/mep/ir/test_bitmanipulation.py
@@ -0,0 +1,55 @@
+# Toshiba MeP-c4 - Bit manipulation instructions unit tests
+# Guillaume Valadon <guillaume@valadon.net>
+
+from ut_helpers_ir import exec_instruction
+
+from miasm2.expression.expression import ExprId, ExprInt, ExprMem
+
+
+class TestBitManipulation:
+
+    def test_bsetm(self):
+        """Test BSETM execution"""
+
+        # BSETM (Rm),imm3
+        exec_instruction("BSETM (R1), 1",
+                         [(ExprId("R1", 32), ExprInt(0x28, 32)),
+                          (ExprMem(ExprInt(0x28, 32), 8), ExprInt(0x1, 8))],
+                         [(ExprMem(ExprInt(0x28, 32), 8), ExprInt(0x3, 8))])
+
+    def test_bclrm(self):
+        """Test BCLRM execution"""
+
+        # BCLRM (Rm),imm3
+        exec_instruction("BCLRM (R1), 1",
+                         [(ExprId("R1", 32), ExprInt(0x28, 32)),
+                          (ExprMem(ExprInt(0x28, 32), 8), ExprInt(0x3, 8))],
+                         [(ExprMem(ExprInt(0x28, 32), 8), ExprInt(0x1, 8))])
+
+    def test_bnotm(self):
+        """Test BNOTM execution"""
+
+        # BNOTM (Rm),imm3
+        exec_instruction("BNOTM (R1), 1",
+                         [(ExprId("R1", 32), ExprInt(0x28, 32)),
+                          (ExprMem(ExprInt(0x28, 32), 8), ExprInt(0x1, 8))],
+                         [(ExprMem(ExprInt(0x28, 32), 8), ExprInt(0x3, 8))])
+
+    def test_btstm(self):
+        """Test BTSTM execution"""
+
+        # BTSTM R0,(Rm),imm3
+        exec_instruction("BTSTM R0, (R1), 1",
+                         [(ExprId("R1", 32), ExprInt(0x28, 32)),
+                          (ExprMem(ExprInt(0x28, 32), 8), ExprInt(0x2, 8))],
+                         [(ExprId("R0", 32), ExprInt(0x2, 32))])
+
+    def test_tas(self):
+        """Test TAS execution"""
+
+        # TAS Rn,(Rm)
+        exec_instruction("TAS R0, (R1)",
+                         [(ExprId("R1", 32), ExprInt(0x28, 32)),
+                          (ExprMem(ExprInt(0x28, 32), 8), ExprInt(0x2, 8))],
+                         [(ExprId("R0", 32), ExprInt(0x2, 32)),
+                          (ExprMem(ExprInt(0x28, 32), 8), ExprInt(0x1, 8))])
diff --git a/test/arch/mep/ir/test_branchjump.py b/test/arch/mep/ir/test_branchjump.py
new file mode 100644
index 00000000..48feb54d
--- /dev/null
+++ b/test/arch/mep/ir/test_branchjump.py
@@ -0,0 +1,191 @@
+# Toshiba MeP-c4 - Branch/Jump instructions unit tests
+# Guillaume Valadon <guillaume@valadon.net>
+
+from ut_helpers_ir import exec_instruction
+
+from miasm2.expression.expression import ExprId, ExprCond, ExprOp, ExprInt
+
+
+class TestBranchJump:
+
+    def test_bra(self):
+        """Test BRA execution"""
+
+        # BRA disp12.align2
+        exec_instruction("BRA 0x28",
+                         [],
+                         [(ExprId("PC", 32), ExprInt(0x28, 32))])
+
+        exec_instruction("BRA 0x800",
+                         [],
+                         [(ExprId("PC", 32), ExprInt(0xFFFFF800, 32))])
+
+        exec_instruction("BRA 0x28",
+                         [],
+                         [(ExprId("PC", 32), ExprInt(0x1028, 32))], offset=0x1000)
+
+    def test_beqz(self):
+        """Test BEQZ execution"""
+
+        # BEQZ Rn,disp8.align2
+        exec_instruction("BEQZ R1, 0x10",
+                         [(ExprId("R1", 32), ExprInt(0, 32))],
+                         [(ExprId("PC", 32), ExprInt(0x20, 32))], offset=0x10)
+
+        exec_instruction("BEQZ R1, 0x10",
+                         [(ExprId("R1", 32), ExprInt(1, 32))],
+                         [(ExprId("PC", 32), ExprInt(0x2, 32))])
+
+        exec_instruction("BEQZ R1, 0x80",
+                         [(ExprId("R1", 32), ExprInt(0, 32))],
+                         [(ExprId("PC", 32), ExprInt(0xFFFFFF90, 32))], offset=0x10)
+
+    def test_bnez(self):
+        """Test BNEZ execution"""
+
+        # BNEZ Rn,disp8.align2
+        exec_instruction("BNEZ R1, 0x10",
+                         [(ExprId("R1", 32), ExprInt(0, 32))],
+                         [(ExprId("PC", 32), ExprInt(0x2, 32))])
+
+        exec_instruction("BNEZ R1, 0x10",
+                         [(ExprId("R1", 32), ExprInt(1, 32))],
+                         [(ExprId("PC", 32), ExprInt(0x20, 32))], offset=0x10)
+
+        exec_instruction("BNEZ R1, 0x80",
+                         [(ExprId("R1", 32), ExprInt(0, 32))],
+                         [(ExprId("PC", 32), ExprInt(0x2, 32))])
+
+    def test_beqi(self):
+        """Test BEQI execution"""
+
+        # BEQI Rn,imm4,disp17.align2
+        exec_instruction("BEQI R1, 0x8, 0x28",
+                         [(ExprId("R1", 32), ExprInt(0, 32))],
+                         [(ExprId("PC", 32), ExprInt(0x4, 32))])
+
+        exec_instruction("BEQI R1, 0x1, 0x28",
+                         [(ExprId("R1", 32), ExprInt(1, 32))],
+                         [(ExprId("PC", 32), ExprInt(0x38, 32))], offset=0x10)
+
+        exec_instruction("BEQI R1, 0x6, 0x10000",
+                         [(ExprId("R1", 32), ExprInt(6, 32))],
+                         [(ExprId("PC", 32), ExprInt(0xFFFF0010, 32))], offset=0x10)
+
+    def test_bnei(self):
+        """Test BNEI execution"""
+
+        # BNEI Rn,imm4,disp17.align2
+        exec_instruction("BNEI R1, 0x5, 0x28",
+                         [(ExprId("R1", 32), ExprInt(0, 32))],
+                         [(ExprId("PC", 32), ExprInt(0x38, 32))], offset=0x10)
+
+        exec_instruction("BNEI R1, 0x7, 0xFF00",
+                         [(ExprId("R1", 32), ExprInt(7, 32)),
+                          (ExprId("PC", 32), ExprInt(0x1, 32))],
+                         [(ExprId("PC", 32), ExprInt(0x4, 32))])
+
+    def test_blti(self):
+        """Test BLTI execution"""
+
+        # BLTI Rn,imm4,disp17.align2
+        exec_instruction("BLTI R1, 0x5, 0x10000",
+                         [(ExprId("R1", 32), ExprInt(0x10, 32))],
+                         [(ExprId("PC", 32), ExprInt(0x14, 32))],
+                         offset=0x10)
+
+        exec_instruction("BLTI R1, 0x5, 0x10000",
+                         [(ExprId("R1", 32), ExprInt(0x1, 32))],
+                         [(ExprId("PC", 32), ExprInt(0xFFFF0010, 32))],
+                         offset=0x10)
+
+    def test_bgei(self):
+        """Test BGEI execution"""
+
+        # BGEI Rn,imm4,disp17.align2
+        exec_instruction("BGEI R1, 0x5, 0x10000",
+                         [(ExprId("R1", 32), ExprInt(0x10, 32))],
+                         [(ExprId("PC", 32), ExprCond(ExprOp(">=", ExprInt(0x10, 32), ExprInt(0x5, 32)), ExprInt(0xFFFF0010, 32), ExprInt(0x14, 32)))],
+                         offset=0x10)
+
+    def test_beq(self):
+        """Test BEQ execution"""
+
+        # BEQ Rn,Rm,disp17.align2
+        exec_instruction("BEQ R1, R2, 0x10000",
+                         [(ExprId("R1", 32), ExprInt(0x10, 32)),
+                          (ExprId("R2", 32), ExprInt(0x10, 32))],
+                         [(ExprId("PC", 32), ExprInt(0xFFFF0010, 32))], offset=0x10)
+
+        exec_instruction("BEQ R1, R2, 0x8000",
+                         [(ExprId("R1", 32), ExprInt(0x09, 32)),
+                          (ExprId("R2", 32), ExprInt(0x10, 32)),
+                          (ExprId("PC", 32), ExprInt(0x10, 32))],
+                         [(ExprId("PC", 32), ExprInt(0x4, 32))])
+
+    def test_bne(self):
+        """Test BNE execution"""
+
+        # BNE Rn,Rm,disp17.align2
+        exec_instruction("BNE R1, R2, 0x8000",
+                         [(ExprId("R1", 32), ExprInt(0x10, 32)),
+                          (ExprId("R2", 32), ExprInt(0x10, 32))],
+                         [(ExprId("PC", 32), ExprInt(0x4, 32))])
+
+        exec_instruction("BNE R1, R2, 0x8000",
+                         [(ExprId("R1", 32), ExprInt(0x09, 32)),
+                          (ExprId("R2", 32), ExprInt(0x10, 32))],
+                         [(ExprId("PC", 32), ExprInt(0x8010, 32))], offset=0x10)
+
+        exec_instruction("BNE R1, R2, 0x10000",
+                         [(ExprId("R1", 32), ExprInt(0x09, 32)),
+                          (ExprId("R2", 32), ExprInt(0x10, 32))],
+                         [(ExprId("PC", 32), ExprInt(0xFFFF0010, 32))], offset=0x10)
+
+    def test_bsr(self):
+        """Test BSR execution"""
+
+        # BSR disp12.align2
+        exec_instruction("BSR 0x800",
+                         [(ExprId("PC", 32), ExprInt(2, 32))],
+                         [(ExprId("PC", 32), ExprInt(0xFFFFF800, 32)),
+                          (ExprId("LP", 32), ExprInt(2, 32))], index=0)
+
+        # BSR disp24.align2
+        exec_instruction("BSR 0x101015",
+                         [(ExprId("PC", 32), ExprInt(4, 32))],
+                         [(ExprId("PC", 32), ExprInt(0x101014, 32)),
+                          (ExprId("LP", 32), ExprInt(4, 32))], index=1)
+
+    def test_jmp(self):
+        """Test JMP execution"""
+
+        # JMP Rm
+        exec_instruction("JMP R1",
+                         [(ExprId("R1", 32), ExprInt(0x101015, 32))],
+                         [(ExprId("PC", 32), ExprInt(0x101015, 32))])
+
+        # JMP target24.align2
+        exec_instruction("JMP 0x2807",
+                         [(ExprId("PC", 32), ExprInt(0, 32))],
+                         [(ExprId("PC", 32), ExprInt(0x2806, 32))], offset=0x42)
+        exec_instruction("JMP 0x2807",
+                         [(ExprId("PC", 32), ExprInt(0xB0000000, 32))],
+                         [(ExprId("PC", 32), ExprInt(0xB0002806, 32))], offset=0xB0000000)
+
+    def test_jsr(self):
+        """Test JSR execution"""
+
+        # JSR Rm
+        exec_instruction("JSR R1",
+                         [(ExprId("R1", 32), ExprInt(0x2807, 32))],
+                         [(ExprId("PC", 32), ExprInt(0x2807, 32)),
+                          (ExprId("LP", 32), ExprInt(0x2, 32))])
+
+    def test_ret(self):
+        """Test RET execution"""
+
+        # RET
+        exec_instruction("RET",
+                         [(ExprId("LP", 32), ExprInt(0x28, 32))],
+                         [(ExprId("PC", 32), ExprInt(0x28, 32))])
diff --git a/test/arch/mep/ir/test_control.py b/test/arch/mep/ir/test_control.py
new file mode 100644
index 00000000..a1b3c7c7
--- /dev/null
+++ b/test/arch/mep/ir/test_control.py
@@ -0,0 +1,105 @@
+# Toshiba MeP-c4 - Control instructions unit tests
+# Guillaume Valadon <guillaume@valadon.net>
+
+from ut_helpers_ir import exec_instruction
+
+from miasm2.expression.expression import ExprId, ExprInt, ExprCond, ExprOp
+
+
+class TestControl:
+
+    def test_stc(self):
+        """Test STC execution"""
+
+        # STC Rn,imm5
+        exec_instruction("STC R1, SAR",
+                         [(ExprId("R1", 32), ExprInt(0x28, 32))],
+                         [(ExprId("SAR", 32), ExprInt(0x28, 32))])
+
+    def test_ldc(self):
+        """Test LDC execution"""
+
+        # LDC Rn,imm5
+        exec_instruction("LDC R1, SAR",
+                         [(ExprId("SAR", 32), ExprInt(0x28, 32))],
+                         [(ExprId("R1", 32), ExprInt(0x28, 32))])
+
+    def test_di(self):
+        """Test DI execution"""
+
+        # DI
+        exec_instruction("DI",
+                         [(ExprId("PSW", 32), ExprInt(1, 32))],
+                         [(ExprId("PSW", 32), ExprInt(0, 32))])
+
+    def test_ei(self):
+        """Test EI execution"""
+
+        # EI
+        exec_instruction("EI",
+                         [(ExprId("PSW", 32), ExprInt(0, 32))],
+                         [(ExprId("PSW", 32), ExprInt(1, 32))])
+
+    def test_reti(self):
+        """Test RETI execution"""
+
+        # RETI
+        exec_instruction("RETI",
+                         [(ExprId("PSW", 32), ExprInt(0xF0000201, 32)),  # PSW_NMI = 1
+                          (ExprId("NPC", 32), ExprInt(0x43, 32))],
+                         [(ExprId("PSW", 32), ExprInt(0xF0000001, 32)),
+                          (ExprId("PC", 32), ExprInt(0x42, 32))])
+
+        exec_instruction("RETI",
+                         [(ExprId("PSW", 32), ExprInt(0b1010, 32)),  # PSW_UMP = 1 & PSW_IEP = 1
+                          (ExprId("EPC", 32), ExprInt(0x29, 32))],
+                         [(ExprId("PSW", 32), ExprInt(0b1111, 32)),  # PSW_UMC = 1 & PSW_IEC = 1
+                          (ExprId("PC", 32), ExprInt(0x28, 32))])
+
+    def test_swi(self):
+        """Test SWI execution"""
+
+        # SWI
+        exec_instruction("SWI 0",
+                         [(ExprId("EXC", 32), ExprInt(0xF0000001, 32))],
+                         [(ExprId("EXC", 32), ExprInt(0xF0000001 + (1 << 4), 32))])
+
+        exec_instruction("SWI 1",
+                         [(ExprId("EXC", 32), ExprInt(0xF0000001, 32))],
+                         [(ExprId("EXC", 32), ExprInt(0xF0000001 + (1 << 5), 32))])
+
+    def test_halt(self):
+        """Test HALT execution"""
+
+        # HALT
+        exec_instruction("HALT", [], [])
+
+    def test_sleep(self):
+        """Test SLEEP execution"""
+
+        # SLEEP
+        exec_instruction("SLEEP", [], [])
+
+    def test_break(self):
+        """Test BREAK execution"""
+
+        # BREAK
+        exec_instruction("BREAK", [], [])
+
+    def test_syncm(self):
+        """Test SYNCM execution"""
+
+        # SYNCM
+        exec_instruction("SYNCM", [], [])
+
+    def test_stcb(self):
+        """Test STCB execution"""
+
+        # STCB Rn,abs16
+        exec_instruction("STCB R0, 0x0", [], [])
+
+    def test_ldcb(self):
+        """Test LDCB execution"""
+
+        # LDCB Rn,abs16
+        exec_instruction("LDCB R0, 0x0", [], [])
diff --git a/test/arch/mep/ir/test_coprocessor.py b/test/arch/mep/ir/test_coprocessor.py
new file mode 100644
index 00000000..e9b745ff
--- /dev/null
+++ b/test/arch/mep/ir/test_coprocessor.py
@@ -0,0 +1,109 @@
+# Toshiba MeP-c4 - Coprocessor instructions unit tests
+# Guillaume Valadon <guillaume@valadon.net>
+
+from ut_helpers_ir import exec_instruction
+
+from miasm2.expression.expression import ExprId, ExprMem, ExprInt
+
+
+class TestCoprocessor:
+
+    def test_swcp(self):
+        """Test SWCP execution"""
+
+        # SWCP CRn,(Rm)
+        exec_instruction("SWCP C1, (R2)",
+                         [(ExprId("C1", 32), ExprInt(0x28071010, 32)),
+                          (ExprId("R2", 32), ExprInt(0x11, 32))],
+                         [(ExprMem(ExprInt(0x10, 32), 32), ExprInt(0x28071010, 32))])
+
+        # SWCP CRn,disp16(Rm)
+        exec_instruction("SWCP C10, 0xF800(R2)",
+                         [(ExprId("C10", 32), ExprInt(0xABC7, 32)),
+                          (ExprId("R2", 32), ExprInt(0x11, 32))],
+                         [(ExprMem(ExprInt(0xFFFFF810, 32), 32), ExprInt(0xABC7, 32))])
+
+    def test_lwcp(self):
+        """Test LWCP execution"""
+
+        # LWCP CRn[0-15],(Rm)
+        exec_instruction("LWCP C1, (R2)",
+                         [(ExprId("R2", 32), ExprInt(0x11, 32)),
+                          (ExprMem(ExprInt(0x10, 32), 32), ExprInt(0xABCD, 32))],
+                         [(ExprId("C1", 32), ExprInt(0xABCD, 32))])
+
+        # LWCP CRn[0-15],disp16(Rm)
+        exec_instruction("LWCP C9, 0xF000(R2)",
+                         [(ExprId("R2", 32), ExprInt(0x42, 32)),
+                          (ExprMem(ExprInt(0xFFFFF040, 32), 32), ExprInt(0x10, 32))],
+                         [(ExprId("C9", 32), ExprInt(0x10, 32))])
+
+    def test_smcp(self):
+        """Test SMCP execution"""
+
+        # SMCP CRn,(Rm)
+        exec_instruction("SMCP C1, (R2)",
+                         [(ExprId("C1", 32), ExprInt(0x28071010, 32)),
+                          (ExprId("R2", 32), ExprInt(0x17, 32))],
+                         [(ExprMem(ExprInt(0x10, 32), 32), ExprInt(0x28071010, 32))])
+
+        # SMCP CRn,disp16(Rm)
+        exec_instruction("SMCP C10, 0xF800(R2)",
+                         [(ExprId("C10", 32), ExprInt(0xABC7, 32)),
+                          (ExprId("R2", 32), ExprInt(0x17, 32))],
+                         [(ExprMem(ExprInt(0xFFFFF810, 32), 32), ExprInt(0xABC7, 32))])
+
+    def test_lmcp(self):
+        """Test LMCP execution"""
+
+        # LMCP CRn[0-15],(Rm)
+        exec_instruction("LMCP C1, (R2)",
+                         [(ExprId("R2", 32), ExprInt(0x10, 32)),
+                          (ExprMem(ExprInt(0x10, 32), 32), ExprInt(0xABCD, 32))],
+                         [(ExprId("C1", 32), ExprInt(0xABCD, 32))])
+
+        # LMCP CRn[0-15],disp16(Rm)
+        exec_instruction("LMCP C9, 0xF000(R2)",
+                         [(ExprId("R2", 32), ExprInt(0x17, 32)),
+                          (ExprMem(ExprInt(0xFFFFF010, 32), 32), ExprInt(0x10, 32))],
+                         [(ExprId("C9", 32), ExprInt(0x10, 32))])
+
+    def test_swcpi(self):
+        """Test SWCPI execution"""
+
+        # SWCPI CRn[0-15],(Rm+)
+        exec_instruction("SWCPI C1, (R2+)",
+                         [(ExprId("C1", 32), ExprInt(0x28071010, 32)),
+                          (ExprId("R2", 32), ExprInt(0x11, 32))],
+                         [(ExprMem(ExprInt(0x10, 32), 32), ExprInt(0x28071010, 32)),
+                          (ExprId("R2", 32), ExprInt(0x15, 32))])
+
+    def test_lwcpi(self):
+        """Test LWCPI execution"""
+
+        # LWCPI CRn[0-15],(Rm+)
+        exec_instruction("LWCPI C1, (R2+)",
+                         [(ExprId("R2", 32), ExprInt(0x11, 32)),
+                          (ExprMem(ExprInt(0x10, 32), 32), ExprInt(0xABCD, 32))],
+                         [(ExprId("C1", 32), ExprInt(0xABCD, 32)),
+                          (ExprId("R2", 32), ExprInt(0x15, 32))])
+
+    def test_smcpi(self):
+        """Test SMCPI execution"""
+
+        # SMCPI CRn[0-15],(Rm+)
+        exec_instruction("SMCPI C1, (R2+)",
+                         [(ExprId("C1", 32), ExprInt(0x28071010, 32)),
+                          (ExprId("R2", 32), ExprInt(0x17, 32))],
+                         [(ExprMem(ExprInt(0x10, 32), 32), ExprInt(0x28071010, 32)),
+                          (ExprId("R2", 32), ExprInt(0x1F, 32))])
+
+    def test_lmcpi(self):
+        """Test LMCPI execution"""
+
+        # LMCPI CRn[0-15],(Rm+)
+        exec_instruction("LMCPI C1, (R2+)",
+                         [(ExprId("R2", 32), ExprInt(0x11, 32)),
+                          (ExprMem(ExprInt(0x10, 32), 32), ExprInt(0xABCD, 32))],
+                         [(ExprId("C1", 32), ExprInt(0xABCD, 32)),
+                          (ExprId("R2", 32), ExprInt(0x19, 32))])
diff --git a/test/arch/mep/ir/test_datacache.py b/test/arch/mep/ir/test_datacache.py
new file mode 100644
index 00000000..a462315d
--- /dev/null
+++ b/test/arch/mep/ir/test_datacache.py
@@ -0,0 +1,13 @@
+# Toshiba MeP-c4 - Data cache instructions unit tests
+# Guillaume Valadon <guillaume@valadon.net>
+
+from ut_helpers_ir import exec_instruction
+
+
+class TestDataCache:
+
+    def test_cache(self):
+        """Test CACHE execution"""
+
+        # CACHE imm4, (Rm)
+        exec_instruction("CACHE 0x0, (R0)", [], [])
diff --git a/test/arch/mep/ir/test_debug.py b/test/arch/mep/ir/test_debug.py
new file mode 100644
index 00000000..53f4064d
--- /dev/null
+++ b/test/arch/mep/ir/test_debug.py
@@ -0,0 +1,33 @@
+# Toshiba MeP-c4 - Debug instructions unit tests
+# Guillaume Valadon <guillaume@valadon.net>
+
+from ut_helpers_ir import exec_instruction
+
+from miasm2.expression.expression import ExprId, ExprInt, ExprCond, ExprOp
+
+
+class TestDebug:
+
+    def test_dret(self):
+        """Test DRET execution"""
+
+        # DRET
+        exec_instruction("DRET",
+                         [(ExprId("DEPC", 32), ExprInt(2, 32)),
+                          (ExprId("DBG", 32), ExprInt(0xFFFFFFFF, 32))],
+                         [(ExprId("PC", 32), ExprInt(2, 32)),
+                          (ExprId("DBG", 32), ExprInt(0xFFFFBFFF, 32))])
+
+        exec_instruction("DRET",
+                         [(ExprId("DEPC", 32), ExprInt(2, 32)),
+                          (ExprId("DBG", 32), ExprInt(2**15, 32))],
+                         [(ExprId("PC", 32), ExprInt(2, 32)),
+                          (ExprId("DBG", 32), ExprInt(2**15, 32))])
+
+    def test_dbreak(self):
+        """Test DBREAK execution"""
+
+        # DBREAK
+        exec_instruction("DBREAK",
+                         [(ExprId("DBG", 32), ExprInt(0, 32))],
+                         [(ExprId("DBG", 32), ExprInt(0b10, 32))])
diff --git a/test/arch/mep/ir/test_divide.py b/test/arch/mep/ir/test_divide.py
new file mode 100644
index 00000000..04d5f6c5
--- /dev/null
+++ b/test/arch/mep/ir/test_divide.py
@@ -0,0 +1,99 @@
+# Toshiba MeP-c4 - Divide instructions unit tests
+# Guillaume Valadon <guillaume@valadon.net>
+
+from ut_helpers_ir import exec_instruction
+
+from miasm2.expression.expression import ExprId, ExprInt, ExprCond, ExprOp
+from miasm2.jitter.csts import EXCEPT_DIV_BY_ZERO
+
+
+class TestDivide:
+
+    def test_div(self):
+        """Test DIV execution"""
+
+        # DIV Rn,Rm
+        exec_instruction("DIV R0, R1",
+                         [(ExprId("R0", 32), ExprInt(0x80, 32)),
+                          (ExprId("R1", 32), ExprInt(0x0, 32)),
+                          (ExprId("HI", 32), ExprInt(0, 32)),
+                          (ExprId("LO", 32), ExprInt(0, 32))],
+                         [(ExprId("HI", 32), ExprInt(0, 32)),
+                          (ExprId("LO", 32), ExprInt(0, 32)),
+                          (ExprId("exception_flags", 32), ExprInt(EXCEPT_DIV_BY_ZERO, 32))])
+
+        # Negative numbers
+        exec_instruction("DIV R0, R1",
+                         [(ExprId("R0", 32), ExprInt(-4, 32)),
+                          (ExprId("R1", 32), ExprInt(-2, 32))],
+                         [(ExprId("HI", 32), ExprInt(0, 32)),
+                          (ExprId("LO", 32), ExprInt(2, 32))])
+
+        exec_instruction("DIV R0, R1",
+                         [(ExprId("R0", 32), ExprInt(-5, 32)),
+                          (ExprId("R1", 32), ExprInt(-2, 32))],
+                         [(ExprId("HI", 32), ExprInt(1, 32)),
+                          (ExprId("LO", 32), ExprInt(2, 32))])
+
+        # Positive numbers
+        exec_instruction("DIV R0, R1",
+                         [(ExprId("R0", 32), ExprInt(4, 32)),
+                          (ExprId("R1", 32), ExprInt(2, 32))],
+                         [(ExprId("HI", 32), ExprCond(ExprOp("==",
+                                                             ExprInt(0, 32),
+                                                             ExprInt(0x80000000, 32)),
+                                                      ExprInt(0, 32),
+                                                      ExprInt(0xFFFFFFFC, 32))),
+                          (ExprId("LO", 32), ExprCond(ExprOp("==",
+                                                             ExprInt(0, 32),
+                                                             ExprInt(0x80000000, 32)),
+                                                       ExprInt(2, 32),
+                                                       ExprInt(0, 32)))])
+
+        # Negative & positive numbers
+        exec_instruction("DIV R0, R1",
+                         [(ExprId("R0", 32), ExprInt(-5, 32)),
+                          (ExprId("R1", 32), ExprInt(2, 32))],
+                         [(ExprId("HI", 32), ExprCond(ExprOp("==", ExprInt(0, 32), ExprInt(0x80000000, 32)),
+                                                      ExprInt(1, 32), ExprInt(0xFFFFFFFF, 32))),
+                          (ExprId("LO", 32), ExprCond(ExprOp("==", ExprInt(0, 32), ExprInt(0x80000000, 32)),
+                                                      ExprInt(0x7FFFFFFD, 32), ExprInt(0xFFFFFFFE, 32)))])
+
+        exec_instruction("DIV R0, R1",
+                         [(ExprId("R0", 32), ExprInt(5, 32)),
+                          (ExprId("R1", 32), ExprInt(-2, 32))],
+                         [(ExprId("HI", 32), ExprCond(ExprOp("==", ExprInt(0, 32), ExprInt(0x80000000, 32)),
+                                                      ExprInt(5, 32), ExprInt(0xFFFFFFFF, 32))),
+                          (ExprId("LO", 32), ExprCond(ExprOp("==", ExprInt(0, 32), ExprInt(0x80000000, 32)),
+                                                      ExprInt(0, 32), ExprInt(0xFFFFFFFE, 32)))])
+
+    def test_divu(self):
+        """Test DIVU execution"""
+
+        # DIVU Rn,Rm
+        exec_instruction("DIVU R0, R1",
+                         [(ExprId("R0", 32), ExprInt(0x80, 32)),
+                          (ExprId("R1", 32), ExprInt(0x0, 32)),
+                          (ExprId("HI", 32), ExprInt(0, 32)),
+                          (ExprId("LO", 32), ExprInt(0, 32))],
+                         [(ExprId("HI", 32), ExprInt(0, 32)),
+                          (ExprId("LO", 32), ExprInt(0, 32)),
+                          (ExprId("exception_flags", 32), ExprInt(EXCEPT_DIV_BY_ZERO, 32))])
+
+        exec_instruction("DIVU R0, R1",
+                         [(ExprId("R0", 32), ExprInt(0x80, 32)),
+                          (ExprId("R1", 32), ExprInt(0x2, 32))],
+                         [(ExprId("HI", 32), ExprInt(0x0, 32)),
+                          (ExprId("LO", 32), ExprInt(0x40, 32))])
+
+        exec_instruction("DIVU R0, R1",
+                         [(ExprId("R0", 32), ExprInt(0x83, 32)),
+                          (ExprId("R1", 32), ExprInt(0x2, 32))],
+                         [(ExprId("HI", 32), ExprInt(0x1, 32)),
+                          (ExprId("LO", 32), ExprInt(0x41, 32))])
+
+        exec_instruction("DIVU R0, R1",
+                         [(ExprId("R0", 32), ExprInt(0x80000000, 32)),
+                          (ExprId("R1", 32), ExprInt(-1, 32))],
+                         [(ExprId("HI", 32), ExprInt(0x80000000, 32)),
+                          (ExprId("LO", 32), ExprInt(0x0, 32))])
diff --git a/test/arch/mep/ir/test_extension.py b/test/arch/mep/ir/test_extension.py
new file mode 100644
index 00000000..72423220
--- /dev/null
+++ b/test/arch/mep/ir/test_extension.py
@@ -0,0 +1,57 @@
+# Toshiba MeP-c4 - Byte/Halfword extension instructions unit tests
+# Guillaume Valadon <guillaume@valadon.net>
+
+from ut_helpers_ir import exec_instruction
+
+from miasm2.expression.expression import ExprId, ExprMem, ExprInt
+
+
+class TestExtension:
+
+    def test_extb(self):
+        """Test EXTB execution"""
+
+        # EXTB Rn
+        exec_instruction("EXTB R1",
+                         [(ExprId("R1", 32), ExprInt(0xFE, 32))],
+                         [(ExprId("R1", 32), ExprInt(0xFFFFFFFE, 32))])
+
+        exec_instruction("EXTB R2",
+                         [(ExprId("R2", 32), ExprInt(0x80, 32))],
+                         [(ExprId("R2", 32), ExprInt(0xFFFFFF80, 32))])
+
+    def test_exth(self):
+        """Test EXTH execution"""
+
+        # EXTH Rn
+        exec_instruction("EXTH R1",
+                         [(ExprId("R1", 32), ExprInt(0xFFFE, 32))],
+                         [(ExprId("R1", 32), ExprInt(0xFFFFFFFE, 32))])
+
+        exec_instruction("EXTH R2",
+                         [(ExprId("R2", 32), ExprInt(0x8000, 32))],
+                         [(ExprId("R2", 32), ExprInt(0xFFFF8000, 32))])
+
+    def test_extub(self):
+        """Test EXTUB execution"""
+
+        # EXTUB Rn
+        exec_instruction("EXTUB R1",
+                         [(ExprId("R1", 32), ExprInt(0xFFFFFFFE, 32))],
+                         [(ExprId("R1", 32), ExprInt(0xFE, 32))])
+
+        exec_instruction("EXTUB R2",
+                         [(ExprId("R2", 32), ExprInt(0xFFFFFF80, 32))],
+                         [(ExprId("R2", 32), ExprInt(0x80, 32))])
+
+    def test_extuh(self):
+        """Test EXTUH execution"""
+
+        # EXTUH Rn
+        exec_instruction("EXTUH R1",
+                         [(ExprId("R1", 32), ExprInt(0xFFFFFFFE, 32))],
+                         [(ExprId("R1", 32), ExprInt(0xFFFE, 32))])
+
+        exec_instruction("EXTUH R2",
+                         [(ExprId("R2", 32), ExprInt(0xFFFF8000, 32))],
+                         [(ExprId("R2", 32), ExprInt(0x8000, 32))])
diff --git a/test/arch/mep/ir/test_ir.py b/test/arch/mep/ir/test_ir.py
new file mode 100644
index 00000000..3fec9ec9
--- /dev/null
+++ b/test/arch/mep/ir/test_ir.py
@@ -0,0 +1,56 @@
+# Toshiba MeP-c4 - Misc unit tests
+# Guillaume Valadon <guillaume@valadon.net>
+
+from miasm2.arch.mep.arch import mn_mep
+from miasm2.arch.mep.regs import regs_init
+from miasm2.arch.mep.ira import ir_mepb, ir_a_mepb
+from miasm2.expression.expression import ExprId, ExprInt, ExprMem
+from miasm2.ir.symbexec import SymbolicExecutionEngine
+from miasm2.core.locationdb import LocationDB
+
+
+class TestMisc:
+
+    def test(self):
+
+        """Simple symbolic execution examples"""
+
+        def exec_instruction(hex_asm, init_values):
+            """Symbolically execute an instruction"""
+
+            print "Hex:", hex_asm
+
+            # Disassemble an instruction
+            mn = mn_mep.dis(hex_asm.decode("hex"), "b")
+            print "Dis:", mn
+
+            # Get the IR
+            im = ir_mepb()
+            iir, eiir, = im.get_ir(mn)
+            print "\nInternal representation:", iir
+
+            # Symbolic execution
+            loc_db = LocationDB()
+            sb = SymbolicExecutionEngine(ir_a_mepb(loc_db), regs_init)
+
+            # Assign register values before symbolic evaluation
+            for reg_expr_id, reg_expr_value in init_values:
+                sb.symbols[reg_expr_id] = reg_expr_value
+
+            print "\nModified registers:", [reg for reg in sb.modified(mems=False)]
+            print "Modified memories:", [mem for mem in sb.modified()]
+
+            print "\nFinal registers:"
+            sb.dump(mems=False)
+
+            print "\nFinal mems:"
+            sb.dump()
+
+        for hex_asm, init_values in [("6108", [(ExprId("R1", 32), ExprInt(0x40, 32))]),
+                                     ("08a2", [(ExprId("R8", 32), ExprInt(0x40, 32)),
+                                               (ExprId("R10", 32), ExprInt(0x41, 32))]),
+                                     ("0948", [(ExprId("R4", 32), ExprInt(0x41, 32)),
+                                               (ExprId("R9", 32), ExprInt(0x28, 32)),
+                                               (ExprMem(ExprInt(0x41, 32), 8), ExprInt(0, 8))])]:
+            print "-" * 49  # Tests separation
+            exec_instruction(hex_asm, init_values)
diff --git a/test/arch/mep/ir/test_ldz.py b/test/arch/mep/ir/test_ldz.py
new file mode 100644
index 00000000..02960b60
--- /dev/null
+++ b/test/arch/mep/ir/test_ldz.py
@@ -0,0 +1,41 @@
+# Toshiba MeP-c4 - Leading zero instructions unit tests
+# Guillaume Valadon <guillaume@valadon.net>
+
+from ut_helpers_ir import exec_instruction
+
+from miasm2.expression.expression import ExprId, ExprInt, ExprCond, ExprOp
+
+
+class TestLdz:
+
+    def test_ldz(self):
+        """Test LDZ execution"""
+
+        # LDZ Rn,Rm
+        exec_instruction("LDZ R0, R1",
+                         [(ExprId("R1", 32), ExprInt(0x80000000, 32))],
+                         [(ExprId("R0", 32), ExprInt(0, 32))])
+
+        exec_instruction("LDZ R0, R1",
+                         [(ExprId("R1", 32), ExprInt(0x40000000, 32))],
+                         [(ExprId("R0", 32), ExprInt(1, 32))])
+
+        exec_instruction("LDZ R0, R1",
+                         [(ExprId("R1", 32), ExprInt(0b1111, 32))],
+                         [(ExprId("R0", 32), ExprInt(28, 32))])
+
+        exec_instruction("LDZ R0, R1",
+                         [(ExprId("R1", 32), ExprInt(0b0100, 32))],
+                         [(ExprId("R0", 32), ExprInt(29, 32))])
+
+        exec_instruction("LDZ R0, R1",
+                         [(ExprId("R1", 32), ExprInt(0b0010, 32))],
+                         [(ExprId("R0", 32), ExprInt(30, 32))])
+
+        exec_instruction("LDZ R0, R1",
+                         [(ExprId("R1", 32), ExprInt(0b0001, 32))],
+                         [(ExprId("R0", 32), ExprInt(31, 32))])
+
+        exec_instruction("LDZ R0, R1",
+                         [(ExprId("R1", 32), ExprInt(0b0000, 32))],
+                         [(ExprId("R0", 32), ExprInt(32, 32))])
diff --git a/test/arch/mep/ir/test_loadstore.py b/test/arch/mep/ir/test_loadstore.py
new file mode 100644
index 00000000..c6b40d55
--- /dev/null
+++ b/test/arch/mep/ir/test_loadstore.py
@@ -0,0 +1,209 @@
+# Toshiba MeP-c4 - Load/Store instructions unit tests
+# Guillaume Valadon <guillaume@valadon.net>
+
+from ut_helpers_ir import exec_instruction
+
+from miasm2.expression.expression import ExprId, ExprMem, ExprInt
+
+
+class TestLoadStore:
+
+    def test_sb(self):
+        """Test SB execution"""
+
+        # SB Rn,(Rm)
+        exec_instruction("SB R1, (R2)",
+                         [(ExprId("R1", 32), ExprInt(0x28, 32)),
+                          (ExprId("R2", 32), ExprInt(0x10, 32))],
+                         [(ExprMem(ExprInt(0x10, 32), 8), ExprInt(0x28, 8))])
+
+        # SB Rn[0-7], disp7(TP)
+        exec_instruction("SB R1, 0x18(R2)",
+                         [(ExprId("R1", 32), ExprInt(0xABC7, 32)),
+                          (ExprId("R2", 32), ExprInt(0x10, 32))],
+                         [(ExprMem(ExprInt(0x28, 32), 8), ExprInt(0xC7, 8))])
+
+        # SB Rn,disp16(Rm)
+        exec_instruction("SB R10, 0xF800(R2)",
+                         [(ExprId("R10", 32), ExprInt(0xABC7, 32)),
+                          (ExprId("R2", 32), ExprInt(0x10, 32))],
+                         [(ExprMem(ExprInt(0xFFFFF810, 32), 8), ExprInt(0xC7, 8))])
+
+    def test_sh(self):
+        """Test SH execution"""
+
+        # SH Rn,(Rm)
+        exec_instruction("SH R1, (R2)",
+                         [(ExprId("R1", 32), ExprInt(0x2807, 32)),
+                          (ExprId("R2", 32), ExprInt(0x10, 32))],
+                         [(ExprMem(ExprInt(0x10, 32), 16), ExprInt(0x2807, 16))])
+
+        # SH Rn[0-7],disp7.align2(TP)
+        exec_instruction("SH R1, 0x18(R2)",
+                         [(ExprId("R1", 32), ExprInt(0xABC7, 32)),
+                          (ExprId("R2", 32), ExprInt(0x10, 32))],
+                         [(ExprMem(ExprInt(0x28, 32), 16), ExprInt(0xABC7, 16))])
+
+        # SH Rn,disp16(Rm)
+        exec_instruction("SH R10, 0xF800(R2)",
+                         [(ExprId("R10", 32), ExprInt(0xABC7, 32)),
+                          (ExprId("R2", 32), ExprInt(0x10, 32))],
+                         [(ExprMem(ExprInt(0xFFFFF810, 32), 16), ExprInt(0xABC7, 16))])
+
+    def test_sw(self):
+        """Test SW execution"""
+
+        # SW Rn,(Rm)
+        exec_instruction("SW R1, (R2)",
+                         [(ExprId("R1", 32), ExprInt(0x28071010, 32)),
+                          (ExprId("R2", 32), ExprInt(0x10, 32))],
+                         [(ExprMem(ExprInt(0x10, 32), 32), ExprInt(0x28071010, 32))])
+
+        # SW Rn,disp7.align4(SP)
+        exec_instruction("SW R1, 4(SP)",
+                         [(ExprId("R1", 32), ExprInt(0x28071010, 32)),
+                          (ExprId("SP", 32), ExprInt(0x10, 32))],
+                         [(ExprMem(ExprInt(0x14, 32), 32), ExprInt(0x28071010, 32))])
+
+        # SW Rn,disp7.align4(TP)
+        exec_instruction("SW R1, 12(TP)",
+                         [(ExprId("R1", 32), ExprInt(0x28071010, 32)),
+                          (ExprId("TP", 32), ExprInt(0x10, 32))],
+                         [(ExprMem(ExprInt(0x1c, 32), 32), ExprInt(0x28071010, 32))])
+
+        # SW Rn,disp16(Rm)
+        exec_instruction("SW R10, 0xF800(R2)",
+                         [(ExprId("R10", 32), ExprInt(0xABC7, 32)),
+                          (ExprId("R2", 32), ExprInt(0x10, 32))],
+                         [(ExprMem(ExprInt(0xFFFFF810, 32), 32), ExprInt(0xABC7, 32))])
+
+        # SW Rn,(abs24.align4)
+        exec_instruction("SW R10, (0x1010)",
+                         [(ExprId("R10", 32), ExprInt(0xABC7, 32))],
+                         [(ExprMem(ExprInt(0x1010, 32), 32), ExprInt(0xABC7, 32))])
+
+    def test_lb(self):
+        """Test LB executon"""
+
+        # LB Rn,(Rm)
+        exec_instruction("LB R1, (R2)",
+                         [(ExprId("R2", 32), ExprInt(0x10, 32)),
+                          (ExprMem(ExprInt(0x10, 32), 8), ExprInt(0xF0, 8))],
+                         [(ExprId("R1", 32), ExprInt(0xFFFFFFF0, 32))])
+
+        # LB Rn[0-7],disp7(TP)
+        exec_instruction("LB R7, 0x3(TP)",
+                         [(ExprId("TP", 32), ExprInt(0x10, 32)),
+                          (ExprMem(ExprInt(0x13, 32), 8), ExprInt(0xF0, 8))],
+                         [(ExprId("R7", 32), ExprInt(0xFFFFFFF0, 32))])
+
+        # LB Rn,disp16(Rm)
+        exec_instruction("LB R10, 0xF800(R2)",
+                         [(ExprId("R2", 32), ExprInt(0x10, 32)),
+                          (ExprMem(ExprInt(0xFFFFF810, 32), 8), ExprInt(0x4, 8))],
+                         [(ExprId("R10", 32), ExprInt(0x4, 32))])
+
+        exec_instruction("LB R10, 0xF800(R2)",
+                         [(ExprId("R2", 32), ExprInt(0x10, 32)),
+                          (ExprMem(ExprInt(0xFFFFF810, 32), 8), ExprInt(0xFE, 8))],
+                         [(ExprId("R10", 32), ExprInt(0xFFFFFFFE, 32))])
+
+    def test_lh(self):
+        """Test lh execution"""
+
+        # LH Rn,(Rm)
+        exec_instruction("LH R1, (R2)",
+                         [(ExprId("R2", 32), ExprInt(0x10, 32)),
+                          (ExprMem(ExprInt(0x10, 32), 16), ExprInt(0xF517, 16))],
+                         [(ExprId("R1", 32), ExprInt(0xFFFFF517, 32))])
+
+        # LH Rn[0-7],disp7.align2(TP)
+        exec_instruction("LH R1, 0x18(R2)",
+                         [(ExprId("R2", 32), ExprInt(0x10, 32)),
+                          (ExprMem(ExprInt(0x28, 32), 16), ExprInt(0xF517, 16))],
+                         [(ExprId("R1", 32), ExprInt(0xFFFFF517, 32))])
+
+        # LH Rn,disp16(Rm)
+        exec_instruction("LH R9, 0xF000(R2)",
+                         [(ExprId("R2", 32), ExprInt(0x42, 32)),
+                          (ExprMem(ExprInt(0xFFFFF042, 32), 16), ExprInt(0x10, 16))],
+                         [(ExprId("R9", 32), ExprInt(0x10, 32))])
+
+        exec_instruction("LH R9, 0xF000(R2)",
+                         [(ExprId("R2", 32), ExprInt(0x42, 32)),
+                          (ExprMem(ExprInt(0xFFFFF042, 32), 16), ExprInt(0xABCD, 16))],
+                         [(ExprId("R9", 32), ExprInt(0xFFFFABCD, 32))])
+
+    def test_lw(self):
+        """Test SW execution"""
+
+        # LW Rn,(Rm)
+        exec_instruction("LW R1, (R2)",
+                         [(ExprId("R2", 32), ExprInt(0x10, 32)),
+                          (ExprMem(ExprInt(0x10, 32), 32), ExprInt(0xABCD, 32))],
+                         [(ExprId("R1", 32), ExprInt(0xABCD, 32))])
+
+        #  LW Rn,disp7.align4(SP)
+        exec_instruction("LW R1, 0x18(SP)",
+                         [(ExprId("SP", 32), ExprInt(0x10, 32)),
+                          (ExprMem(ExprInt(0x28, 32), 32), ExprInt(0x01234567, 32))],
+                         [(ExprId("R1", 32), ExprInt(0x01234567, 32))])
+
+        # LW Rn[0-7],disp7.align4(TP)
+        exec_instruction("LW R1, 0x18(TP)",
+                         [(ExprId("TP", 32), ExprInt(0x10, 32)),
+                          (ExprMem(ExprInt(0x28, 32), 32), ExprInt(0x1010, 32))],
+                         [(ExprId("R1", 32), ExprInt(0x1010, 32))])
+
+        # LW Rn,disp16(Rm)
+        exec_instruction("LW R9, 0xF000(R2)",
+                         [(ExprId("R2", 32), ExprInt(0x42, 32)),
+                          (ExprMem(ExprInt(0xFFFFF040, 32), 32), ExprInt(0x10, 32))],
+                         [(ExprId("R9", 32), ExprInt(0x10, 32))])
+
+        # LW Rn,(abs24.align4)
+        exec_instruction("LW R10, (0x1010)",
+                         [(ExprMem(ExprInt(0x1010, 32), 32), ExprInt(0xABC7, 32))],
+                         [(ExprId("R10", 32), ExprInt(0xABC7, 32))])
+
+    def test_lbu(self):
+        """Test LBU execution"""
+
+        # LBU Rn,(Rm)
+        exec_instruction("LBU R1, (R2)",
+                         [(ExprId("R2", 32), ExprInt(0x10, 32)),
+                          (ExprMem(ExprInt(0x10, 32), 8), ExprInt(0xA, 8))],
+                         [(ExprId("R1", 32), ExprInt(0xA, 32))])
+
+        # LBU Rn[0-7],disp7(TP)
+        exec_instruction("LBU R1, 0x22(R3)",
+                         [(ExprId("R3", 32), ExprInt(0x10, 32)),
+                          (ExprMem(ExprInt(0x32, 32), 8), ExprInt(0xA, 8))],
+                         [(ExprId("R1", 32), ExprInt(0xA, 32))])
+
+        # LBU Rn,disp16(Rm)
+        exec_instruction("LBU R10, 0xF000(R2)",
+                         [(ExprId("R2", 32), ExprInt(0x42, 32)),
+                          (ExprMem(ExprInt(0xFFFFF042, 32), 32), ExprInt(0x10, 32))],
+                         [(ExprId("R10", 32), ExprInt(0x10, 32))])
+
+    def test_lhu(self):
+        """Test LHU execution"""
+
+        # LHU Rn,(Rm)
+        exec_instruction("LHU R1, (R2)",
+                         [(ExprId("R2", 32), ExprInt(0x10, 32)),
+                          (ExprMem(ExprInt(0x10, 32), 16), ExprInt(0xEF, 16))],
+                         [(ExprId("R1", 32), ExprInt(0xEF, 32))])
+
+        # LHU Rn[0-7],disp7.align2(TP)
+        exec_instruction("LHU R1, 0x22(R3)",
+                         [(ExprId("R3", 32), ExprInt(0x10, 32)),
+                          (ExprMem(ExprInt(0x32, 32), 16), ExprInt(0xFEDC, 16))],
+                         [(ExprId("R1", 32), ExprInt(0xFEDC, 32))])
+
+        # LHU Rn,disp16(Rm)
+        exec_instruction("LHU R10, 0xF000(R2)",
+                         [(ExprId("R2", 32), ExprInt(0x42, 32)),
+                          (ExprMem(ExprInt(0xFFFFF042, 32), 16), ExprInt(0x1234, 16))],
+                         [(ExprId("R10", 32), ExprInt(0x1234, 32))])
diff --git a/test/arch/mep/ir/test_logical.py b/test/arch/mep/ir/test_logical.py
new file mode 100644
index 00000000..61cbbf0a
--- /dev/null
+++ b/test/arch/mep/ir/test_logical.py
@@ -0,0 +1,65 @@
+# Toshiba MeP-c4 - Logical instructions unit tests
+# Guillaume Valadon <guillaume@valadon.net>
+
+from ut_helpers_ir import exec_instruction
+
+from miasm2.expression.expression import ExprId, ExprInt, ExprCond, ExprOp
+
+
+class TestLogical:
+
+    def test_or(self):
+        """Test OR execution"""
+
+        # OR Rn, Rm
+        exec_instruction("OR R1, R2",
+                         [(ExprId("R1", 32), ExprInt(1, 32)), (ExprId("R2", 32), ExprInt(1, 32))],
+                         [(ExprId("R1", 32), ExprInt(1, 32))])
+
+    def test_or3(self):
+        """Test OR3 execution"""
+
+        # OR3 Rn,Rm,imm16
+        exec_instruction("OR3 R1, R2, 1",
+                         [(ExprId("R2", 32), ExprInt(1, 32))],
+                         [(ExprId("R1", 32), ExprInt(1, 32))])
+
+    def test_and(self):
+        """Test AND  execution"""
+
+        # AND Rn, Rm
+        exec_instruction("AND R1, R2",
+                         [(ExprId("R1", 32), ExprInt(1, 32)), (ExprId("R2", 32), ExprInt(0, 32))],
+                         [(ExprId("R1", 32), ExprInt(0, 32))])
+
+    def test_and3(self):
+        """Test AND3 execution"""
+
+        # AND3 Rn,Rm,imm16
+        exec_instruction("AND3 R1, R2, 0",
+                         [(ExprId("R2", 32), ExprInt(1, 32))],
+                         [(ExprId("R1", 32), ExprInt(0, 32))])
+
+    def test_xor(self):
+        """Test XOR execution"""
+
+        # XOR Rn, Rm
+        exec_instruction("XOR R1, R2",
+                         [(ExprId("R1", 32), ExprInt(1, 32)), (ExprId("R2", 32), ExprInt(0, 32))],
+                         [(ExprId("R1", 32), ExprInt(1, 32))])
+
+    def test_xor3(self):
+        """Test XOR3 execution"""
+
+        # XOR3 Rn,Rm,imm16
+        exec_instruction("XOR3 R1, R2, 1",
+                         [(ExprId("R2", 32), ExprInt(0, 32))],
+                         [(ExprId("R1", 32), ExprInt(1, 32))])
+
+    def test_nor(self):
+        """Test NOR execution"""
+
+        # NOR Rn, Rm
+        exec_instruction("NOR R1, R2",
+                         [(ExprId("R1", 32), ExprInt(1, 32)), (ExprId("R2", 32), ExprInt(0, 32))],
+                         [(ExprId("R1", 32), ExprInt(0xFFFFFFFE, 32))])
diff --git a/test/arch/mep/ir/test_move.py b/test/arch/mep/ir/test_move.py
new file mode 100644
index 00000000..56a4225e
--- /dev/null
+++ b/test/arch/mep/ir/test_move.py
@@ -0,0 +1,58 @@
+# Toshiba MeP-c4 - Move instructions unit tests
+# Guillaume Valadon <guillaume@valadon.net>
+
+from ut_helpers_ir import exec_instruction
+
+from miasm2.expression.expression import ExprId, ExprMem, ExprInt
+
+
+class TestMove:
+
+    def test_mov(self):
+        """Test MOV execution"""
+
+        # MOV Rn,Rm
+        exec_instruction("MOV R1, R2",
+                         [(ExprId("R2", 32), ExprInt(0x2807, 32))],
+                         [(ExprId("R1", 32), ExprInt(0x2807, 32))])
+
+        # MOV Rn,imm8
+        exec_instruction("MOV R1, 0x28",
+                         [],
+                         [(ExprId("R1", 32), ExprInt(0x28, 32))])
+
+        exec_instruction("MOV R1, 0x80",
+                         [],
+                         [(ExprId("R1", 32), ExprInt(0xFFFFFF80, 32))])
+
+        # MOV Rn,imm16
+        exec_instruction("MOV R1, 0x2807",
+                         [],
+                         [(ExprId("R1", 32), ExprInt(0x2807, 32))],
+                         index=1)
+
+    def test_movu(self):
+        """Test MOVU execution"""
+
+        # MOVU Rn[0-7],imm24
+        exec_instruction("MOVU R1, 0xFF2807",
+                         [],
+                         [(ExprId("R1", 32), ExprInt(0xFF2807, 32))],
+                         index=1)
+
+        # MOVU Rn,imm16
+        exec_instruction("MOVU R10, 0x2807",
+                         [],
+                         [(ExprId("R10", 32), ExprInt(0x2807, 32))])
+
+    def test_movh(self):
+        """Test MOVH execution"""
+
+        # MOVH Rn,imm16
+        exec_instruction("MOVH R1, 1",
+                         [],
+                         [(ExprId("R1", 32), ExprInt(0x10000, 32))])
+
+        exec_instruction("MOVH R1, 0xFFFF",
+                         [],
+                         [(ExprId("R1", 32), ExprInt(0xFFFF0000, 32))])
diff --git a/test/arch/mep/ir/test_multiply.py b/test/arch/mep/ir/test_multiply.py
new file mode 100644
index 00000000..0618f69f
--- /dev/null
+++ b/test/arch/mep/ir/test_multiply.py
@@ -0,0 +1,138 @@
+# Toshiba MeP-c4 - Multiply instructions unit tests
+# Guillaume Valadon <guillaume@valadon.net>
+
+from ut_helpers_ir import exec_instruction
+
+from miasm2.expression.expression import ExprId, ExprInt, ExprCond, ExprOp
+
+
+class TestMultiply:
+
+    def test_mul(self):
+        """Test MUL execution"""
+
+        # MUL Rn,Rm
+        exec_instruction("MUL R0, R1",
+                         [(ExprId("R0", 32), ExprInt(0x80, 32)),
+                          (ExprId("R1", 32), ExprInt(0xFFFFFFFF, 32))],
+                         [(ExprId("HI", 32), ExprInt(0xFFFFFFFF, 32)),
+                          (ExprId("LO", 32), ExprInt(0xFFFFFF80, 32))])
+
+        exec_instruction("MUL R0, R1",
+                         [(ExprId("R0", 32), ExprInt(0x80000000, 32)),
+                          (ExprId("R1", 32), ExprInt(0xFFFFFFFF, 32))],
+                         [(ExprId("HI", 32), ExprInt(0x00000000, 32)),
+                          (ExprId("LO", 32), ExprInt(0x80000000, 32))])
+
+    def test_mulu(self):
+        """Test MULU execution"""
+
+        # MULU Rn,Rm
+        exec_instruction("MULU R0, R1",
+                         [(ExprId("R0", 32), ExprInt(0x2, 32)),
+                          (ExprId("R1", 32), ExprInt(0xFFFFFFFF, 32))],
+                         [(ExprId("HI", 32), ExprInt(0x1, 32)),
+                          (ExprId("LO", 32), ExprInt(0xFFFFFFFE, 32))])
+
+        exec_instruction("MULU R0, R1",
+                         [(ExprId("R0", 32), ExprInt(0x80000000, 32)),
+                          (ExprId("R1", 32), ExprInt(0xFFFFFFFF, 32))],
+                         [(ExprId("HI", 32), ExprInt(0x7FFFFFFF, 32)),
+                          (ExprId("LO", 32), ExprInt(0x80000000, 32))])
+
+    def test_mulr(self):
+        """Test MULR execution"""
+
+        # MULR Rn,Rm
+        exec_instruction("MULR R0, R1",
+                         [(ExprId("R0", 32), ExprInt(0x80, 32)),
+                          (ExprId("R1", 32), ExprInt(0xFFFFFFFF, 32))],
+                         [(ExprId("HI", 32), ExprInt(0xFFFFFFFF, 32)),
+                          (ExprId("LO", 32), ExprInt(0xFFFFFF80, 32)),
+                          (ExprId("R0", 32), ExprInt(0xFFFFFF80, 32))])
+
+    def test_mulru(self):
+        """Test MULRU execution"""
+
+        # MULRU Rn,Rm
+        exec_instruction("MULRU R0, R1",
+                         [(ExprId("R0", 32), ExprInt(0x2, 32)),
+                          (ExprId("R1", 32), ExprInt(0xFFFFFFFF, 32))],
+                         [(ExprId("HI", 32), ExprInt(0x1, 32)),
+                          (ExprId("LO", 32), ExprInt(0xFFFFFFFE, 32)),
+                          (ExprId("R0", 32), ExprInt(0xFFFFFFFE, 32))])
+
+    def test_madd(self):
+        """Test MADD execution"""
+
+        # MADD Rn,Rm
+        exec_instruction("MADD R0, R1",
+                         [(ExprId("R0", 32), ExprInt(0x80, 32)),
+                          (ExprId("R1", 32), ExprInt(0xFFFFFFFF, 32)),
+                          (ExprId("HI", 32), ExprInt(0, 32)),
+                          (ExprId("LO", 32), ExprInt(0, 32))],
+                         [(ExprId("HI", 32), ExprInt(0xFFFFFFFF, 32)),
+                          (ExprId("LO", 32), ExprInt(0xFFFFFF80, 32))])
+
+        exec_instruction("MADD R0, R1",
+                         [(ExprId("R0", 32), ExprInt(0x80, 32)),
+                          (ExprId("R1", 32), ExprInt(0xFFFFFFFF, 32)),
+                          (ExprId("HI", 32), ExprInt(1, 32)),
+                          (ExprId("LO", 32), ExprInt(1, 32))],
+                         [(ExprId("HI", 32), ExprInt(0xFFFFFFFF, 32)),
+                          (ExprId("LO", 32), ExprInt(0xFFFFFF81, 32))])
+
+    def test_maddu(self):
+        """Test MADDU execution"""
+
+        # MADDU Rn,Rm
+        exec_instruction("MADDU R0, R1",
+                         [(ExprId("R0", 32), ExprInt(0x2, 32)),
+                          (ExprId("R1", 32), ExprInt(0xFFFFFFFF, 32)),
+                          (ExprId("HI", 32), ExprInt(0, 32)),
+                          (ExprId("LO", 32), ExprInt(0, 32))],
+                         [(ExprId("HI", 32), ExprInt(0x1, 32)),
+                          (ExprId("LO", 32), ExprInt(0xFFFFFFFE, 32))])
+
+        exec_instruction("MADDU R0, R1",
+                         [(ExprId("R0", 32), ExprInt(0x2, 32)),
+                          (ExprId("R1", 32), ExprInt(0xFFFFFFFF, 32)),
+                          (ExprId("HI", 32), ExprInt(1, 32)),
+                          (ExprId("LO", 32), ExprInt(1, 32))],
+                         [(ExprId("HI", 32), ExprInt(0x1, 32)),
+                          (ExprId("LO", 32), ExprInt(0xFFFFFFFF, 32))])
+
+    def test_maddr(self):
+        """Test MADDR execution"""
+
+        # MADDR Rn,Rm
+        exec_instruction("MADDR R0, R1",
+                         [(ExprId("R0", 32), ExprInt(0x80, 32)),
+                          (ExprId("R1", 32), ExprInt(0xFFFFFFFF, 32)),
+                          (ExprId("HI", 32), ExprInt(0, 32)),
+                          (ExprId("LO", 32), ExprInt(0, 32))],
+                         [(ExprId("HI", 32), ExprInt(0xFFFFFFFF, 32)),
+                          (ExprId("LO", 32), ExprInt(0xFFFFFF80, 32)),
+                          (ExprId("R0", 32), ExprInt(0xFFFFFF80, 32))])
+
+        exec_instruction("MADDR R0, R1",
+                         [(ExprId("R0", 32), ExprInt(0x80, 32)),
+                          (ExprId("R1", 32), ExprInt(0xFFFFFFFF, 32)),
+                          (ExprId("HI", 32), ExprInt(1, 32)),
+                          (ExprId("LO", 32), ExprInt(1, 32))],
+                         [(ExprId("HI", 32), ExprInt(0xFFFFFFFF, 32)),
+                          (ExprId("LO", 32), ExprInt(0xFFFFFF81, 32)),
+                          (ExprId("R0", 32), ExprInt(0xFFFFFF81, 32))])
+
+    def test_maddru(self):
+        """Test MADDRU execution"""
+
+        # MADDRU Rn,Rm
+        exec_instruction("MADDRU R0, R1",
+                         [(ExprId("R0", 32), ExprInt(0x2, 32)),
+                          (ExprId("R1", 32), ExprInt(0xFFFFFFFF, 32)),
+                          (ExprId("HI", 32), ExprInt(0, 32)),
+                          (ExprId("LO", 32), ExprInt(0, 32))],
+                         [(ExprId("HI", 32), ExprInt(0x1, 32)),
+                          (ExprId("LO", 32), ExprInt(0xFFFFFFFE, 32)),
+                          (ExprId("R0", 32), ExprInt(0xFFFFFFFE, 32))])
diff --git a/test/arch/mep/ir/test_repeat.py b/test/arch/mep/ir/test_repeat.py
new file mode 100644
index 00000000..252764b1
--- /dev/null
+++ b/test/arch/mep/ir/test_repeat.py
@@ -0,0 +1,29 @@
+# Toshiba MeP-c4 - Repeat instructions unit tests
+# Guillaume Valadon <guillaume@valadon.net>
+
+from ut_helpers_ir import exec_instruction
+
+from miasm2.expression.expression import ExprId, ExprInt, ExprCond, ExprOp
+
+
+class TestRepeat:
+
+    def test_repeat(self):
+        """Test REPEAT execution"""
+
+        # REPEAT Rn, disp17.align2
+        exec_instruction("REPEAT R0, 0x42",
+                         [(ExprId("PC", 32), ExprInt(2, 32)),
+                          (ExprId("R0", 32), ExprInt(0x28, 32))],
+                         [(ExprId("RPB", 32), ExprInt(6, 32)),
+                          (ExprId("RPE", 32), ExprInt(0x44, 32)),
+                          (ExprId("RPC", 32), ExprInt(0x28, 32))])
+
+    def test_erepeat(self):
+        """Test EREPEAT execution"""
+
+        # EREPEAT disp17.align2
+        exec_instruction("EREPEAT 0x42",
+                         [(ExprId("PC", 32), ExprInt(0, 32))],
+                         [(ExprId("RPB", 32), ExprInt(4, 32)),
+                          (ExprId("RPE", 32), ExprInt(0x43, 32))])
diff --git a/test/arch/mep/ir/test_shift.py b/test/arch/mep/ir/test_shift.py
new file mode 100644
index 00000000..b63f9ed7
--- /dev/null
+++ b/test/arch/mep/ir/test_shift.py
@@ -0,0 +1,108 @@
+# Toshiba MeP-c4 - Shift instructions unit tests
+# Guillaume Valadon <guillaume@valadon.net>
+
+from ut_helpers_ir import exec_instruction
+
+from miasm2.expression.expression import ExprId, ExprInt, ExprCond, ExprOp
+from miasm2.core.cpu import sign_ext
+
+
+class TestShift:
+
+    def test_sra(self):
+        """Test SRA execution"""
+
+        # SRA Rn, Rm
+        exec_instruction("SRA R1, R2",
+                         [(ExprId("R1", 32), ExprInt(4, 32)), (ExprId("R2", 32), ExprInt(1, 32))],
+                         [(ExprId("R1", 32), ExprInt(2, 32))])
+
+        exec_instruction("SRA R1, R2",
+                         [(ExprId("R1", 32), ExprInt(sign_ext(4, 3, 32), 32)), (ExprId("R2", 32), ExprInt(1, 32))],
+                         [(ExprId("R1", 32), ExprInt(0xFFFFFFFE, 32))])
+
+        exec_instruction("SRA R1, R2",
+                         [(ExprId("R1", 32), ExprInt(0xF0000000, 32)), (ExprId("R2", 32), ExprInt(4, 32))],
+                         [(ExprId("R1", 32), ExprInt(0xFF000000, 32))])
+
+        # SRA Rn,imm5
+        exec_instruction("SRA R1, 1",
+                         [(ExprId("R1", 32), ExprInt(4, 32))],
+                         [(ExprId("R1", 32), ExprInt(2, 32))])
+
+        # SRA Rn,imm5
+        exec_instruction("SRA R1, 1",
+                         [(ExprId("R1", 32), ExprInt(0x80000000, 32))],
+                         [(ExprId("R1", 32), ExprInt(0xC0000000, 32))])
+
+        exec_instruction("SRA R1, 1",
+                         [(ExprId("R1", 32), ExprInt(1, 32))],
+                         [(ExprId("R1", 32), ExprInt(0, 32))])
+
+    def test_srl(self):
+        """Test SRL execution"""
+
+        # SRL Rn, Rm
+        exec_instruction("SRL R1, R2",
+                         [(ExprId("R1", 32), ExprInt(4, 32)), (ExprId("R2", 32), ExprInt(1, 32))],
+                         [(ExprId("R1", 32), ExprInt(2, 32))])
+
+        # SRL Rn,imm5
+        exec_instruction("SRL R1, 1",
+                         [(ExprId("R1", 32), ExprInt(4, 32))],
+                         [(ExprId("R1", 32), ExprInt(2, 32))])
+
+        exec_instruction("SRL R1, 1",
+                         [(ExprId("R1", 32), ExprInt(1, 32))],
+                         [(ExprId("R1", 32), ExprInt(0, 32))])
+
+    def test_sll(self):
+        """Test SLL execution"""
+
+        # SLL Rn, Rm
+        exec_instruction("SLL R1, R2",
+                         [(ExprId("R1", 32), ExprInt(4, 32)), (ExprId("R2", 32), ExprInt(1, 32))],
+                         [(ExprId("R1", 32), ExprInt(8, 32))])
+
+        exec_instruction("SLL R1, R2",
+                         [(ExprId("R1", 32), ExprInt(0x80000000, 32)), (ExprId("R2", 32), ExprInt(1, 32))],
+                         [(ExprId("R1", 32), ExprInt(0, 32))])
+
+        # SLL Rn,imm5
+        exec_instruction("SLL R1, 1",
+                         [(ExprId("R1", 32), ExprInt(4, 32))],
+                         [(ExprId("R1", 32), ExprInt(8, 32))])
+
+    def test_sll3(self):
+        """Test SLL3 execution"""
+
+        # SLL3 R0,Rn,imm5
+        exec_instruction("SLL3 R0, R1, 2",
+                         [(ExprId("R1", 32), ExprInt(4, 32))],
+                         [(ExprId("R0", 32), ExprInt(16, 32))])
+
+        exec_instruction("SLL3 R0, R1, 2",
+                         [(ExprId("R1", 32), ExprInt(0xC0000000, 32))],
+                         [(ExprId("R0", 32), ExprInt(0, 32))])
+
+    def test_fsft(self):
+        """Test FSFT execution"""
+
+        # FSFT Rn,Rm
+        exec_instruction("FSFT R0, R1",
+                         [(ExprId("SAR", 32), ExprInt(0x00000001, 32)),
+                          (ExprId("R0", 32), ExprInt(0x00000001, 32)),
+                          (ExprId("R1", 32), ExprInt(0x80000000, 32))],
+                         [(ExprId("R0", 32), ExprInt(0x00000003, 32))])
+
+        exec_instruction("FSFT R0, R1",
+                         [(ExprId("SAR", 32), ExprInt(0x00000004, 32)),
+                          (ExprId("R0", 32), ExprInt(0xFFFFFFFF, 32)),
+                          (ExprId("R1", 32), ExprInt(0xF0000000, 32))],
+                         [(ExprId("R0", 32), ExprInt(0xFFFFFFFF, 32))])
+
+        exec_instruction("FSFT R0, R1",
+                         [(ExprId("SAR", 32), ExprInt(0x00000004, 32)),
+                          (ExprId("R0", 32), ExprInt(0xF0000000, 32)),
+                          (ExprId("R1", 32), ExprInt(0x0F000000, 32))],
+                         [(ExprId("R0", 32), ExprInt(0, 32))])
diff --git a/test/arch/mep/ir/ut_helpers_ir.py b/test/arch/mep/ir/ut_helpers_ir.py
new file mode 100644
index 00000000..fcf31764
--- /dev/null
+++ b/test/arch/mep/ir/ut_helpers_ir.py
@@ -0,0 +1,87 @@
+# Toshiba MeP-c4 - unit tests helpers
+# Guillaume Valadon <guillaume@valadon.net>
+
+from miasm2.arch.mep.arch import mn_mep
+from miasm2.arch.mep.sem import ir_mepb
+from miasm2.arch.mep.regs import regs_init
+
+from miasm2.ir.symbexec import SymbolicExecutionEngine
+from miasm2.core.locationdb import LocationDB
+from miasm2.core.utils import Disasm_Exception
+from miasm2.ir.ir import AssignBlock
+from miasm2.arch.mep.ira import ir_a_mepb
+from miasm2.expression.expression import ExprId, ExprInt, ExprOp, ExprMem, ExprAff, ExprLoc
+
+
+def exec_instruction(mn_str, init_values, results, index=0, offset=0):
+    """Symbolically execute an instruction and check the expected results."""
+
+    # Assemble and disassemble the instruction
+    instr = mn_mep.fromstring(mn_str, "b")
+    instr.mode = "b"
+    mn_bin = mn_mep.asm(instr)[index]
+    try:
+        instr = mn_mep.dis(mn_bin, "b")
+    except Disasm_Exception:
+        assert(False)  # miasm don't know what to do
+
+    # Specify the instruction offset and compute the destination label
+    instr.offset = offset
+    loc_db = LocationDB()
+    if instr.dstflow():
+        instr.dstflow2label(loc_db)
+
+    # Get the IR
+    im = ir_mepb(loc_db)
+    iir, eiir = im.get_ir(instr)
+
+    # Filter out IRDst
+    iir = [ir for ir in iir if not (isinstance(ir, ExprAff) and
+                                    isinstance(ir.dst, ExprId) and
+                                    ir.dst.name == "IRDst")]
+
+    # Prepare symbolic execution
+    sb = SymbolicExecutionEngine(ir_a_mepb(loc_db), regs_init)
+
+    # Assign int values before symbolic evaluation
+    for expr_id, expr_value in init_values:
+        sb.symbols[expr_id] = expr_value
+
+    # Execute the IR
+    ab = AssignBlock(iir)
+    sb.eval_updt_assignblk(ab)
+
+    # Check if expected expr_id were modified
+    matched_results = 0
+    for expr_id, expr_value in results:
+
+        result = sb.eval_expr(expr_id)
+        if isinstance(result, ExprLoc):
+            addr = loc_db.get_location_offset(result.loc_key)
+            if expr_value.arg == addr:
+                matched_results += 1
+                continue
+        elif result == expr_value:
+            matched_results += 1
+            continue
+
+    # Ensure that all expected results were verified
+    if len(results) is not matched_results:
+        print "Expected:", results
+        print "Modified:", [r for r in sb.modified(mems=False)]
+        assert(False)
+
+
+def launch_tests(obj):
+    """Call test methods by name"""
+
+    test_methods = [name for name in dir(obj) if name.startswith("test")]
+
+    for method in test_methods:
+        print method
+        try:
+            getattr(obj, method)()
+        except AttributeError as e:
+            print "Method not found: %s" % method
+            assert(False)
+        print '-' * 42