diff options
Diffstat (limited to 'test/arch/msp430')
| -rw-r--r-- | test/arch/msp430/arch.py | 110 | ||||
| -rw-r--r-- | test/arch/msp430/sem.py | 143 |
2 files changed, 253 insertions, 0 deletions
diff --git a/test/arch/msp430/arch.py b/test/arch/msp430/arch.py new file mode 100644 index 00000000..f3e82955 --- /dev/null +++ b/test/arch/msp430/arch.py @@ -0,0 +1,110 @@ + +import os +import time +from miasm2.arch.msp430.arch import * + +filename = os.environ.get('PYTHONSTARTUP') +if filename and os.path.isfile(filename): + execfile(filename) + + +def h2i(s): + return s.replace(' ', '').decode('hex') + + +def u16swap(i): + return struct.unpack('<H', struct.pack('>H', i))[0] + + +reg_tests_msp = [ + ("4456 mov.w SP, R4", + "0441"), + ("4d4f mov.b R13, R15", + "4f4d"), + ("49fe mov.w @R13, R9", + "294d"), + ("4982 mov.w 0x10(R14), R13", + "1d4e1000"), + ("4972 mov.w R14, 0x0(SP)", + "814e0000"), + ("46de mov.w 0x2(R14), 0x2(R13)", + "9d4e02000200"), + ("469e mov.w @0x2400, R11", + "1b420024"), + ("4c14 mov.w 0x4A96, R15", + "3f40964a"), + ("47c0 mov.w 0x1, R8", + "1843"), + ("48fc mov.w 0x2, R10", + "2a43"), + ("44fe mov.w 0x4, R7", + "2742"), + ("4a28 mov.w 0xFFFF, R15", + "3f43"), + ("4416 mov.w R5, @0x15C", + "82455c01"), + + ("4a22 add.w R11, R15", + "0f5b"), + ("448e sub.w R15, SP", + "018f"), + ("4474 cmp.b @R15, R13", + "6d9f"), + ("46a8 bit.w 0x1, R13", + "1db3"), + ("440a bis.w 0x5A08, R5", + "35d0085a"), + ("4c1a xor.w R15, R10", + "0aef"), + ("4408 and.b 0xFF, R5", + "75f3"), + + + ("4cf0 push.w SR", + "0212"), + ("4d6e push.w 0x0", + "0312"), + ("45dc push.w 0x2(R11)", + "1b120200"), + ("49cc push.w R11", + "0b12"), + + ("443a call 0x4B66", + "b012664b"), + + ("4442 jmp 0xFFFA", + "fd3f"), + ("4422 jnz 0xFFF2", + "f923"), + + ("xxxx mov.b @R13+, 0x0(R14)", + "fe4d0000"), + + ("4a36 mov.w @SP+, PC", + "3041"), + + +] + +ts = time.time() + +for s, l in reg_tests_msp: + print "-" * 80 + s = s[8:] + b = h2i((l)) + print repr(b) + mn = mn_msp430.dis(b, None) + print [str(x) for x in mn.args] + print s + print mn + assert(str(mn) == s) + # print hex(b) + # print [str(x.get()) for x in mn.args] + l = mn_msp430.fromstring(s, None) + # print l + assert(str(l) == s) + a = mn_msp430.asm(l) + print [x for x in a] + print repr(b) + # print mn.args + assert(b in a) diff --git a/test/arch/msp430/sem.py b/test/arch/msp430/sem.py new file mode 100644 index 00000000..55da5d56 --- /dev/null +++ b/test/arch/msp430/sem.py @@ -0,0 +1,143 @@ +#!/usr/bin/env python +#-*- coding:utf-8 -*- + +import unittest +import logging + +from miasm2.ir.symbexec import symbexec +from miasm2.arch.msp430.arch import mn_msp430 as mn, mode_msp430 as mode +from miasm2.arch.msp430.sem import ir_msp430 as ir +from miasm2.arch.msp430.regs import * +from miasm2.expression.expression import * + +logging.getLogger('cpuhelper').setLevel(logging.ERROR) +EXCLUDE_REGS = set([res]) + + +def M(addr): + return ExprMem(ExprInt_fromsize(16, addr), 16) + + +def compute(asm, inputstate={}, debug=False): + sympool = dict(regs_init) + sympool.update({k: ExprInt_from(k, v) for k, v in inputstate.iteritems()}) + symexec = symbexec(mn, sympool) + instr = mn.fromstring(asm, mode) + code = mn.asm(instr)[0] + instr = mn.dis(code, mode) + instr.offset = inputstate.get(PC, 0) + interm = ir() + interm.add_instr(instr) + symexec.emul_ir_blocs(interm, instr.offset) + if debug: + for k, v in symexec.symbols.items(): + if regs_init.get(k, None) != v: + print k, v + return {k: v.arg.arg for k, v in symexec.symbols.items() + if k not in EXCLUDE_REGS and regs_init.get(k, None) != v} + + +class TestMSP430Semantic(unittest.TestCase): + + def test_ADD_W(self): + # Testing status flags + self.assertEqual(compute('add.w 0x0000, R4', {R4: 0x0001, }), { + R4: 0x0001, nf: 0, zf: 0, cf: 0, of: 0}) + self.assertEqual(compute('add.w 0x0000, R4', {R4: 0xFFFF, }), { + R4: 0xFFFF, nf: 1, zf: 0, cf: 0, of: 0}) + self.assertEqual(compute('add.w 0x0000, R4', {R4: 0x0000, }), { + R4: 0x0000, nf: 0, zf: 1, cf: 0, of: 0}) + self.assertEqual(compute('add.w 0x0002, R4', {R4: 0xFFFF, }), { + R4: 0x0001, nf: 0, zf: 0, cf: 1, of: 0}) + self.assertEqual(compute('add.w 0x7FFF, R4', {R4: 0x7FFF, }), { + R4: 0xFFFE, nf: 1, zf: 0, cf: 0, of: 1}) + self.assertEqual(compute('add.w 0x8001, R4', {R4: 0x8001, }), { + R4: 0x0002, nf: 0, zf: 0, cf: 1, of: 1}) + # Testing addressing mode + self.assertEqual(compute('add.w R5, R4', {R4: 0x1F53, R5: 0x28C4, }), { + R4: 0x4817, R5: 0x28C4, nf: 0, zf: 0, cf: 0, of: 0}) + self.assertEqual(compute('add.w @R5, R4', {R4: 0x1F53, R5: 0x28C4, M(0x28C4): 0, }), { + R4: 0x1F53, R5: 0x28C4, M(0x28C4): 0, nf: 0, zf: 0, cf: 0, of: 0}) + self.assertEqual(compute('add.w @R5+, R4', {R4: 0x1F53, R5: 0x28C4, M(0x28C4): 0, }), { + R4: 0x1F53, R5: 0x28C6, M(0x28C4): 0, nf: 0, zf: 0, cf: 0, of: 0}) + self.assertEqual(compute('add.w 1(R5), R4', {R4: 0x1F53, R5: 0x28C4, M(0x28C5): 0, }), { + R4: 0x1F53, R5: 0x28C4, M(0x28C5): 0, nf: 0, zf: 0, cf: 0, of: 0}) + self.assertEqual(compute('add.w @0x0000, R4', {R4: 0x1F53, M(0): 0x28C4, }), { + R4: 0x4817, M(0): 0x28C4, nf: 0, zf: 0, cf: 0, of: 0}) + self.assertEqual(compute('add.w 0x0000, R4', {R4: 0x1F53, }), { + R4: 0x1F53, nf: 0, zf: 0, cf: 0, of: 0}) + + def test_AND_B(self): + # Testing status flags + self.assertEqual(compute('and.b 0x0001, R4', {R4: 0x0001, }), { + R4: 0x0001, nf: 0, zf: 0, cf: 1, of: 0}) + self.assertEqual(compute('and.b 0xFFFF, R4', {R4: 0xFFFF, }), { + R4: 0x00FF, nf: 1, zf: 0, cf: 1, of: 0}) + self.assertEqual(compute('and.b 0x0000, R4', {R4: 0x0000, }), { + R4: 0x0000, nf: 0, zf: 1, cf: 0, of: 0}) + # Testing addressing mode + self.assertEqual(compute('and.b R5, R4', {R4: 0x1F53, R5: 0x38C4, }), { + R4: 0x0040, R5: 0x38C4, nf: 0, zf: 0, cf: 1, of: 0}) + self.assertEqual(compute('and.b @R5, R4', {R4: 0x1F53, R5: 0x38C4, M(0x38C4): 0, }), { + R4: 0x0000, R5: 0x38C4, M(0x38C4): 0, nf: 0, zf: 1, cf: 0, of: 0}) + self.assertEqual(compute('and.b @R5+, R4', {R4: 0x1F53, R5: 0x38C4, M(0x38C4): 0, }), { + R4: 0x0000, R5: 0x38C5, M(0x38C4): 0, nf: 0, zf: 1, cf: 0, of: 0}) + self.assertEqual(compute('and.b 1(R5), R4', {R4: 0x1F53, R5: 0x38C4, M(0x38C5): 1, }), { + R4: 0x0001, R5: 0x38C4, M(0x38C5): 1, nf: 0, zf: 0, cf: 1, of: 0}) + self.assertEqual(compute('and.b @0x0000, R4', {R4: 0x1F53, M(0): 0x38C4, }), { + R4: 0x0040, M(0): 0x38C4, nf: 0, zf: 0, cf: 1, of: 0}) + self.assertEqual(compute('and.b 0xFFFF, R4', {R4: 0x1F53, }), { + R4: 0x0053, nf: 0, zf: 0, cf: 1, of: 0}) + + def test_AND_W(self): + # Testing status flags + self.assertEqual(compute('and.w 0x0001, R4', {R4: 0x0001, }), { + R4: 0x0001, nf: 0, zf: 0, cf: 1, of: 0}) + self.assertEqual(compute('and.w 0xFFFF, R4', {R4: 0xFFFF, }), { + R4: 0xFFFF, nf: 1, zf: 0, cf: 1, of: 0}) + self.assertEqual(compute('and.w 0x0000, R4', {R4: 0x0000, }), { + R4: 0x0000, nf: 0, zf: 1, cf: 0, of: 0}) + # Testing addressing mode + self.assertEqual(compute('and.w R5, R4', {R4: 0x1F53, R5: 0x38C4, }), { + R4: 0x1840, R5: 0x38C4, nf: 0, zf: 0, cf: 1, of: 0}) + self.assertEqual(compute('and.w @R5, R4', {R4: 0x1F53, R5: 0x38C4, M(0x38C4): 0, }), { + R4: 0x0000, R5: 0x38C4, M(0x38C4): 0, nf: 0, zf: 1, cf: 0, of: 0}) + self.assertEqual(compute('and.w @R5+, R4', {R4: 0x1F53, R5: 0x38C4, M(0x38C4): 0, }), { + R4: 0x0000, R5: 0x38C6, M(0x38C4): 0, nf: 0, zf: 1, cf: 0, of: 0}) + self.assertEqual(compute('and.w 1(R5), R4', {R4: 0x1F53, R5: 0x38C4, M(0x38C5): 1, }), { + R4: 0x0001, R5: 0x38C4, M(0x38C5): 1, nf: 0, zf: 0, cf: 1, of: 0}) + self.assertEqual(compute('and.w @0x0000, R4', {R4: 0x1F53, M(0): 0x38C4, }), { + R4: 0x1840, M(0): 0x38C4, nf: 0, zf: 0, cf: 1, of: 0}) + self.assertEqual(compute('and.w 0xFFFF, R4', {R4: 0x1F53, }), { + R4: 0x1F53, nf: 0, zf: 0, cf: 1, of: 0}) + + def test_BIC_B(self): + # Testing addressing mode + self.assertEqual( + compute('bic.b 0x0000, R4', {R4: 0x1F53, }), {R4: 0x0053, }) + # self.assertEqual(compute('bic.b 0x0000, @R4', {R4:0x1F53,M(0x1F53):0x569D, }), {R4:0x1F53,M(0x1F53):0x38C4, }) + # self.assertEqual(compute('bic.b 0x38C4, @R4+', {R4:0x1F53,M(0x1F53):0x569D, }), {R4:0x1F55,M(0x1F53):0x38C4, }) + # self.assertEqual(compute('bic.b 0x38C4, 1(R4)', {R4:0x1F53,M(0x1F54):0x569D, }), {R4:0x1F53,M(0x1F54):0x5619, }) + # self.assertEqual(compute('bic.b 0x0000, @0x0000', { M(0x0000):0x569D, }), { M(0x0000):0x38C4, }) + # self.assertEqual(compute('bic.b 0x38C4, 0xFFFE', { + # }), { }) + + def test_CALL(self): + # Testing addressing mode + self.assertEqual(compute('call R4', {PC: 0x0100, SP: 0x0400, R4: 0x1F53, }), { + PC: 0x1F53, SP: 0x03FE, R4: 0x1F53, M(0x03FE): 0x102, }) + self.assertEqual(compute('call @R4', {PC: 0x0100, SP: 0x0400, R4: 0x1F53, M(0x1F53): 0x38C4, }), { + PC: 0x38C4, SP: 0x03FE, R4: 0x1F53, M(0x1F53): 0x38C4, M(0x03FE): 0x102, }) + self.assertEqual(compute('call @R4+', {PC: 0x0100, SP: 0x0400, R4: 0x1F53, M(0x1F53): 0x38C4, }), { + PC: 0x38C4, SP: 0x03FE, R4: 0x1F55, M(0x1F53): 0x38C4, M(0x03FE): 0x102, }) + self.assertEqual(compute('call 1(R4)', {PC: 0x0100, SP: 0x0400, R4: 0x1F53, M(0x1F54): 0x38C4, }), { + PC: 0x38C4, SP: 0x03FE, R4: 0x1F53, M(0x1F54): 0x38C4, M(0x03FE): 0x104, }) + self.assertEqual(compute('call @0x0000', {PC: 0x0100, SP: 0x0400, M(0x0000): 0x38C4, }), { + PC: 0x38C4, SP: 0x03FE, M(0x0000): 0x38C4, M(0x03FE): 0x104, }) + self.assertEqual(compute('call 0xFFFE', {PC: 0x0100, SP: 0x0400, }), { + PC: 0xFFFE, SP: 0x03FE, M(0x03FE): 0x104, }) + +if __name__ == '__main__': + testsuite = unittest.TestLoader().loadTestsFromTestCase(TestMSP430Semantic) + report = unittest.TextTestRunner(verbosity=2).run(testsuite) + exit(len(report.errors + report.failures)) |