diff options
Diffstat (limited to 'test/arch/x86/unit')
| -rw-r--r-- | test/arch/x86/unit/access_xmm.py | 4 | ||||
| -rw-r--r-- | test/arch/x86/unit/asm_test.py | 15 | ||||
| -rwxr-xr-x | test/arch/x86/unit/mn_pushpop.py | 24 | ||||
| -rw-r--r-- | test/arch/x86/unit/test_asm_x86_64.py | 10 |
4 files changed, 30 insertions, 23 deletions
diff --git a/test/arch/x86/unit/access_xmm.py b/test/arch/x86/unit/access_xmm.py index 65248b2e..c7ecfb1e 100644 --- a/test/arch/x86/unit/access_xmm.py +++ b/test/arch/x86/unit/access_xmm.py @@ -2,9 +2,11 @@ """Test getter and setter for XMM registers (128 bits)""" from miasm.analysis.machine import Machine +from miasm.core.locationdb import LocationDB # Jitter engine doesn't matter, use the always available 'python' one -myjit = Machine("x86_32").jitter("python") +loc_db = LocationDB() +myjit = Machine("x86_32").jitter(loc_db, "python") # Test basic access (get) assert myjit.cpu.XMM0 == 0 diff --git a/test/arch/x86/unit/asm_test.py b/test/arch/x86/unit/asm_test.py index 6e7c55e2..d3ecf660 100644 --- a/test/arch/x86/unit/asm_test.py +++ b/test/arch/x86/unit/asm_test.py @@ -11,15 +11,16 @@ from miasm.expression.expression import * from miasm.core import asmblock from miasm.loader.strpatchwork import StrPatchwork from miasm.analysis.machine import Machine +from miasm.core.locationdb import LocationDB from miasm.jitter.csts import * reg_and_id = dict(mn_x86.regs.all_regs_ids_byname) - class Asm_Test(object): run_addr = 0x0 def __init__(self, jitter_engine): - self.myjit = Machine(self.arch_name).jitter(jitter_engine) + self.loc_db = LocationDB() + self.myjit = Machine(self.arch_name).jitter(self.loc_db, jitter_engine) self.myjit.init_stack() def test_init(self): @@ -44,12 +45,11 @@ class Asm_Test(object): assert(self.myjit.pc == self.ret_addr) def asm(self): - blocks, loc_db = parse_asm.parse_txt(mn_x86, self.arch_attrib, self.TXT, - loc_db = self.myjit.ir_arch.loc_db) + blocks = parse_asm.parse_txt(mn_x86, self.arch_attrib, self.TXT, self.loc_db) # fix shellcode addr - loc_db.set_location_offset(loc_db.get_name_location("main"), 0x0) + self.loc_db.set_location_offset(self.loc_db.get_name_location("main"), 0x0) s = StrPatchwork() - patches = asmblock.asm_resolve_final(mn_x86, blocks, loc_db) + patches = asmblock.asm_resolve_final(mn_x86, blocks, self.loc_db) for offset, raw in viewitems(patches): s[offset] = raw @@ -77,7 +77,8 @@ class Asm_Test_16(Asm_Test): ret_addr = 0x1337 def __init__(self, jitter_engine): - self.myjit = Machine(self.arch_name).jitter(jitter_engine) + self.loc_db = LocationDB() + self.myjit = Machine(self.arch_name).jitter(self.loc_db, jitter_engine) self.myjit.stack_base = 0x1000 self.myjit.stack_size = 0x1000 self.myjit.init_stack() diff --git a/test/arch/x86/unit/mn_pushpop.py b/test/arch/x86/unit/mn_pushpop.py index 6dc37b74..c13f5989 100755 --- a/test/arch/x86/unit/mn_pushpop.py +++ b/test/arch/x86/unit/mn_pushpop.py @@ -21,7 +21,7 @@ class Test_PUSHAD_32(Asm_Test_32): MYSTRING = "test pushad 32" def prepare(self): - self.myjit.ir_arch.loc_db.add_location("lbl_ret", self.ret_addr) + self.loc_db.add_location("lbl_ret", self.ret_addr) def test_init(self): init_regs(self) @@ -48,7 +48,7 @@ class Test_PUSHA_32(Asm_Test_32): MYSTRING = "test pusha 32" def prepare(self): - self.myjit.ir_arch.loc_db.add_location("lbl_ret", self.ret_addr) + self.loc_db.add_location("lbl_ret", self.ret_addr) def test_init(self): init_regs(self) @@ -75,7 +75,7 @@ class Test_PUSHA_16(Asm_Test_16): MYSTRING = "test pusha 16" def prepare(self): - self.myjit.ir_arch.loc_db.add_location("lbl_ret", self.ret_addr) + self.loc_db.add_location("lbl_ret", self.ret_addr) def test_init(self): init_regs(self) @@ -102,7 +102,7 @@ class Test_PUSHAD_16(Asm_Test_16): MYSTRING = "test pushad 16" def prepare(self): - self.myjit.ir_arch.loc_db.add_location("lbl_ret", self.ret_addr) + self.loc_db.add_location("lbl_ret", self.ret_addr) def test_init(self): init_regs(self) @@ -129,7 +129,7 @@ class Test_PUSH_mode32_32(Asm_Test_32): MYSTRING = "test push mode32 32" def prepare(self): - self.myjit.ir_arch.loc_db.add_location("lbl_ret", self.ret_addr) + self.loc_db.add_location("lbl_ret", self.ret_addr) def test_init(self): init_regs(self) @@ -152,7 +152,7 @@ class Test_PUSH_mode32_16(Asm_Test_32): MYSTRING = "test push mode32 16" def prepare(self): - self.myjit.ir_arch.loc_db.add_location("lbl_ret", self.ret_addr) + self.loc_db.add_location("lbl_ret", self.ret_addr) def test_init(self): init_regs(self) @@ -175,7 +175,7 @@ class Test_PUSH_mode16_16(Asm_Test_16): MYSTRING = "test push mode16 16" def prepare(self): - self.myjit.ir_arch.loc_db.add_location("lbl_ret", self.ret_addr) + self.loc_db.add_location("lbl_ret", self.ret_addr) def test_init(self): init_regs(self) @@ -198,7 +198,7 @@ class Test_PUSH_mode16_32(Asm_Test_16): MYSTRING = "test push mode16 32" def prepare(self): - self.myjit.ir_arch.loc_db.add_location("lbl_ret", self.ret_addr) + self.loc_db.add_location("lbl_ret", self.ret_addr) def test_init(self): init_regs(self) @@ -221,7 +221,7 @@ class Test_POP_mode32_32(Asm_Test_32): MYSTRING = "test pop mode32 32" def prepare(self): - self.myjit.ir_arch.loc_db.add_location("lbl_ret", self.ret_addr) + self.loc_db.add_location("lbl_ret", self.ret_addr) def test_init(self): self.value = 0x11223344 @@ -243,7 +243,7 @@ class Test_POP_mode32_16(Asm_Test_32): MYSTRING = "test pop mode32 16" def prepare(self): - self.myjit.ir_arch.loc_db.add_location("lbl_ret", self.ret_addr) + self.loc_db.add_location("lbl_ret", self.ret_addr) def test_init(self): self.value = 0x1122 @@ -265,7 +265,7 @@ class Test_POP_mode16_16(Asm_Test_16): MYSTRING = "test pop mode16 16" def prepare(self): - self.myjit.ir_arch.loc_db.add_location("lbl_ret", self.ret_addr) + self.loc_db.add_location("lbl_ret", self.ret_addr) def test_init(self): self.value = 0x1122 @@ -287,7 +287,7 @@ class Test_POP_mode16_32(Asm_Test_16): MYSTRING = "test pop mode16 32" def prepare(self): - self.myjit.ir_arch.loc_db.add_location("lbl_ret", self.ret_addr) + self.loc_db.add_location("lbl_ret", self.ret_addr) def test_init(self): self.value = 0x11223344 diff --git a/test/arch/x86/unit/test_asm_x86_64.py b/test/arch/x86/unit/test_asm_x86_64.py index e23f9a19..e1d99ec1 100644 --- a/test/arch/x86/unit/test_asm_x86_64.py +++ b/test/arch/x86/unit/test_asm_x86_64.py @@ -2,11 +2,13 @@ from miasm.core import asmblock from miasm.arch.x86 import arch from miasm.core import parse_asm from miasm.core.interval import interval +from miasm.core.locationdb import LocationDB my_mn = arch.mn_x86 +loc_db = LocationDB() - -asmcfg, loc_db = parse_asm.parse_txt(my_mn, 64, r''' +asmcfg = parse_asm.parse_txt( + my_mn, 64, r''' main: PUSH RBP MOV RBP, RSP @@ -18,7 +20,9 @@ end: POP RBP RET -''') +''', + loc_db +) loc_db.set_location_offset(loc_db.get_name_location("main"), 0x100001000) dst_interval = interval([(0x100001000, 0x100002000)]) |