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-rw-r--r--test/arch/x86/arch.py13
-rwxr-xr-xtest/arch/x86/sem.py35
-rw-r--r--test/arch/x86/unit/access_xmm.py16
-rw-r--r--test/arch/x86/unit/asm_test.py15
-rw-r--r--test/arch/x86/unit/mn_cdq.py38
-rwxr-xr-xtest/arch/x86/unit/mn_int.py10
-rwxr-xr-xtest/arch/x86/unit/mn_pushpop.py24
-rwxr-xr-xtest/arch/x86/unit/mn_strings.py9
8 files changed, 86 insertions, 74 deletions
diff --git a/test/arch/x86/arch.py b/test/arch/x86/arch.py
index 05b31815..43e973e1 100644
--- a/test/arch/x86/arch.py
+++ b/test/arch/x86/arch.py
@@ -5,9 +5,9 @@ from miasm2.arch.x86.arch import mn_x86, deref_mem_ad, \
     base_expr, rmarg, print_size
 from miasm2.arch.x86.sem import ir_x86_16, ir_x86_32, ir_x86_64
 from miasm2.core.bin_stream import bin_stream_str
-from miasm2.core.asmblock import AsmSymbolPool
+from miasm2.core.locationdb import LocationDB
 
-symbol_pool = AsmSymbolPool()
+loc_db = LocationDB()
 
 mylabel16 = m2_expr.ExprId('mylabel16', 16)
 mylabel32 = m2_expr.ExprId('mylabel32', 32)
@@ -3062,17 +3062,13 @@ for mode, s, l, in reg_tests:
     print s
     print mn
     assert(str(mn).strip() == s)
-    # print hex(b)
-    # print [str(x.get()) for x in mn.args]
     print 'fromstring', repr(s)
-    l = mn_x86.fromstring(s, symbol_pool, mode)
-    # print l
+    l = mn_x86.fromstring(s, loc_db, mode)
     print 'str args', [(str(x), x.size) for x in l.args]
     assert(str(l).strip(' ') == s)
     a = mn_x86.asm(l)
     print 'asm result', [x for x in a]
     print repr(b)
-    # test_file[mode[0]].write(b)
 
     for x in a:
         print "BYTES", repr(x)
@@ -3086,7 +3082,6 @@ for mode, s, l, in reg_tests:
         assert(str(rl).strip(' ') == s)
     print repr(b), a
     assert(b in a)
-    # print mn.args
 print 'TEST time', time.time() - ts
 
 
@@ -3118,9 +3113,7 @@ def profile_dis(o):
     print 'instr per sec:', instr_num / (time.time() - ts)
 
 import cProfile
-# cProfile.run(r'mn_x86.dis("\x81\x54\x18\xfe\x44\x33\x22\x11", m32)')
 cProfile.run('profile_dis(o)')
-# profile_dis(o)
 
 # Test instruction representation with prefix
 instr_bytes = '\x65\xc7\x00\x09\x00\x00\x00'
diff --git a/test/arch/x86/sem.py b/test/arch/x86/sem.py
index b3b7e940..0783089d 100755
--- a/test/arch/x86/sem.py
+++ b/test/arch/x86/sem.py
@@ -12,24 +12,23 @@ from miasm2.arch.x86.arch import mn_x86 as mn
 from miasm2.arch.x86.sem import ir_x86_32 as ir_32, ir_x86_64 as ir_64
 from miasm2.arch.x86.regs import *
 from miasm2.expression.expression import *
-from miasm2.expression.simplifications      import expr_simp
+from miasm2.expression.simplifications import expr_simp
 from miasm2.core import parse_asm, asmblock
-from miasm2.core.asmblock import AsmSymbolPool
+from miasm2.core.locationdb import LocationDB
 
 
 logging.getLogger('cpuhelper').setLevel(logging.ERROR)
 EXCLUDE_REGS = set([ir_32().IRDst, ir_64().IRDst])
 
-symbol_pool = AsmSymbolPool()
 
 m32 = 32
 m64 = 64
 
-def symb_exec(interm, inputstate, debug):
+def symb_exec(lbl, ir_arch, ircfg, inputstate, debug):
     sympool = dict(regs_init)
     sympool.update(inputstate)
-    symexec = SymbolicExecutionEngine(interm, sympool)
-    symexec.run_at(0)
+    symexec = SymbolicExecutionEngine(ir_arch, sympool)
+    symexec.run_at(ircfg, lbl)
     if debug:
         for k, v in symexec.symbols.items():
             if regs_init.get(k, None) != v:
@@ -38,23 +37,25 @@ def symb_exec(interm, inputstate, debug):
             if k not in EXCLUDE_REGS and regs_init.get(k, None) != v}
 
 def compute(ir, mode, asm, inputstate={}, debug=False):
-    instr = mn.fromstring(asm, symbol_pool, mode)
+    loc_db = LocationDB()
+    instr = mn.fromstring(asm, loc_db, mode)
     code = mn.asm(instr)[0]
     instr = mn.dis(code, mode)
     instr.offset = inputstate.get(EIP, 0)
-    interm = ir()
-    interm.add_instr(instr)
-    return symb_exec(interm, inputstate, debug)
+    ir_arch = ir(loc_db)
+    ircfg = ir_arch.new_ircfg()
+    lbl = ir_arch.add_instr_to_ircfg(instr, ircfg)
+    return symb_exec(lbl, ir_arch, ircfg, inputstate, debug)
 
 
 def compute_txt(ir, mode, txt, inputstate={}, debug=False):
-    blocks, symbol_pool = parse_asm.parse_txt(mn, mode, txt)
-    symbol_pool.set_offset(symbol_pool.getby_name("main"), 0x0)
-    patches = asmblock.asm_resolve_final(mn, blocks, symbol_pool)
-    interm = ir(symbol_pool)
-    for bbl in blocks:
-        interm.add_block(bbl)
-    return symb_exec(interm, inputstate, debug)
+    asmcfg, loc_db = parse_asm.parse_txt(mn, mode, txt)
+    loc_db.set_location_offset(loc_db.get_name_location("main"), 0x0)
+    patches = asmblock.asm_resolve_final(mn, asmcfg, loc_db)
+    ir_arch = ir(loc_db)
+    lbl = loc_db.get_name_location("main")
+    ircfg = ir_arch.new_ircfg_from_asmcfg(asmcfg)
+    return symb_exec(lbl, ir_arch, ircfg, inputstate, debug)
 
 op_add = lambda a, b: a+b
 op_sub = lambda a, b: a-b
diff --git a/test/arch/x86/unit/access_xmm.py b/test/arch/x86/unit/access_xmm.py
new file mode 100644
index 00000000..950c8b56
--- /dev/null
+++ b/test/arch/x86/unit/access_xmm.py
@@ -0,0 +1,16 @@
+#! /usr/bin/env python2
+"""Test getter and setter for XMM registers (128 bits)"""
+
+from miasm2.analysis.machine import Machine
+
+# Jitter engine doesn't matter, use the always available 'python' one
+myjit = Machine("x86_32").jitter("python")
+
+# Test basic access (get)
+assert myjit.cpu.XMM0 == 0
+
+# Test set
+myjit.cpu.XMM1 = 0x00112233445566778899aabbccddeeffL
+
+# Ensure set has been correctly handled
+assert myjit.cpu.XMM1 == 0x00112233445566778899aabbccddeeffL
diff --git a/test/arch/x86/unit/asm_test.py b/test/arch/x86/unit/asm_test.py
index 961967f9..91da1942 100644
--- a/test/arch/x86/unit/asm_test.py
+++ b/test/arch/x86/unit/asm_test.py
@@ -18,9 +18,6 @@ class Asm_Test(object):
         self.myjit = Machine(self.arch_name).jitter(jitter_engine)
         self.myjit.init_stack()
 
-        self.myjit.jit.log_regs = False
-        self.myjit.jit.log_mn = False
-
     def test_init(self):
         pass
 
@@ -43,12 +40,12 @@ class Asm_Test(object):
         assert(self.myjit.pc == self.ret_addr)
 
     def asm(self):
-        blocks, symbol_pool = parse_asm.parse_txt(mn_x86, self.arch_attrib, self.TXT,
-                                                  symbol_pool = self.myjit.ir_arch.symbol_pool)
+        blocks, loc_db = parse_asm.parse_txt(mn_x86, self.arch_attrib, self.TXT,
+                                                  loc_db = self.myjit.ir_arch.loc_db)
         # fix shellcode addr
-        symbol_pool.set_offset(symbol_pool.getby_name("main"), 0x0)
+        loc_db.set_location_offset(loc_db.get_name_location("main"), 0x0)
         s = StrPatchwork()
-        patches = asmblock.asm_resolve_final(mn_x86, blocks, symbol_pool)
+        patches = asmblock.asm_resolve_final(mn_x86, blocks, loc_db)
         for offset, raw in patches.items():
             s[offset] = raw
 
@@ -81,10 +78,6 @@ class Asm_Test_16(Asm_Test):
         self.myjit.stack_size = 0x1000
         self.myjit.init_stack()
 
-        self.myjit.jit.log_regs = False
-        self.myjit.jit.log_mn = False
-
-
     def init_machine(self):
         self.myjit.vm.add_memory_page(self.run_addr, PAGE_READ | PAGE_WRITE, self.assembly)
         self.myjit.push_uint16_t(self.ret_addr)
diff --git a/test/arch/x86/unit/mn_cdq.py b/test/arch/x86/unit/mn_cdq.py
index b6abc781..947b40bb 100644
--- a/test/arch/x86/unit/mn_cdq.py
+++ b/test/arch/x86/unit/mn_cdq.py
@@ -10,7 +10,7 @@ class Test_CBW_16(Asm_Test_16):
     MYSTRING = "test CBW 16"
 
     def prepare(self):
-        self.myjit.ir_arch.symbol_pool.add_label("lbl_ret", self.ret_addr)
+        self.myjit.ir_arch.loc_db.add_location("lbl_ret", self.ret_addr)
 
     def test_init(self):
         self.myjit.cpu.EAX = 0x87654321
@@ -31,7 +31,7 @@ class Test_CBW_16_signed(Asm_Test_16):
     MYSTRING = "test CBW 16 signed"
 
     def prepare(self):
-        self.myjit.ir_arch.symbol_pool.add_label("lbl_ret", self.ret_addr)
+        self.myjit.ir_arch.loc_db.add_location("lbl_ret", self.ret_addr)
 
     def test_init(self):
         self.myjit.cpu.EAX = 0x87654381
@@ -52,7 +52,7 @@ class Test_CBW_32(Asm_Test_32):
     MYSTRING = "test CBW 32"
 
     def prepare(self):
-        self.myjit.ir_arch.symbol_pool.add_label("lbl_ret", self.ret_addr)
+        self.myjit.ir_arch.loc_db.add_location("lbl_ret", self.ret_addr)
 
     def test_init(self):
         self.myjit.cpu.EAX = 0x87654321
@@ -73,7 +73,7 @@ class Test_CBW_32_signed(Asm_Test_32):
     MYSTRING = "test CBW 32 signed"
 
     def prepare(self):
-        self.myjit.ir_arch.symbol_pool.add_label("lbl_ret", self.ret_addr)
+        self.myjit.ir_arch.loc_db.add_location("lbl_ret", self.ret_addr)
 
     def test_init(self):
         self.myjit.cpu.EAX = 0x87654381
@@ -94,7 +94,7 @@ class Test_CDQ_32(Asm_Test_32):
     MYSTRING = "test cdq 32"
 
     def prepare(self):
-        self.myjit.ir_arch.symbol_pool.add_label("lbl_ret", self.ret_addr)
+        self.myjit.ir_arch.loc_db.add_location("lbl_ret", self.ret_addr)
 
     def test_init(self):
         self.myjit.cpu.EAX = 0x77654321
@@ -115,7 +115,7 @@ class Test_CDQ_32_signed(Asm_Test_32):
     MYSTRING = "test cdq 32 signed"
 
     def prepare(self):
-        self.myjit.ir_arch.symbol_pool.add_label("lbl_ret", self.ret_addr)
+        self.myjit.ir_arch.loc_db.add_location("lbl_ret", self.ret_addr)
 
     def test_init(self):
         self.myjit.cpu.EAX = 0x87654321
@@ -136,7 +136,7 @@ class Test_CDQ_64(Asm_Test_64):
     MYSTRING = "test cdq 64"
 
     def prepare(self):
-        self.myjit.ir_arch.symbol_pool.add_label("lbl_ret", self.ret_addr)
+        self.myjit.ir_arch.loc_db.add_location("lbl_ret", self.ret_addr)
 
     def test_init(self):
         self.myjit.cpu.RAX = 0x1234567877654321
@@ -157,7 +157,7 @@ class Test_CDQ_64_signed(Asm_Test_64):
     MYSTRING = "test cdq 64 signed"
 
     def prepare(self):
-        self.myjit.ir_arch.symbol_pool.add_label("lbl_ret", self.ret_addr)
+        self.myjit.ir_arch.loc_db.add_location("lbl_ret", self.ret_addr)
 
     def test_init(self):
         self.myjit.cpu.RAX = 0x1234567887654321
@@ -178,7 +178,7 @@ class Test_CDQE_64(Asm_Test_64):
     MYSTRING = "test cdq 64"
 
     def prepare(self):
-        self.myjit.ir_arch.symbol_pool.add_label("lbl_ret", self.ret_addr)
+        self.myjit.ir_arch.loc_db.add_location("lbl_ret", self.ret_addr)
 
     def test_init(self):
         self.myjit.cpu.RAX = 0x1234567877654321
@@ -199,7 +199,7 @@ class Test_CDQE_64_signed(Asm_Test_64):
     MYSTRING = "test cdq 64 signed"
 
     def prepare(self):
-        self.myjit.ir_arch.symbol_pool.add_label("lbl_ret", self.ret_addr)
+        self.myjit.ir_arch.loc_db.add_location("lbl_ret", self.ret_addr)
 
     def test_init(self):
         self.myjit.cpu.RAX = 0x1234567887654321
@@ -220,7 +220,7 @@ class Test_CWD_32(Asm_Test_32):
     MYSTRING = "test cdq 32"
 
     def prepare(self):
-        self.myjit.ir_arch.symbol_pool.add_label("lbl_ret", self.ret_addr)
+        self.myjit.ir_arch.loc_db.add_location("lbl_ret", self.ret_addr)
 
     def test_init(self):
         self.myjit.cpu.EAX = 0x87654321
@@ -241,7 +241,7 @@ class Test_CWD_32_signed(Asm_Test_32):
     MYSTRING = "test cdq 32"
 
     def prepare(self):
-        self.myjit.ir_arch.symbol_pool.add_label("lbl_ret", self.ret_addr)
+        self.myjit.ir_arch.loc_db.add_location("lbl_ret", self.ret_addr)
 
     def test_init(self):
         self.myjit.cpu.EAX = 0x87658321
@@ -262,7 +262,7 @@ class Test_CWD_32(Asm_Test_32):
     MYSTRING = "test cdq 32"
 
     def prepare(self):
-        self.myjit.ir_arch.symbol_pool.add_label("lbl_ret", self.ret_addr)
+        self.myjit.ir_arch.loc_db.add_location("lbl_ret", self.ret_addr)
 
     def test_init(self):
         self.myjit.cpu.EAX = 0x87654321
@@ -283,7 +283,7 @@ class Test_CWDE_32(Asm_Test_32):
     MYSTRING = "test cwde 32"
 
     def prepare(self):
-        self.myjit.ir_arch.symbol_pool.add_label("lbl_ret", self.ret_addr)
+        self.myjit.ir_arch.loc_db.add_location("lbl_ret", self.ret_addr)
 
     def test_init(self):
         self.myjit.cpu.EAX = 0x87654321
@@ -304,7 +304,7 @@ class Test_CWDE_32_signed(Asm_Test_32):
     MYSTRING = "test cwde 32 signed"
 
     def prepare(self):
-        self.myjit.ir_arch.symbol_pool.add_label("lbl_ret", self.ret_addr)
+        self.myjit.ir_arch.loc_db.add_location("lbl_ret", self.ret_addr)
 
     def test_init(self):
         self.myjit.cpu.RAX = 0x87658321
@@ -325,7 +325,7 @@ class Test_CWDE_64(Asm_Test_64):
     MYSTRING = "test cwde 64"
 
     def prepare(self):
-        self.myjit.ir_arch.symbol_pool.add_label("lbl_ret", self.ret_addr)
+        self.myjit.ir_arch.loc_db.add_location("lbl_ret", self.ret_addr)
 
     def test_init(self):
         self.myjit.cpu.RAX = 0x1234567887654321
@@ -346,7 +346,7 @@ class Test_CWDE_64_signed(Asm_Test_64):
     MYSTRING = "test cwde 64 signed"
 
     def prepare(self):
-        self.myjit.ir_arch.symbol_pool.add_label("lbl_ret", self.ret_addr)
+        self.myjit.ir_arch.loc_db.add_location("lbl_ret", self.ret_addr)
 
     def test_init(self):
         self.myjit.cpu.RAX = 0x1234567887658321
@@ -367,7 +367,7 @@ class Test_CQO_64(Asm_Test_64):
     MYSTRING = "test cwde 64"
 
     def prepare(self):
-        self.myjit.ir_arch.symbol_pool.add_label("lbl_ret", self.ret_addr)
+        self.myjit.ir_arch.loc_db.add_location("lbl_ret", self.ret_addr)
 
     def test_init(self):
         self.myjit.cpu.RAX = 0x1234567887654321
@@ -388,7 +388,7 @@ class Test_CQO_64_signed(Asm_Test_64):
     MYSTRING = "test cwde 64 signed"
 
     def prepare(self):
-        self.myjit.ir_arch.symbol_pool.add_label("lbl_ret", self.ret_addr)
+        self.myjit.ir_arch.loc_db.add_location("lbl_ret", self.ret_addr)
 
     def test_init(self):
         self.myjit.cpu.RAX = 0x8234567887658321
diff --git a/test/arch/x86/unit/mn_int.py b/test/arch/x86/unit/mn_int.py
index 09792371..efacb105 100755
--- a/test/arch/x86/unit/mn_int.py
+++ b/test/arch/x86/unit/mn_int.py
@@ -8,12 +8,18 @@ from asm_test import Asm_Test_32
 class Test_INT(Asm_Test_32):
     TXT = '''
     main:
+       MOV ECX, 0x10
+    loop:
        INT 0x42
+       DEC ECX
+       JNZ loop
+    ret:
        RET
     '''
 
     def set_int_num(self, jitter):
-        self.int_num = jitter.cpu.get_interrupt_num()
+        assert jitter.cpu.get_interrupt_num() == 0x42
+        self.int_num += 1
         jitter.cpu.set_exception(0)
         return True
 
@@ -24,7 +30,7 @@ class Test_INT(Asm_Test_32):
                                          self.set_int_num)
 
     def check(self):
-        assert self.int_num == 0x42
+        assert self.int_num == 0x10
         self.myjit.cpu.set_interrupt_num(14)
         assert self.myjit.cpu.get_interrupt_num() == 14
 
diff --git a/test/arch/x86/unit/mn_pushpop.py b/test/arch/x86/unit/mn_pushpop.py
index 7ac400c0..6e9005ca 100755
--- a/test/arch/x86/unit/mn_pushpop.py
+++ b/test/arch/x86/unit/mn_pushpop.py
@@ -21,7 +21,7 @@ class Test_PUSHAD_32(Asm_Test_32):
     MYSTRING = "test pushad 32"
 
     def prepare(self):
-        self.myjit.ir_arch.symbol_pool.add_label("lbl_ret", self.ret_addr)
+        self.myjit.ir_arch.loc_db.add_location("lbl_ret", self.ret_addr)
 
     def test_init(self):
         init_regs(self)
@@ -48,7 +48,7 @@ class Test_PUSHA_32(Asm_Test_32):
     MYSTRING = "test pusha 32"
 
     def prepare(self):
-        self.myjit.ir_arch.symbol_pool.add_label("lbl_ret", self.ret_addr)
+        self.myjit.ir_arch.loc_db.add_location("lbl_ret", self.ret_addr)
 
     def test_init(self):
         init_regs(self)
@@ -75,7 +75,7 @@ class Test_PUSHA_16(Asm_Test_16):
     MYSTRING = "test pusha 16"
 
     def prepare(self):
-        self.myjit.ir_arch.symbol_pool.add_label("lbl_ret", self.ret_addr)
+        self.myjit.ir_arch.loc_db.add_location("lbl_ret", self.ret_addr)
 
     def test_init(self):
         init_regs(self)
@@ -102,7 +102,7 @@ class Test_PUSHAD_16(Asm_Test_16):
     MYSTRING = "test pushad 16"
 
     def prepare(self):
-        self.myjit.ir_arch.symbol_pool.add_label("lbl_ret", self.ret_addr)
+        self.myjit.ir_arch.loc_db.add_location("lbl_ret", self.ret_addr)
 
     def test_init(self):
         init_regs(self)
@@ -129,7 +129,7 @@ class Test_PUSH_mode32_32(Asm_Test_32):
     MYSTRING = "test push mode32 32"
 
     def prepare(self):
-        self.myjit.ir_arch.symbol_pool.add_label("lbl_ret", self.ret_addr)
+        self.myjit.ir_arch.loc_db.add_location("lbl_ret", self.ret_addr)
 
     def test_init(self):
         init_regs(self)
@@ -152,7 +152,7 @@ class Test_PUSH_mode32_16(Asm_Test_32):
     MYSTRING = "test push mode32 16"
 
     def prepare(self):
-        self.myjit.ir_arch.symbol_pool.add_label("lbl_ret", self.ret_addr)
+        self.myjit.ir_arch.loc_db.add_location("lbl_ret", self.ret_addr)
 
     def test_init(self):
         init_regs(self)
@@ -175,7 +175,7 @@ class Test_PUSH_mode16_16(Asm_Test_16):
     MYSTRING = "test push mode16 16"
 
     def prepare(self):
-        self.myjit.ir_arch.symbol_pool.add_label("lbl_ret", self.ret_addr)
+        self.myjit.ir_arch.loc_db.add_location("lbl_ret", self.ret_addr)
 
     def test_init(self):
         init_regs(self)
@@ -198,7 +198,7 @@ class Test_PUSH_mode16_32(Asm_Test_16):
     MYSTRING = "test push mode16 32"
 
     def prepare(self):
-        self.myjit.ir_arch.symbol_pool.add_label("lbl_ret", self.ret_addr)
+        self.myjit.ir_arch.loc_db.add_location("lbl_ret", self.ret_addr)
 
     def test_init(self):
         init_regs(self)
@@ -221,7 +221,7 @@ class Test_POP_mode32_32(Asm_Test_32):
     MYSTRING = "test pop mode32 32"
 
     def prepare(self):
-        self.myjit.ir_arch.symbol_pool.add_label("lbl_ret", self.ret_addr)
+        self.myjit.ir_arch.loc_db.add_location("lbl_ret", self.ret_addr)
 
     def test_init(self):
         self.value = 0x11223344
@@ -243,7 +243,7 @@ class Test_POP_mode32_16(Asm_Test_32):
     MYSTRING = "test pop mode32 16"
 
     def prepare(self):
-        self.myjit.ir_arch.symbol_pool.add_label("lbl_ret", self.ret_addr)
+        self.myjit.ir_arch.loc_db.add_location("lbl_ret", self.ret_addr)
 
     def test_init(self):
         self.value = 0x1122
@@ -265,7 +265,7 @@ class Test_POP_mode16_16(Asm_Test_16):
     MYSTRING = "test pop mode16 16"
 
     def prepare(self):
-        self.myjit.ir_arch.symbol_pool.add_label("lbl_ret", self.ret_addr)
+        self.myjit.ir_arch.loc_db.add_location("lbl_ret", self.ret_addr)
 
     def test_init(self):
         self.value = 0x1122
@@ -287,7 +287,7 @@ class Test_POP_mode16_32(Asm_Test_16):
     MYSTRING = "test pop mode16 32"
 
     def prepare(self):
-        self.myjit.ir_arch.symbol_pool.add_label("lbl_ret", self.ret_addr)
+        self.myjit.ir_arch.loc_db.add_location("lbl_ret", self.ret_addr)
 
     def test_init(self):
         self.value = 0x11223344
diff --git a/test/arch/x86/unit/mn_strings.py b/test/arch/x86/unit/mn_strings.py
index 3cb70e2a..8ca148e5 100755
--- a/test/arch/x86/unit/mn_strings.py
+++ b/test/arch/x86/unit/mn_strings.py
@@ -21,7 +21,8 @@ class Test_SCAS(Asm_Test_32):
 
     def check(self):
         assert(self.myjit.cpu.ECX == len(self.MYSTRING))
-        assert(self.myjit.cpu.EDI == self.myjit.ir_arch.symbol_pool.getby_name('mystr').offset + len(self.MYSTRING)+1)
+        mystr = self.myjit.ir_arch.loc_db.get_name_location('mystr')
+        assert(self.myjit.cpu.EDI == self.myjit.ir_arch.loc_db.get_location_offset(mystr) + len(self.MYSTRING)+1)
 
 
 class Test_MOVS(Asm_Test_32):
@@ -42,8 +43,10 @@ class Test_MOVS(Asm_Test_32):
 
     def check(self):
         assert(self.myjit.cpu.ECX == 0)
-        assert(self.myjit.cpu.EDI == self.myjit.ir_arch.symbol_pool.getby_name('buffer').offset + len(self.MYSTRING))
-        assert(self.myjit.cpu.ESI == self.myjit.ir_arch.symbol_pool.getby_name('mystr').offset + len(self.MYSTRING))
+        buffer = self.myjit.ir_arch.loc_db.get_name_location('buffer')
+        assert(self.myjit.cpu.EDI == self.myjit.ir_arch.loc_db.get_location_offset(buffer) + len(self.MYSTRING))
+        mystr = self.myjit.ir_arch.loc_db.get_name_location('mystr')
+        assert(self.myjit.cpu.ESI == self.myjit.ir_arch.loc_db.get_location_offset(mystr) + len(self.MYSTRING))
 
 
 if __name__ == "__main__":