diff options
Diffstat (limited to 'test/arch/x86')
| -rw-r--r-- | test/arch/x86/arch.py | 6 | ||||
| -rwxr-xr-x | test/arch/x86/sem.py | 16 | ||||
| -rw-r--r-- | test/arch/x86/unit/asm_test.py | 8 | ||||
| -rw-r--r-- | test/arch/x86/unit/mn_cdq.py | 38 | ||||
| -rwxr-xr-x | test/arch/x86/unit/mn_pushpop.py | 24 | ||||
| -rwxr-xr-x | test/arch/x86/unit/mn_strings.py | 12 |
6 files changed, 52 insertions, 52 deletions
diff --git a/test/arch/x86/arch.py b/test/arch/x86/arch.py index 1865ceba..43e973e1 100644 --- a/test/arch/x86/arch.py +++ b/test/arch/x86/arch.py @@ -5,9 +5,9 @@ from miasm2.arch.x86.arch import mn_x86, deref_mem_ad, \ base_expr, rmarg, print_size from miasm2.arch.x86.sem import ir_x86_16, ir_x86_32, ir_x86_64 from miasm2.core.bin_stream import bin_stream_str -from miasm2.core.asmblock import AsmSymbolPool +from miasm2.core.locationdb import LocationDB -symbol_pool = AsmSymbolPool() +loc_db = LocationDB() mylabel16 = m2_expr.ExprId('mylabel16', 16) mylabel32 = m2_expr.ExprId('mylabel32', 32) @@ -3063,7 +3063,7 @@ for mode, s, l, in reg_tests: print mn assert(str(mn).strip() == s) print 'fromstring', repr(s) - l = mn_x86.fromstring(s, symbol_pool, mode) + l = mn_x86.fromstring(s, loc_db, mode) print 'str args', [(str(x), x.size) for x in l.args] assert(str(l).strip(' ') == s) a = mn_x86.asm(l) diff --git a/test/arch/x86/sem.py b/test/arch/x86/sem.py index baa05341..23b22245 100755 --- a/test/arch/x86/sem.py +++ b/test/arch/x86/sem.py @@ -14,13 +14,13 @@ from miasm2.arch.x86.regs import * from miasm2.expression.expression import * from miasm2.expression.simplifications import expr_simp from miasm2.core import parse_asm, asmblock -from miasm2.core.asmblock import AsmSymbolPool +from miasm2.core.locationdb import LocationDB logging.getLogger('cpuhelper').setLevel(logging.ERROR) EXCLUDE_REGS = set([ir_32().IRDst, ir_64().IRDst]) -symbol_pool = AsmSymbolPool() +loc_db = LocationDB() m32 = 32 m64 = 64 @@ -38,7 +38,7 @@ def symb_exec(lbl, interm, inputstate, debug): if k not in EXCLUDE_REGS and regs_init.get(k, None) != v} def compute(ir, mode, asm, inputstate={}, debug=False): - instr = mn.fromstring(asm, symbol_pool, mode) + instr = mn.fromstring(asm, loc_db, mode) code = mn.asm(instr)[0] instr = mn.dis(code, mode) instr.offset = inputstate.get(EIP, 0) @@ -48,11 +48,11 @@ def compute(ir, mode, asm, inputstate={}, debug=False): def compute_txt(ir, mode, txt, inputstate={}, debug=False): - asmcfg, symbol_pool = parse_asm.parse_txt(mn, mode, txt) - symbol_pool.set_offset(symbol_pool.getby_name("main"), 0x0) - patches = asmblock.asm_resolve_final(mn, asmcfg, symbol_pool) - interm = ir(symbol_pool) - lbl = symbol_pool.getby_name("main") + asmcfg, loc_db = parse_asm.parse_txt(mn, mode, txt) + loc_db.set_offset(loc_db.getby_name("main"), 0x0) + patches = asmblock.asm_resolve_final(mn, asmcfg, loc_db) + interm = ir(loc_db) + lbl = loc_db.getby_name("main") for bbl in asmcfg.blocks: interm.add_block(bbl) return symb_exec(lbl, interm, inputstate, debug) diff --git a/test/arch/x86/unit/asm_test.py b/test/arch/x86/unit/asm_test.py index 4b802606..e626768d 100644 --- a/test/arch/x86/unit/asm_test.py +++ b/test/arch/x86/unit/asm_test.py @@ -40,12 +40,12 @@ class Asm_Test(object): assert(self.myjit.pc == self.ret_addr) def asm(self): - blocks, symbol_pool = parse_asm.parse_txt(mn_x86, self.arch_attrib, self.TXT, - symbol_pool = self.myjit.ir_arch.symbol_pool) + blocks, loc_db = parse_asm.parse_txt(mn_x86, self.arch_attrib, self.TXT, + loc_db = self.myjit.ir_arch.loc_db) # fix shellcode addr - symbol_pool.set_offset(symbol_pool.getby_name("main"), 0x0) + loc_db.set_offset(loc_db.getby_name("main"), 0x0) s = StrPatchwork() - patches = asmblock.asm_resolve_final(mn_x86, blocks, symbol_pool) + patches = asmblock.asm_resolve_final(mn_x86, blocks, loc_db) for offset, raw in patches.items(): s[offset] = raw diff --git a/test/arch/x86/unit/mn_cdq.py b/test/arch/x86/unit/mn_cdq.py index 15b73913..947b40bb 100644 --- a/test/arch/x86/unit/mn_cdq.py +++ b/test/arch/x86/unit/mn_cdq.py @@ -10,7 +10,7 @@ class Test_CBW_16(Asm_Test_16): MYSTRING = "test CBW 16" def prepare(self): - self.myjit.ir_arch.symbol_pool.add_location("lbl_ret", self.ret_addr) + self.myjit.ir_arch.loc_db.add_location("lbl_ret", self.ret_addr) def test_init(self): self.myjit.cpu.EAX = 0x87654321 @@ -31,7 +31,7 @@ class Test_CBW_16_signed(Asm_Test_16): MYSTRING = "test CBW 16 signed" def prepare(self): - self.myjit.ir_arch.symbol_pool.add_location("lbl_ret", self.ret_addr) + self.myjit.ir_arch.loc_db.add_location("lbl_ret", self.ret_addr) def test_init(self): self.myjit.cpu.EAX = 0x87654381 @@ -52,7 +52,7 @@ class Test_CBW_32(Asm_Test_32): MYSTRING = "test CBW 32" def prepare(self): - self.myjit.ir_arch.symbol_pool.add_location("lbl_ret", self.ret_addr) + self.myjit.ir_arch.loc_db.add_location("lbl_ret", self.ret_addr) def test_init(self): self.myjit.cpu.EAX = 0x87654321 @@ -73,7 +73,7 @@ class Test_CBW_32_signed(Asm_Test_32): MYSTRING = "test CBW 32 signed" def prepare(self): - self.myjit.ir_arch.symbol_pool.add_location("lbl_ret", self.ret_addr) + self.myjit.ir_arch.loc_db.add_location("lbl_ret", self.ret_addr) def test_init(self): self.myjit.cpu.EAX = 0x87654381 @@ -94,7 +94,7 @@ class Test_CDQ_32(Asm_Test_32): MYSTRING = "test cdq 32" def prepare(self): - self.myjit.ir_arch.symbol_pool.add_location("lbl_ret", self.ret_addr) + self.myjit.ir_arch.loc_db.add_location("lbl_ret", self.ret_addr) def test_init(self): self.myjit.cpu.EAX = 0x77654321 @@ -115,7 +115,7 @@ class Test_CDQ_32_signed(Asm_Test_32): MYSTRING = "test cdq 32 signed" def prepare(self): - self.myjit.ir_arch.symbol_pool.add_location("lbl_ret", self.ret_addr) + self.myjit.ir_arch.loc_db.add_location("lbl_ret", self.ret_addr) def test_init(self): self.myjit.cpu.EAX = 0x87654321 @@ -136,7 +136,7 @@ class Test_CDQ_64(Asm_Test_64): MYSTRING = "test cdq 64" def prepare(self): - self.myjit.ir_arch.symbol_pool.add_location("lbl_ret", self.ret_addr) + self.myjit.ir_arch.loc_db.add_location("lbl_ret", self.ret_addr) def test_init(self): self.myjit.cpu.RAX = 0x1234567877654321 @@ -157,7 +157,7 @@ class Test_CDQ_64_signed(Asm_Test_64): MYSTRING = "test cdq 64 signed" def prepare(self): - self.myjit.ir_arch.symbol_pool.add_location("lbl_ret", self.ret_addr) + self.myjit.ir_arch.loc_db.add_location("lbl_ret", self.ret_addr) def test_init(self): self.myjit.cpu.RAX = 0x1234567887654321 @@ -178,7 +178,7 @@ class Test_CDQE_64(Asm_Test_64): MYSTRING = "test cdq 64" def prepare(self): - self.myjit.ir_arch.symbol_pool.add_location("lbl_ret", self.ret_addr) + self.myjit.ir_arch.loc_db.add_location("lbl_ret", self.ret_addr) def test_init(self): self.myjit.cpu.RAX = 0x1234567877654321 @@ -199,7 +199,7 @@ class Test_CDQE_64_signed(Asm_Test_64): MYSTRING = "test cdq 64 signed" def prepare(self): - self.myjit.ir_arch.symbol_pool.add_location("lbl_ret", self.ret_addr) + self.myjit.ir_arch.loc_db.add_location("lbl_ret", self.ret_addr) def test_init(self): self.myjit.cpu.RAX = 0x1234567887654321 @@ -220,7 +220,7 @@ class Test_CWD_32(Asm_Test_32): MYSTRING = "test cdq 32" def prepare(self): - self.myjit.ir_arch.symbol_pool.add_location("lbl_ret", self.ret_addr) + self.myjit.ir_arch.loc_db.add_location("lbl_ret", self.ret_addr) def test_init(self): self.myjit.cpu.EAX = 0x87654321 @@ -241,7 +241,7 @@ class Test_CWD_32_signed(Asm_Test_32): MYSTRING = "test cdq 32" def prepare(self): - self.myjit.ir_arch.symbol_pool.add_location("lbl_ret", self.ret_addr) + self.myjit.ir_arch.loc_db.add_location("lbl_ret", self.ret_addr) def test_init(self): self.myjit.cpu.EAX = 0x87658321 @@ -262,7 +262,7 @@ class Test_CWD_32(Asm_Test_32): MYSTRING = "test cdq 32" def prepare(self): - self.myjit.ir_arch.symbol_pool.add_location("lbl_ret", self.ret_addr) + self.myjit.ir_arch.loc_db.add_location("lbl_ret", self.ret_addr) def test_init(self): self.myjit.cpu.EAX = 0x87654321 @@ -283,7 +283,7 @@ class Test_CWDE_32(Asm_Test_32): MYSTRING = "test cwde 32" def prepare(self): - self.myjit.ir_arch.symbol_pool.add_location("lbl_ret", self.ret_addr) + self.myjit.ir_arch.loc_db.add_location("lbl_ret", self.ret_addr) def test_init(self): self.myjit.cpu.EAX = 0x87654321 @@ -304,7 +304,7 @@ class Test_CWDE_32_signed(Asm_Test_32): MYSTRING = "test cwde 32 signed" def prepare(self): - self.myjit.ir_arch.symbol_pool.add_location("lbl_ret", self.ret_addr) + self.myjit.ir_arch.loc_db.add_location("lbl_ret", self.ret_addr) def test_init(self): self.myjit.cpu.RAX = 0x87658321 @@ -325,7 +325,7 @@ class Test_CWDE_64(Asm_Test_64): MYSTRING = "test cwde 64" def prepare(self): - self.myjit.ir_arch.symbol_pool.add_location("lbl_ret", self.ret_addr) + self.myjit.ir_arch.loc_db.add_location("lbl_ret", self.ret_addr) def test_init(self): self.myjit.cpu.RAX = 0x1234567887654321 @@ -346,7 +346,7 @@ class Test_CWDE_64_signed(Asm_Test_64): MYSTRING = "test cwde 64 signed" def prepare(self): - self.myjit.ir_arch.symbol_pool.add_location("lbl_ret", self.ret_addr) + self.myjit.ir_arch.loc_db.add_location("lbl_ret", self.ret_addr) def test_init(self): self.myjit.cpu.RAX = 0x1234567887658321 @@ -367,7 +367,7 @@ class Test_CQO_64(Asm_Test_64): MYSTRING = "test cwde 64" def prepare(self): - self.myjit.ir_arch.symbol_pool.add_location("lbl_ret", self.ret_addr) + self.myjit.ir_arch.loc_db.add_location("lbl_ret", self.ret_addr) def test_init(self): self.myjit.cpu.RAX = 0x1234567887654321 @@ -388,7 +388,7 @@ class Test_CQO_64_signed(Asm_Test_64): MYSTRING = "test cwde 64 signed" def prepare(self): - self.myjit.ir_arch.symbol_pool.add_location("lbl_ret", self.ret_addr) + self.myjit.ir_arch.loc_db.add_location("lbl_ret", self.ret_addr) def test_init(self): self.myjit.cpu.RAX = 0x8234567887658321 diff --git a/test/arch/x86/unit/mn_pushpop.py b/test/arch/x86/unit/mn_pushpop.py index bed70ea3..6e9005ca 100755 --- a/test/arch/x86/unit/mn_pushpop.py +++ b/test/arch/x86/unit/mn_pushpop.py @@ -21,7 +21,7 @@ class Test_PUSHAD_32(Asm_Test_32): MYSTRING = "test pushad 32" def prepare(self): - self.myjit.ir_arch.symbol_pool.add_location("lbl_ret", self.ret_addr) + self.myjit.ir_arch.loc_db.add_location("lbl_ret", self.ret_addr) def test_init(self): init_regs(self) @@ -48,7 +48,7 @@ class Test_PUSHA_32(Asm_Test_32): MYSTRING = "test pusha 32" def prepare(self): - self.myjit.ir_arch.symbol_pool.add_location("lbl_ret", self.ret_addr) + self.myjit.ir_arch.loc_db.add_location("lbl_ret", self.ret_addr) def test_init(self): init_regs(self) @@ -75,7 +75,7 @@ class Test_PUSHA_16(Asm_Test_16): MYSTRING = "test pusha 16" def prepare(self): - self.myjit.ir_arch.symbol_pool.add_location("lbl_ret", self.ret_addr) + self.myjit.ir_arch.loc_db.add_location("lbl_ret", self.ret_addr) def test_init(self): init_regs(self) @@ -102,7 +102,7 @@ class Test_PUSHAD_16(Asm_Test_16): MYSTRING = "test pushad 16" def prepare(self): - self.myjit.ir_arch.symbol_pool.add_location("lbl_ret", self.ret_addr) + self.myjit.ir_arch.loc_db.add_location("lbl_ret", self.ret_addr) def test_init(self): init_regs(self) @@ -129,7 +129,7 @@ class Test_PUSH_mode32_32(Asm_Test_32): MYSTRING = "test push mode32 32" def prepare(self): - self.myjit.ir_arch.symbol_pool.add_location("lbl_ret", self.ret_addr) + self.myjit.ir_arch.loc_db.add_location("lbl_ret", self.ret_addr) def test_init(self): init_regs(self) @@ -152,7 +152,7 @@ class Test_PUSH_mode32_16(Asm_Test_32): MYSTRING = "test push mode32 16" def prepare(self): - self.myjit.ir_arch.symbol_pool.add_location("lbl_ret", self.ret_addr) + self.myjit.ir_arch.loc_db.add_location("lbl_ret", self.ret_addr) def test_init(self): init_regs(self) @@ -175,7 +175,7 @@ class Test_PUSH_mode16_16(Asm_Test_16): MYSTRING = "test push mode16 16" def prepare(self): - self.myjit.ir_arch.symbol_pool.add_location("lbl_ret", self.ret_addr) + self.myjit.ir_arch.loc_db.add_location("lbl_ret", self.ret_addr) def test_init(self): init_regs(self) @@ -198,7 +198,7 @@ class Test_PUSH_mode16_32(Asm_Test_16): MYSTRING = "test push mode16 32" def prepare(self): - self.myjit.ir_arch.symbol_pool.add_location("lbl_ret", self.ret_addr) + self.myjit.ir_arch.loc_db.add_location("lbl_ret", self.ret_addr) def test_init(self): init_regs(self) @@ -221,7 +221,7 @@ class Test_POP_mode32_32(Asm_Test_32): MYSTRING = "test pop mode32 32" def prepare(self): - self.myjit.ir_arch.symbol_pool.add_location("lbl_ret", self.ret_addr) + self.myjit.ir_arch.loc_db.add_location("lbl_ret", self.ret_addr) def test_init(self): self.value = 0x11223344 @@ -243,7 +243,7 @@ class Test_POP_mode32_16(Asm_Test_32): MYSTRING = "test pop mode32 16" def prepare(self): - self.myjit.ir_arch.symbol_pool.add_location("lbl_ret", self.ret_addr) + self.myjit.ir_arch.loc_db.add_location("lbl_ret", self.ret_addr) def test_init(self): self.value = 0x1122 @@ -265,7 +265,7 @@ class Test_POP_mode16_16(Asm_Test_16): MYSTRING = "test pop mode16 16" def prepare(self): - self.myjit.ir_arch.symbol_pool.add_location("lbl_ret", self.ret_addr) + self.myjit.ir_arch.loc_db.add_location("lbl_ret", self.ret_addr) def test_init(self): self.value = 0x1122 @@ -287,7 +287,7 @@ class Test_POP_mode16_32(Asm_Test_16): MYSTRING = "test pop mode16 32" def prepare(self): - self.myjit.ir_arch.symbol_pool.add_location("lbl_ret", self.ret_addr) + self.myjit.ir_arch.loc_db.add_location("lbl_ret", self.ret_addr) def test_init(self): self.value = 0x11223344 diff --git a/test/arch/x86/unit/mn_strings.py b/test/arch/x86/unit/mn_strings.py index 44da0a70..a6facd08 100755 --- a/test/arch/x86/unit/mn_strings.py +++ b/test/arch/x86/unit/mn_strings.py @@ -21,8 +21,8 @@ class Test_SCAS(Asm_Test_32): def check(self): assert(self.myjit.cpu.ECX == len(self.MYSTRING)) - mystr = self.myjit.ir_arch.symbol_pool.getby_name('mystr') - assert(self.myjit.cpu.EDI == self.myjit.ir_arch.symbol_pool.loc_key_to_offset(mystr) + len(self.MYSTRING)+1) + mystr = self.myjit.ir_arch.loc_db.getby_name('mystr') + assert(self.myjit.cpu.EDI == self.myjit.ir_arch.loc_db.loc_key_to_offset(mystr) + len(self.MYSTRING)+1) class Test_MOVS(Asm_Test_32): @@ -43,10 +43,10 @@ class Test_MOVS(Asm_Test_32): def check(self): assert(self.myjit.cpu.ECX == 0) - buffer = self.myjit.ir_arch.symbol_pool.getby_name('buffer') - assert(self.myjit.cpu.EDI == self.myjit.ir_arch.symbol_pool.loc_key_to_offset(buffer) + len(self.MYSTRING)) - mystr = self.myjit.ir_arch.symbol_pool.getby_name('mystr') - assert(self.myjit.cpu.ESI == self.myjit.ir_arch.symbol_pool.loc_key_to_offset(mystr) + len(self.MYSTRING)) + buffer = self.myjit.ir_arch.loc_db.getby_name('buffer') + assert(self.myjit.cpu.EDI == self.myjit.ir_arch.loc_db.loc_key_to_offset(buffer) + len(self.MYSTRING)) + mystr = self.myjit.ir_arch.loc_db.getby_name('mystr') + assert(self.myjit.cpu.ESI == self.myjit.ir_arch.loc_db.loc_key_to_offset(mystr) + len(self.MYSTRING)) if __name__ == "__main__": |